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Changed reset mode to asynchronous for soft_latch.sv
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soft_latch.sv

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
//------------------------------------------------------------------------------
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// soft_latch.sv
3+
// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, [email protected]
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//------------------------------------------------------------------------------
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@@ -40,7 +41,7 @@ soft_latch #(
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.WIDTH( 16 )
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) SL1 (
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.clk( clk ),
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.nrst( 1'b1 ),
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.anrst( 1'b1 ),
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.latch( ),
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.in( ),
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.out( )
@@ -50,10 +51,10 @@ soft_latch #(
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module soft_latch #( parameter
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WIDTH = 1 // data width
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bit [7:0] WIDTH = 1 // data width
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)(
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input clk, // clock
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input nrst, // inverted reset
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input anrst, // inverted reset
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input latch, // latch strobe
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input [WIDTH-1:0] in, // data in
@@ -63,8 +64,8 @@ module soft_latch #( parameter
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logic [WIDTH-1:0] in_buf = '0;
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// buffering input data
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always_ff @(posedge clk) begin
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if( ~nrst ) begin
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always_ff @(posedge clk or negedge anrst) begin
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if( ~anrst ) begin
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in_buf[WIDTH-1:0] <= '0;
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end else if( latch ) begin
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in_buf[WIDTH-1:0] <= in[WIDTH-1:0];
@@ -73,7 +74,7 @@ end
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// mixing combinational and buffered data to the output
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always_comb begin
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if( ~nrst ) begin
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if( ~anrst ) begin
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out[WIDTH-1:0] <= '0;
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end else if( latch ) begin
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out[WIDTH-1:0] <= in[WIDTH-1:0];

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