@@ -290,6 +290,7 @@ static void smmuv3_init_regs(SMMUv3State *s)
290
290
}
291
291
s -> idr [3 ] = FIELD_DP32 (s -> idr [3 ], IDR3 , RIL , 1 );
292
292
s -> idr [3 ] = FIELD_DP32 (s -> idr [3 ], IDR3 , BBML , 2 );
293
+ s -> idr [3 ] = FIELD_DP32 (s -> idr [3 ], IDR3 , STT , 1 ); /* FEAT_TTST */
293
294
294
295
s -> idr [5 ] = FIELD_DP32 (s -> idr [5 ], IDR5 , OAS , SMMU_IDR5_OAS ); /* 44 bits */
295
296
/* 4K, 16K and 64K granule support */
@@ -358,7 +359,11 @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, SMMUTransCfg *cfg,
358
359
359
360
trace_smmuv3_get_cd (addr );
360
361
362
+ if (cfg -> stage == SMMU_STAGE_2 ) {
363
+ g_assert_not_reached ();
364
+ }
361
365
if (cfg -> stage == SMMU_NESTED ) {
366
+ g_assert_not_reached ();
362
367
status = smmuv3_do_translate (s , addr , cfg , event ,
363
368
IOMMU_RO , & entry , SMMU_CLASS_CD );
364
369
@@ -397,6 +402,7 @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, SMMUTransCfg *cfg,
397
402
*/
398
403
static bool s2t0sz_valid (SMMUTransCfg * cfg )
399
404
{
405
+ abort ();
400
406
if (cfg -> s2cfg .tsz > 39 ) {
401
407
return false;
402
408
}
0 commit comments