diff --git a/magma/primitives/mux.py b/magma/primitives/mux.py index d218b4d11..9db247bd8 100644 --- a/magma/primitives/mux.py +++ b/magma/primitives/mux.py @@ -1,16 +1,17 @@ import hwtypes as ht -from hwtypes import BitVector +from hwtypes import BitVector, UIntVector, SIntVector from magma.array import Array from magma.bit import Bit -from magma.bits import Bits +from magma.bits import Bits, UInt, SInt from magma.bitutils import clog2, seq2int from magma.circuit import coreir_port_mapping from magma.generator import Generator2 from magma.interface import IO from magma.protocol_type import MagmaProtocol, magma_type -from magma.t import Type, In, Out -from magma.tuple import Product +from magma.t import Type, In, Out, Direction +from magma.tuple import Product, Tuple from magma.conversions import tuple_ +from magma.wireable import wireable class CoreIRCommonLibMuxN(Generator2): @@ -84,18 +85,43 @@ def _infer_mux_type(args): Note that we do not infer from standard python int arguments because we cannot, in general, determine the correct bit width (use BitVector instead) """ + T = None for arg in args: if isinstance(arg, (Type, MagmaProtocol)): - return type(arg), args - if isinstance(arg, BitVector): - return Bits[len(arg)], args - if isinstance(arg, (ht.Bit, bool)): - return Bit, args - if isinstance(arg, tuple): - return type(tuple_(arg)), [tuple_(a) for a in args] - raise TypeError( - f"Could not infer mux type from {args}\n" - "Need at least one magma value, BitVector, bool or tuple") + next_T = type(arg).qualify(Direction.Undirected) + elif isinstance(arg, UIntVector): + next_T = UInt[len(arg)] + elif isinstance(arg, SIntVector): + next_T = SInt[len(arg)] + elif isinstance(arg, BitVector): + next_T = Bits[len(arg)] + elif isinstance(arg, (ht.Bit, bool)): + next_T = Bit + elif isinstance(arg, tuple): + next_T = type(tuple_(arg)) + elif isinstance(arg, int): + # Cannot infer type without width, use wiring implicit coercion to + # handle (or raise type error there) + continue + + if T is not None: + if issubclass(T, next_T): + # upcast + T = next_T + elif not wireable(next_T, T): + raise TypeError( + f"Found incompatible types {next_T} and {T} in mux" + " inference" + ) + else: + T = next_T + if T is None: + raise TypeError( + f"Could not infer mux type from {args}\n" + "Need at least one magma value, BitVector, bool or tuple") + if issubclass(T, Tuple): + args = [tuple_(a) for a in args] + return T, args def mux(I: list, S, **kwargs): diff --git a/magma/primitives/register.py b/magma/primitives/register.py index eb5ef8e47..f83e046c1 100644 --- a/magma/primitives/register.py +++ b/magma/primitives/register.py @@ -16,6 +16,7 @@ AsyncReset, AsyncResetN, Clock, get_reset_args) from magma.clock_io import ClockIO from magma.primitives.mux import Mux +from magma.wireable import wireable class _CoreIRRegister(Generator2): @@ -109,18 +110,6 @@ def _get_T_from_init(init): raise ValueError("Could not infer register type from {init}") -def _can_wire_types(T1, T2): - if issubclass(T1, Tuple): - if not issubclass(T2, Tuple): - return False - return all(_can_wire_types(t1, t2) for t1, t2 in zip(T1, T2)) - if issubclass(T1, Array): - if not issubclass(T2, Array): - return False - return _can_wire_types(T1.T, T2.T) - return issubclass(T1, T2) or issubclass(T1, T2) - - def _check_init_T(init, T): init_T = _get_T_from_init(init) if isinstance(init, int) and issubclass(T, Bits): @@ -134,7 +123,7 @@ def _check_init_T(init, T): if len(init_T) > 1: return False return True - return _can_wire_types(init_T, T) + return wireable(init_T, T) class Register(Generator2): diff --git a/magma/wireable.py b/magma/wireable.py new file mode 100644 index 000000000..37a651c09 --- /dev/null +++ b/magma/wireable.py @@ -0,0 +1,19 @@ +from magma.array import Array +from magma.tuple import Tuple +from magma.protocol_type import magma_type + + +def wireable(T1, T2): + """ + Returns true if T1 can be wired to T2 + """ + T1, T2 = magma_type(T1), magma_type(T2) + if issubclass(T1, Tuple): + if not issubclass(T2, Tuple): + return False + return all(wireable(t1, t2) for t1, t2 in zip(T1, T2)) + if issubclass(T1, Array): + if not issubclass(T2, Array): + return False + return wireable(T1.T, T2.T) + return issubclass(T1, T2) or issubclass(T1, T2) diff --git a/tests/test_errors/test_mux_errors.py b/tests/test_errors/test_mux_errors.py index c44260c73..7d38b7554 100644 --- a/tests/test_errors/test_mux_errors.py +++ b/tests/test_errors/test_mux_errors.py @@ -22,5 +22,5 @@ class Foo(m.Circuit): with pytest.raises(TypeError) as e: m.mux([io.I0, io.I1], io.S) assert str(e.value) == f"""\ -mux arg I[1] (I1: Out(Bits[3])) does not match inferred input port type Out(Bits[2])\ +mux arg I[1] (I1: Out(Bits[3])) does not match inferred input port type Bits[2]\ """ diff --git a/tests/test_issues/gold/test_708_inline_False.v b/tests/test_issues/gold/test_708_inline_False.v index 4ffdc5fe0..4a1d3924c 100644 --- a/tests/test_issues/gold/test_708_inline_False.v +++ b/tests/test_issues/gold/test_708_inline_False.v @@ -64,7 +64,7 @@ coreir_mux #( assign out = _join_out; endmodule -module Mux2xTuplex_OutUInt8 ( +module Mux2xTuplex_UInt8 ( input [7:0] I0_x, input [7:0] I1_x, output [7:0] O_x, @@ -86,13 +86,13 @@ module Test_comb ( input c, input [7:0] self_a_O_x ); -wire [7:0] Mux2xTuplex_OutUInt8_inst0_O_x; +wire [7:0] Mux2xTuplex_UInt8_inst0_O_x; wire [7:0] const_1_8_out; wire [7:0] magma_Bits_8_add_inst0_out; -Mux2xTuplex_OutUInt8 Mux2xTuplex_OutUInt8_inst0 ( +Mux2xTuplex_UInt8 Mux2xTuplex_UInt8_inst0 ( .I0_x(self_a_O_x), .I1_x(magma_Bits_8_add_inst0_out), - .O_x(Mux2xTuplex_OutUInt8_inst0_O_x), + .O_x(Mux2xTuplex_UInt8_inst0_O_x), .S(c) ); coreir_const #( @@ -109,7 +109,7 @@ coreir_add #( .out(magma_Bits_8_add_inst0_out) ); assign O0_x = self_a_O_x; -assign O1_a_x = Mux2xTuplex_OutUInt8_inst0_O_x; +assign O1_a_x = Mux2xTuplex_UInt8_inst0_O_x; endmodule module Test ( diff --git a/tests/test_issues/gold/test_708_inline_True.v b/tests/test_issues/gold/test_708_inline_True.v index 92e32b4b1..e81d9c966 100644 --- a/tests/test_issues/gold/test_708_inline_True.v +++ b/tests/test_issues/gold/test_708_inline_True.v @@ -16,7 +16,7 @@ module coreir_reg #( assign out = outReg; endmodule -module Mux2xTuplex_OutUInt8 ( +module Mux2xTuplex_UInt8 ( input [7:0] I0_x, input [7:0] I1_x, output [7:0] O_x, @@ -41,7 +41,7 @@ module Test_comb ( input [7:0] self_a_O_x ); wire [7:0] magma_Bits_8_add_inst0_out; -Mux2xTuplex_OutUInt8 Mux2xTuplex_OutUInt8_inst0 ( +Mux2xTuplex_UInt8 Mux2xTuplex_UInt8_inst0 ( .I0_x(self_a_O_x), .I1_x(magma_Bits_8_add_inst0_out), .O_x(O1_a_x), diff --git a/tests/test_operators/gold/TestSlice.v b/tests/test_operators/gold/TestSlice.v index feca854af..ae31a1746 100644 --- a/tests/test_operators/gold/TestSlice.v +++ b/tests/test_operators/gold/TestSlice.v @@ -90,7 +90,7 @@ coreir_slice #( assign out = _join_out; endmodule -module Mux4xOutBits6 ( +module Mux4xBits6 ( input [5:0] I0, input [5:0] I1, input [5:0] I2, @@ -117,15 +117,15 @@ module TestSlice ( input [1:0] x, output [5:0] O ); -wire [5:0] Mux4xOutBits6_inst0_O; -Mux4xOutBits6 Mux4xOutBits6_inst0 ( +wire [5:0] Mux4xBits6_inst0_O; +Mux4xBits6 Mux4xBits6_inst0 ( .I0(I[5:0]), .I1(I[6:1]), .I2(I[7:2]), .I3(I[8:3]), .S(x), - .O(Mux4xOutBits6_inst0_O) + .O(Mux4xBits6_inst0_O) ); -assign O = Mux4xOutBits6_inst0_O; +assign O = Mux4xBits6_inst0_O; endmodule diff --git a/tests/test_primitives/gold/test_mux_operator.v b/tests/test_primitives/gold/test_mux_operator.v index 28946bd93..4fcfa2f14 100644 --- a/tests/test_primitives/gold/test_mux_operator.v +++ b/tests/test_primitives/gold/test_mux_operator.v @@ -26,7 +26,7 @@ coreir_mux #( assign out = _join_out; endmodule -module Mux2xOutBit ( +module Mux2xBit ( input I0, input I1, input S, @@ -49,13 +49,13 @@ module test_mux_operator ( input S, output O ); -wire Mux2xOutBit_inst0_O; -Mux2xOutBit Mux2xOutBit_inst0 ( +wire Mux2xBit_inst0_O; +Mux2xBit Mux2xBit_inst0 ( .I0(I[0]), .I1(I[1]), .S(S), - .O(Mux2xOutBit_inst0_O) + .O(Mux2xBit_inst0_O) ); -assign O = Mux2xOutBit_inst0_O; +assign O = Mux2xBit_inst0_O; endmodule diff --git a/tests/test_primitives/gold/test_mux_operator_int.v b/tests/test_primitives/gold/test_mux_operator_int.v index a142aa412..ac8cc67df 100644 --- a/tests/test_primitives/gold/test_mux_operator_int.v +++ b/tests/test_primitives/gold/test_mux_operator_int.v @@ -34,7 +34,7 @@ coreir_mux #( assign out = _join_out; endmodule -module Mux2xOutBit ( +module Mux2xBit ( input I0, input I1, input S, @@ -57,19 +57,19 @@ module test_mux_operator_int ( input S, output O ); -wire Mux2xOutBit_inst0_O; +wire Mux2xBit_inst0_O; wire bit_const_0_None_out; -Mux2xOutBit Mux2xOutBit_inst0 ( +Mux2xBit Mux2xBit_inst0 ( .I0(bit_const_0_None_out), .I1(I), .S(S), - .O(Mux2xOutBit_inst0_O) + .O(Mux2xBit_inst0_O) ); corebit_const #( .value(1'b0) ) bit_const_0_None ( .out(bit_const_0_None_out) ); -assign O = Mux2xOutBit_inst0_O; +assign O = Mux2xBit_inst0_O; endmodule diff --git a/tests/test_primitives/test_mux.py b/tests/test_primitives/test_mux.py index c8a9b4e59..03f3284b0 100644 --- a/tests/test_primitives/test_mux.py +++ b/tests/test_primitives/test_mux.py @@ -1,4 +1,5 @@ import os +import pytest from hwtypes import BitVector import hwtypes as ht @@ -293,3 +294,18 @@ class test_mux_array_select_bits_1(m.Circuit): tester.compile_and_run("verilator", skip_compile=True, directory=os.path.join(os.path.dirname(__file__), "build")) + + +@pytest.mark.parametrize("ht_T, m_T", [(ht.UIntVector, m.UInt), + (ht.SIntVector, m.SInt)]) +def test_mux_intv(ht_T, m_T): + class Main(m.Circuit): + O = m.mux([ht_T[4](1), m_T[4](2)], m.Bit()) + assert isinstance(O, m_T) + + +@pytest.mark.parametrize("ht_T", [ht.UIntVector, ht.SIntVector]) +def test_mux_intv_bits(ht_T): + class Main(m.Circuit): + O = m.mux([ht_T[4](1), m.Bits[4](2)], m.Bit()) + assert type(O) is m.Out(m.Bits[4]) diff --git a/tests/test_syntax/gold/RdPtr.json b/tests/test_syntax/gold/RdPtr.json index bb68f7628..b99fa9790 100644 --- a/tests/test_syntax/gold/RdPtr.json +++ b/tests/test_syntax/gold/RdPtr.json @@ -2,7 +2,7 @@ "namespaces":{ "global":{ "modules":{ - "Mux2xOutUInt10":{ + "Mux2xUInt10":{ "type":["Record",[ ["I0",["Array",10,"BitIn"]], ["I1",["Array",10,"BitIn"]], @@ -56,8 +56,8 @@ ["O1",["Array",10,"Bit"]] ]], "instances":{ - "Mux2xOutUInt10_inst0":{ - "modref":"global.Mux2xOutUInt10" + "Mux2xUInt10_inst0":{ + "modref":"global.Mux2xUInt10" }, "const_1_10":{ "genref":"coreir.const", @@ -70,10 +70,10 @@ } }, "connections":[ - ["self.self_rd_ptr_O","Mux2xOutUInt10_inst0.I0"], - ["magma_Bits_10_add_inst0.out","Mux2xOutUInt10_inst0.I1"], - ["self.O0","Mux2xOutUInt10_inst0.O"], - ["self.read","Mux2xOutUInt10_inst0.S"], + ["self.self_rd_ptr_O","Mux2xUInt10_inst0.I0"], + ["magma_Bits_10_add_inst0.out","Mux2xUInt10_inst0.I1"], + ["self.O0","Mux2xUInt10_inst0.O"], + ["self.read","Mux2xUInt10_inst0.S"], ["magma_Bits_10_add_inst0.in1","const_1_10.out"], ["self.self_rd_ptr_O","magma_Bits_10_add_inst0.in0"], ["self.self_rd_ptr_O","self.O1"] diff --git a/tests/test_syntax/gold/RdPtr.v b/tests/test_syntax/gold/RdPtr.v index cd0e4bd59..dd8a04f39 100644 --- a/tests/test_syntax/gold/RdPtr.v +++ b/tests/test_syntax/gold/RdPtr.v @@ -68,7 +68,7 @@ coreir_mux #( assign out = _join_out; endmodule -module Mux2xOutUInt10 ( +module Mux2xUInt10 ( input [9:0] I0, input [9:0] I1, input S, @@ -92,14 +92,14 @@ module RdPtr_comb ( output [9:0] O0, output [9:0] O1 ); -wire [9:0] Mux2xOutUInt10_inst0_O; +wire [9:0] Mux2xUInt10_inst0_O; wire [9:0] const_1_10_out; wire [9:0] magma_Bits_10_add_inst0_out; -Mux2xOutUInt10 Mux2xOutUInt10_inst0 ( +Mux2xUInt10 Mux2xUInt10_inst0 ( .I0(self_rd_ptr_O), .I1(magma_Bits_10_add_inst0_out), .S(read), - .O(Mux2xOutUInt10_inst0_O) + .O(Mux2xUInt10_inst0_O) ); coreir_const #( .value(10'h001), @@ -114,7 +114,7 @@ coreir_add #( .in1(const_1_10_out), .out(magma_Bits_10_add_inst0_out) ); -assign O0 = Mux2xOutUInt10_inst0_O; +assign O0 = Mux2xUInt10_inst0_O; assign O1 = self_rd_ptr_O; endmodule diff --git a/tests/test_syntax/gold/RegisterMode.json b/tests/test_syntax/gold/RegisterMode.json index b770870cb..94c4d0bea 100644 --- a/tests/test_syntax/gold/RegisterMode.json +++ b/tests/test_syntax/gold/RegisterMode.json @@ -2,7 +2,7 @@ "namespaces":{ "global":{ "modules":{ - "Mux2xOutBit":{ + "Mux2xBit":{ "type":["Record",[ ["I0","BitIn"], ["I1","BitIn"], @@ -22,7 +22,7 @@ ["self.O","coreir_commonlib_mux2x1_inst0.out.0"] ] }, - "Mux2xOutBits4":{ + "Mux2xBits4":{ "type":["Record",[ ["I0",["Array",4,"BitIn"]], ["I1",["Array",4,"BitIn"]], @@ -118,68 +118,68 @@ ["O3",["Array",4,"Bit"]] ]], "instances":{ - "Mux2xOutBit_inst0":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst0":{ + "modref":"global.Mux2xBit" }, - "Mux2xOutBit_inst1":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst1":{ + "modref":"global.Mux2xBit" }, - "Mux2xOutBit_inst2":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst2":{ + "modref":"global.Mux2xBit" }, - "Mux2xOutBit_inst3":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst3":{ + "modref":"global.Mux2xBit" }, - "Mux2xOutBit_inst4":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst4":{ + "modref":"global.Mux2xBit" }, - "Mux2xOutBit_inst5":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst5":{ + "modref":"global.Mux2xBit" }, - "Mux2xOutBits4_inst0":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst0":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst1":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst1":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst10":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst10":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst11":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst11":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst12":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst12":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst13":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst13":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst14":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst14":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst2":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst2":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst3":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst3":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst4":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst4":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst5":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst5":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst6":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst6":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst7":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst7":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst8":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst8":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst9":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst9":{ + "modref":"global.Mux2xBits4" }, "bit_const_0_None":{ "modref":"corebit.const", @@ -435,73 +435,73 @@ } }, "connections":[ - ["self.clk_en","Mux2xOutBit_inst0.I0"], - ["bit_const_0_None.out","Mux2xOutBit_inst0.I1"], - ["Mux2xOutBit_inst1.I0","Mux2xOutBit_inst0.O"], - ["magma_Bits_2_eq_inst1.out","Mux2xOutBit_inst0.S"], - ["bit_const_0_None.out","Mux2xOutBit_inst1.I1"], - ["Mux2xOutBit_inst2.I0","Mux2xOutBit_inst1.O"], - ["magma_Bits_2_eq_inst4.out","Mux2xOutBit_inst1.S"], - ["bit_const_1_None.out","Mux2xOutBit_inst2.I1"], - ["magma_Bit_not_inst1.out","Mux2xOutBit_inst2.S"], - ["self.clk_en","Mux2xOutBit_inst3.I0"], - ["bit_const_0_None.out","Mux2xOutBit_inst3.I1"], - ["Mux2xOutBit_inst4.I0","Mux2xOutBit_inst3.O"], - ["magma_Bit_and_inst3.out","Mux2xOutBit_inst3.S"], - ["bit_const_0_None.out","Mux2xOutBit_inst4.I1"], - ["Mux2xOutBit_inst5.I0","Mux2xOutBit_inst4.O"], - ["magma_Bit_and_inst9.out","Mux2xOutBit_inst4.S"], - ["bit_const_1_None.out","Mux2xOutBit_inst5.I1"], - ["self.O1","Mux2xOutBit_inst5.O"], - ["magma_Bit_not_inst24.out","Mux2xOutBit_inst5.S"], - ["self.value","Mux2xOutBits4_inst0.I0"], - ["self.value","Mux2xOutBits4_inst0.I1"], - ["Mux2xOutBits4_inst2.I0","Mux2xOutBits4_inst0.O"], - ["magma_Bits_2_eq_inst0.out","Mux2xOutBits4_inst0.S"], - ["self.self_register_O","Mux2xOutBits4_inst1.I0"], - ["self.self_register_O","Mux2xOutBits4_inst1.I1"], - ["Mux2xOutBits4_inst3.I0","Mux2xOutBits4_inst1.O"], - ["magma_Bits_2_eq_inst2.out","Mux2xOutBits4_inst1.S"], - ["Mux2xOutBits4_inst7.O","Mux2xOutBits4_inst10.I0"], - ["self.const_","Mux2xOutBits4_inst10.I1"], - ["Mux2xOutBits4_inst13.I0","Mux2xOutBits4_inst10.O"], - ["magma_Bit_and_inst10.out","Mux2xOutBits4_inst10.S"], - ["Mux2xOutBits4_inst8.O","Mux2xOutBits4_inst11.I0"], - ["self.self_register_O","Mux2xOutBits4_inst11.I1"], - ["Mux2xOutBits4_inst14.I0","Mux2xOutBits4_inst11.O"], - ["magma_Bit_and_inst11.out","Mux2xOutBits4_inst11.S"], - ["Mux2xOutBits4_inst9.O","Mux2xOutBits4_inst12.I0"], - ["self.config_data","Mux2xOutBits4_inst12.I1"], - ["self.O0","Mux2xOutBits4_inst12.O"], - ["magma_Bit_not_inst23.out","Mux2xOutBits4_inst12.S"], - ["self.self_register_O","Mux2xOutBits4_inst13.I1"], - ["self.O2","Mux2xOutBits4_inst13.O"], - ["magma_Bit_not_inst25.out","Mux2xOutBits4_inst13.S"], - ["self.self_register_O","Mux2xOutBits4_inst14.I1"], - ["self.O3","Mux2xOutBits4_inst14.O"], - ["magma_Bit_not_inst26.out","Mux2xOutBits4_inst14.S"], - ["self.value","Mux2xOutBits4_inst2.I1"], - ["Mux2xOutBits4_inst4.I0","Mux2xOutBits4_inst2.O"], - ["magma_Bits_2_eq_inst3.out","Mux2xOutBits4_inst2.S"], - ["self.self_register_O","Mux2xOutBits4_inst3.I1"], - ["Mux2xOutBits4_inst5.I0","Mux2xOutBits4_inst3.O"], - ["magma_Bits_2_eq_inst5.out","Mux2xOutBits4_inst3.S"], - ["self.config_data","Mux2xOutBits4_inst4.I1"], - ["magma_Bit_not_inst0.out","Mux2xOutBits4_inst4.S"], - ["self.self_register_O","Mux2xOutBits4_inst5.I1"], - ["magma_Bit_not_inst2.out","Mux2xOutBits4_inst5.S"], - ["self.value","Mux2xOutBits4_inst6.I0"], - ["self.value","Mux2xOutBits4_inst6.I1"], - ["Mux2xOutBits4_inst9.I0","Mux2xOutBits4_inst6.O"], - ["magma_Bit_and_inst1.out","Mux2xOutBits4_inst6.S"], - ["self.self_register_O","Mux2xOutBits4_inst7.I0"], - ["self.value","Mux2xOutBits4_inst7.I1"], - ["magma_Bit_and_inst5.out","Mux2xOutBits4_inst7.S"], - ["self.self_register_O","Mux2xOutBits4_inst8.I0"], - ["self.self_register_O","Mux2xOutBits4_inst8.I1"], - ["magma_Bit_and_inst7.out","Mux2xOutBits4_inst8.S"], - ["self.value","Mux2xOutBits4_inst9.I1"], - ["magma_Bit_and_inst8.out","Mux2xOutBits4_inst9.S"], + ["self.clk_en","Mux2xBit_inst0.I0"], + ["bit_const_0_None.out","Mux2xBit_inst0.I1"], + ["Mux2xBit_inst1.I0","Mux2xBit_inst0.O"], + ["magma_Bits_2_eq_inst1.out","Mux2xBit_inst0.S"], + ["bit_const_0_None.out","Mux2xBit_inst1.I1"], + ["Mux2xBit_inst2.I0","Mux2xBit_inst1.O"], + ["magma_Bits_2_eq_inst4.out","Mux2xBit_inst1.S"], + ["bit_const_1_None.out","Mux2xBit_inst2.I1"], + ["magma_Bit_not_inst1.out","Mux2xBit_inst2.S"], + ["self.clk_en","Mux2xBit_inst3.I0"], + ["bit_const_0_None.out","Mux2xBit_inst3.I1"], + ["Mux2xBit_inst4.I0","Mux2xBit_inst3.O"], + ["magma_Bit_and_inst3.out","Mux2xBit_inst3.S"], + ["bit_const_0_None.out","Mux2xBit_inst4.I1"], + ["Mux2xBit_inst5.I0","Mux2xBit_inst4.O"], + ["magma_Bit_and_inst9.out","Mux2xBit_inst4.S"], + ["bit_const_1_None.out","Mux2xBit_inst5.I1"], + ["self.O1","Mux2xBit_inst5.O"], + ["magma_Bit_not_inst24.out","Mux2xBit_inst5.S"], + ["self.value","Mux2xBits4_inst0.I0"], + ["self.value","Mux2xBits4_inst0.I1"], + ["Mux2xBits4_inst2.I0","Mux2xBits4_inst0.O"], + ["magma_Bits_2_eq_inst0.out","Mux2xBits4_inst0.S"], + ["self.self_register_O","Mux2xBits4_inst1.I0"], + ["self.self_register_O","Mux2xBits4_inst1.I1"], + ["Mux2xBits4_inst3.I0","Mux2xBits4_inst1.O"], + ["magma_Bits_2_eq_inst2.out","Mux2xBits4_inst1.S"], + ["Mux2xBits4_inst7.O","Mux2xBits4_inst10.I0"], + ["self.const_","Mux2xBits4_inst10.I1"], + ["Mux2xBits4_inst13.I0","Mux2xBits4_inst10.O"], + ["magma_Bit_and_inst10.out","Mux2xBits4_inst10.S"], + ["Mux2xBits4_inst8.O","Mux2xBits4_inst11.I0"], + ["self.self_register_O","Mux2xBits4_inst11.I1"], + ["Mux2xBits4_inst14.I0","Mux2xBits4_inst11.O"], + ["magma_Bit_and_inst11.out","Mux2xBits4_inst11.S"], + ["Mux2xBits4_inst9.O","Mux2xBits4_inst12.I0"], + ["self.config_data","Mux2xBits4_inst12.I1"], + ["self.O0","Mux2xBits4_inst12.O"], + ["magma_Bit_not_inst23.out","Mux2xBits4_inst12.S"], + ["self.self_register_O","Mux2xBits4_inst13.I1"], + ["self.O2","Mux2xBits4_inst13.O"], + ["magma_Bit_not_inst25.out","Mux2xBits4_inst13.S"], + ["self.self_register_O","Mux2xBits4_inst14.I1"], + ["self.O3","Mux2xBits4_inst14.O"], + ["magma_Bit_not_inst26.out","Mux2xBits4_inst14.S"], + ["self.value","Mux2xBits4_inst2.I1"], + ["Mux2xBits4_inst4.I0","Mux2xBits4_inst2.O"], + ["magma_Bits_2_eq_inst3.out","Mux2xBits4_inst2.S"], + ["self.self_register_O","Mux2xBits4_inst3.I1"], + ["Mux2xBits4_inst5.I0","Mux2xBits4_inst3.O"], + ["magma_Bits_2_eq_inst5.out","Mux2xBits4_inst3.S"], + ["self.config_data","Mux2xBits4_inst4.I1"], + ["magma_Bit_not_inst0.out","Mux2xBits4_inst4.S"], + ["self.self_register_O","Mux2xBits4_inst5.I1"], + ["magma_Bit_not_inst2.out","Mux2xBits4_inst5.S"], + ["self.value","Mux2xBits4_inst6.I0"], + ["self.value","Mux2xBits4_inst6.I1"], + ["Mux2xBits4_inst9.I0","Mux2xBits4_inst6.O"], + ["magma_Bit_and_inst1.out","Mux2xBits4_inst6.S"], + ["self.self_register_O","Mux2xBits4_inst7.I0"], + ["self.value","Mux2xBits4_inst7.I1"], + ["magma_Bit_and_inst5.out","Mux2xBits4_inst7.S"], + ["self.self_register_O","Mux2xBits4_inst8.I0"], + ["self.self_register_O","Mux2xBits4_inst8.I1"], + ["magma_Bit_and_inst7.out","Mux2xBits4_inst8.S"], + ["self.value","Mux2xBits4_inst9.I1"], + ["magma_Bit_and_inst8.out","Mux2xBits4_inst9.S"], ["magma_Bit_xor_inst0.in1","bit_const_1_None.out"], ["magma_Bit_xor_inst1.in1","bit_const_1_None.out"], ["magma_Bit_xor_inst10.in1","bit_const_1_None.out"], @@ -630,15 +630,15 @@ ["O1",["Array",4,"Bit"]] ]], "instances":{ - "Mux2xOutBits4_inst0":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst0":{ + "modref":"global.Mux2xBits4" } }, "connections":[ - ["self.self_value_O","Mux2xOutBits4_inst0.I0"], - ["self.value","Mux2xOutBits4_inst0.I1"], - ["self.O0","Mux2xOutBits4_inst0.O"], - ["self.en","Mux2xOutBits4_inst0.S"], + ["self.self_value_O","Mux2xBits4_inst0.I0"], + ["self.value","Mux2xBits4_inst0.I1"], + ["self.O0","Mux2xBits4_inst0.O"], + ["self.en","Mux2xBits4_inst0.S"], ["self.self_value_O","self.O1"] ] } diff --git a/tests/test_syntax/gold/RegisterMode.v b/tests/test_syntax/gold/RegisterMode.v index 8502c0908..8adb8834c 100644 --- a/tests/test_syntax/gold/RegisterMode.v +++ b/tests/test_syntax/gold/RegisterMode.v @@ -111,7 +111,7 @@ coreir_mux #( assign out = _join_out; endmodule -module Mux2xOutBits4 ( +module Mux2xBits4 ( input [3:0] I0, input [3:0] I1, input S, @@ -136,14 +136,14 @@ module Register_comb ( output [3:0] O0, output [3:0] O1 ); -wire [3:0] Mux2xOutBits4_inst0_O; -Mux2xOutBits4 Mux2xOutBits4_inst0 ( +wire [3:0] Mux2xBits4_inst0_O; +Mux2xBits4 Mux2xBits4_inst0 ( .I0(self_value_O), .I1(value), .S(en), - .O(Mux2xOutBits4_inst0_O) + .O(Mux2xBits4_inst0_O) ); -assign O0 = Mux2xOutBits4_inst0_O; +assign O0 = Mux2xBits4_inst0_O; assign O1 = self_value_O; endmodule @@ -175,7 +175,7 @@ coreir_reg #( assign O = Register_comb_inst0_O1; endmodule -module Mux2xOutBit ( +module Mux2xBit ( input I0, input I1, input S, @@ -206,27 +206,27 @@ module RegisterMode_comb ( output [3:0] O2, output [3:0] O3 ); -wire Mux2xOutBit_inst0_O; -wire Mux2xOutBit_inst1_O; -wire Mux2xOutBit_inst2_O; -wire Mux2xOutBit_inst3_O; -wire Mux2xOutBit_inst4_O; -wire Mux2xOutBit_inst5_O; -wire [3:0] Mux2xOutBits4_inst0_O; -wire [3:0] Mux2xOutBits4_inst1_O; -wire [3:0] Mux2xOutBits4_inst10_O; -wire [3:0] Mux2xOutBits4_inst11_O; -wire [3:0] Mux2xOutBits4_inst12_O; -wire [3:0] Mux2xOutBits4_inst13_O; -wire [3:0] Mux2xOutBits4_inst14_O; -wire [3:0] Mux2xOutBits4_inst2_O; -wire [3:0] Mux2xOutBits4_inst3_O; -wire [3:0] Mux2xOutBits4_inst4_O; -wire [3:0] Mux2xOutBits4_inst5_O; -wire [3:0] Mux2xOutBits4_inst6_O; -wire [3:0] Mux2xOutBits4_inst7_O; -wire [3:0] Mux2xOutBits4_inst8_O; -wire [3:0] Mux2xOutBits4_inst9_O; +wire Mux2xBit_inst0_O; +wire Mux2xBit_inst1_O; +wire Mux2xBit_inst2_O; +wire Mux2xBit_inst3_O; +wire Mux2xBit_inst4_O; +wire Mux2xBit_inst5_O; +wire [3:0] Mux2xBits4_inst0_O; +wire [3:0] Mux2xBits4_inst1_O; +wire [3:0] Mux2xBits4_inst10_O; +wire [3:0] Mux2xBits4_inst11_O; +wire [3:0] Mux2xBits4_inst12_O; +wire [3:0] Mux2xBits4_inst13_O; +wire [3:0] Mux2xBits4_inst14_O; +wire [3:0] Mux2xBits4_inst2_O; +wire [3:0] Mux2xBits4_inst3_O; +wire [3:0] Mux2xBits4_inst4_O; +wire [3:0] Mux2xBits4_inst5_O; +wire [3:0] Mux2xBits4_inst6_O; +wire [3:0] Mux2xBits4_inst7_O; +wire [3:0] Mux2xBits4_inst8_O; +wire [3:0] Mux2xBits4_inst9_O; wire bit_const_0_None_out; wire bit_const_1_None_out; wire [1:0] const_0_2_out; @@ -303,131 +303,131 @@ wire magma_Bits_2_eq_inst6_out; wire magma_Bits_2_eq_inst7_out; wire magma_Bits_2_eq_inst8_out; wire magma_Bits_2_eq_inst9_out; -Mux2xOutBit Mux2xOutBit_inst0 ( +Mux2xBit Mux2xBit_inst0 ( .I0(clk_en), .I1(bit_const_0_None_out), .S(magma_Bits_2_eq_inst1_out), - .O(Mux2xOutBit_inst0_O) + .O(Mux2xBit_inst0_O) ); -Mux2xOutBit Mux2xOutBit_inst1 ( - .I0(Mux2xOutBit_inst0_O), +Mux2xBit Mux2xBit_inst1 ( + .I0(Mux2xBit_inst0_O), .I1(bit_const_0_None_out), .S(magma_Bits_2_eq_inst4_out), - .O(Mux2xOutBit_inst1_O) + .O(Mux2xBit_inst1_O) ); -Mux2xOutBit Mux2xOutBit_inst2 ( - .I0(Mux2xOutBit_inst1_O), +Mux2xBit Mux2xBit_inst2 ( + .I0(Mux2xBit_inst1_O), .I1(bit_const_1_None_out), .S(magma_Bit_not_inst1_out), - .O(Mux2xOutBit_inst2_O) + .O(Mux2xBit_inst2_O) ); -Mux2xOutBit Mux2xOutBit_inst3 ( +Mux2xBit Mux2xBit_inst3 ( .I0(clk_en), .I1(bit_const_0_None_out), .S(magma_Bit_and_inst3_out), - .O(Mux2xOutBit_inst3_O) + .O(Mux2xBit_inst3_O) ); -Mux2xOutBit Mux2xOutBit_inst4 ( - .I0(Mux2xOutBit_inst3_O), +Mux2xBit Mux2xBit_inst4 ( + .I0(Mux2xBit_inst3_O), .I1(bit_const_0_None_out), .S(magma_Bit_and_inst9_out), - .O(Mux2xOutBit_inst4_O) + .O(Mux2xBit_inst4_O) ); -Mux2xOutBit Mux2xOutBit_inst5 ( - .I0(Mux2xOutBit_inst4_O), +Mux2xBit Mux2xBit_inst5 ( + .I0(Mux2xBit_inst4_O), .I1(bit_const_1_None_out), .S(magma_Bit_not_inst24_out), - .O(Mux2xOutBit_inst5_O) + .O(Mux2xBit_inst5_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst0 ( +Mux2xBits4 Mux2xBits4_inst0 ( .I0(value), .I1(value), .S(magma_Bits_2_eq_inst0_out), - .O(Mux2xOutBits4_inst0_O) + .O(Mux2xBits4_inst0_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst1 ( +Mux2xBits4 Mux2xBits4_inst1 ( .I0(self_register_O), .I1(self_register_O), .S(magma_Bits_2_eq_inst2_out), - .O(Mux2xOutBits4_inst1_O) + .O(Mux2xBits4_inst1_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst10 ( - .I0(Mux2xOutBits4_inst7_O), +Mux2xBits4 Mux2xBits4_inst10 ( + .I0(Mux2xBits4_inst7_O), .I1(const_), .S(magma_Bit_and_inst10_out), - .O(Mux2xOutBits4_inst10_O) + .O(Mux2xBits4_inst10_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst11 ( - .I0(Mux2xOutBits4_inst8_O), +Mux2xBits4 Mux2xBits4_inst11 ( + .I0(Mux2xBits4_inst8_O), .I1(self_register_O), .S(magma_Bit_and_inst11_out), - .O(Mux2xOutBits4_inst11_O) + .O(Mux2xBits4_inst11_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst12 ( - .I0(Mux2xOutBits4_inst9_O), +Mux2xBits4 Mux2xBits4_inst12 ( + .I0(Mux2xBits4_inst9_O), .I1(config_data), .S(magma_Bit_not_inst23_out), - .O(Mux2xOutBits4_inst12_O) + .O(Mux2xBits4_inst12_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst13 ( - .I0(Mux2xOutBits4_inst10_O), +Mux2xBits4 Mux2xBits4_inst13 ( + .I0(Mux2xBits4_inst10_O), .I1(self_register_O), .S(magma_Bit_not_inst25_out), - .O(Mux2xOutBits4_inst13_O) + .O(Mux2xBits4_inst13_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst14 ( - .I0(Mux2xOutBits4_inst11_O), +Mux2xBits4 Mux2xBits4_inst14 ( + .I0(Mux2xBits4_inst11_O), .I1(self_register_O), .S(magma_Bit_not_inst26_out), - .O(Mux2xOutBits4_inst14_O) + .O(Mux2xBits4_inst14_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst2 ( - .I0(Mux2xOutBits4_inst0_O), +Mux2xBits4 Mux2xBits4_inst2 ( + .I0(Mux2xBits4_inst0_O), .I1(value), .S(magma_Bits_2_eq_inst3_out), - .O(Mux2xOutBits4_inst2_O) + .O(Mux2xBits4_inst2_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst3 ( - .I0(Mux2xOutBits4_inst1_O), +Mux2xBits4 Mux2xBits4_inst3 ( + .I0(Mux2xBits4_inst1_O), .I1(self_register_O), .S(magma_Bits_2_eq_inst5_out), - .O(Mux2xOutBits4_inst3_O) + .O(Mux2xBits4_inst3_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst4 ( - .I0(Mux2xOutBits4_inst2_O), +Mux2xBits4 Mux2xBits4_inst4 ( + .I0(Mux2xBits4_inst2_O), .I1(config_data), .S(magma_Bit_not_inst0_out), - .O(Mux2xOutBits4_inst4_O) + .O(Mux2xBits4_inst4_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst5 ( - .I0(Mux2xOutBits4_inst3_O), +Mux2xBits4 Mux2xBits4_inst5 ( + .I0(Mux2xBits4_inst3_O), .I1(self_register_O), .S(magma_Bit_not_inst2_out), - .O(Mux2xOutBits4_inst5_O) + .O(Mux2xBits4_inst5_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst6 ( +Mux2xBits4 Mux2xBits4_inst6 ( .I0(value), .I1(value), .S(magma_Bit_and_inst1_out), - .O(Mux2xOutBits4_inst6_O) + .O(Mux2xBits4_inst6_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst7 ( +Mux2xBits4 Mux2xBits4_inst7 ( .I0(self_register_O), .I1(value), .S(magma_Bit_and_inst5_out), - .O(Mux2xOutBits4_inst7_O) + .O(Mux2xBits4_inst7_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst8 ( +Mux2xBits4 Mux2xBits4_inst8 ( .I0(self_register_O), .I1(self_register_O), .S(magma_Bit_and_inst7_out), - .O(Mux2xOutBits4_inst8_O) + .O(Mux2xBits4_inst8_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst9 ( - .I0(Mux2xOutBits4_inst6_O), +Mux2xBits4 Mux2xBits4_inst9 ( + .I0(Mux2xBits4_inst6_O), .I1(value), .S(magma_Bit_and_inst8_out), - .O(Mux2xOutBits4_inst9_O) + .O(Mux2xBits4_inst9_O) ); corebit_const #( .value(1'b0) @@ -820,10 +820,10 @@ coreir_eq #( .in1(const_0_2_out), .out(magma_Bits_2_eq_inst9_out) ); -assign O0 = Mux2xOutBits4_inst12_O; -assign O1 = Mux2xOutBit_inst5_O; -assign O2 = Mux2xOutBits4_inst13_O; -assign O3 = Mux2xOutBits4_inst14_O; +assign O0 = Mux2xBits4_inst12_O; +assign O1 = Mux2xBit_inst5_O; +assign O2 = Mux2xBits4_inst13_O; +assign O3 = Mux2xBits4_inst14_O; endmodule module RegisterMode ( diff --git a/tests/test_syntax/gold/RegisterModeARST.json b/tests/test_syntax/gold/RegisterModeARST.json index 135d60c8d..1e31cde22 100644 --- a/tests/test_syntax/gold/RegisterModeARST.json +++ b/tests/test_syntax/gold/RegisterModeARST.json @@ -2,7 +2,7 @@ "namespaces":{ "global":{ "modules":{ - "Mux2xOutBit":{ + "Mux2xBit":{ "type":["Record",[ ["I0","BitIn"], ["I1","BitIn"], @@ -22,7 +22,7 @@ ["self.O","coreir_commonlib_mux2x1_inst0.out.0"] ] }, - "Mux2xOutBits4":{ + "Mux2xBits4":{ "type":["Record",[ ["I0",["Array",4,"BitIn"]], ["I1",["Array",4,"BitIn"]], @@ -122,68 +122,68 @@ ["O3",["Array",4,"Bit"]] ]], "instances":{ - "Mux2xOutBit_inst0":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst0":{ + "modref":"global.Mux2xBit" }, - "Mux2xOutBit_inst1":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst1":{ + "modref":"global.Mux2xBit" }, - "Mux2xOutBit_inst2":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst2":{ + "modref":"global.Mux2xBit" }, - "Mux2xOutBit_inst3":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst3":{ + "modref":"global.Mux2xBit" }, - "Mux2xOutBit_inst4":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst4":{ + "modref":"global.Mux2xBit" }, - "Mux2xOutBit_inst5":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst5":{ + "modref":"global.Mux2xBit" }, - "Mux2xOutBits4_inst0":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst0":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst1":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst1":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst10":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst10":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst11":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst11":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst12":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst12":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst13":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst13":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst14":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst14":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst2":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst2":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst3":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst3":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst4":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst4":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst5":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst5":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst6":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst6":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst7":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst7":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst8":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst8":{ + "modref":"global.Mux2xBits4" }, - "Mux2xOutBits4_inst9":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst9":{ + "modref":"global.Mux2xBits4" }, "bit_const_0_None":{ "modref":"corebit.const", @@ -439,73 +439,73 @@ } }, "connections":[ - ["self.clk_en","Mux2xOutBit_inst0.I0"], - ["bit_const_0_None.out","Mux2xOutBit_inst0.I1"], - ["Mux2xOutBit_inst1.I0","Mux2xOutBit_inst0.O"], - ["magma_Bits_2_eq_inst1.out","Mux2xOutBit_inst0.S"], - ["bit_const_0_None.out","Mux2xOutBit_inst1.I1"], - ["Mux2xOutBit_inst2.I0","Mux2xOutBit_inst1.O"], - ["magma_Bits_2_eq_inst4.out","Mux2xOutBit_inst1.S"], - ["bit_const_1_None.out","Mux2xOutBit_inst2.I1"], - ["magma_Bit_not_inst1.out","Mux2xOutBit_inst2.S"], - ["self.clk_en","Mux2xOutBit_inst3.I0"], - ["bit_const_0_None.out","Mux2xOutBit_inst3.I1"], - ["Mux2xOutBit_inst4.I0","Mux2xOutBit_inst3.O"], - ["magma_Bit_and_inst3.out","Mux2xOutBit_inst3.S"], - ["bit_const_0_None.out","Mux2xOutBit_inst4.I1"], - ["Mux2xOutBit_inst5.I0","Mux2xOutBit_inst4.O"], - ["magma_Bit_and_inst9.out","Mux2xOutBit_inst4.S"], - ["bit_const_1_None.out","Mux2xOutBit_inst5.I1"], - ["self.O1","Mux2xOutBit_inst5.O"], - ["magma_Bit_not_inst24.out","Mux2xOutBit_inst5.S"], - ["self.value","Mux2xOutBits4_inst0.I0"], - ["self.value","Mux2xOutBits4_inst0.I1"], - ["Mux2xOutBits4_inst2.I0","Mux2xOutBits4_inst0.O"], - ["magma_Bits_2_eq_inst0.out","Mux2xOutBits4_inst0.S"], - ["self.self_register_O","Mux2xOutBits4_inst1.I0"], - ["self.self_register_O","Mux2xOutBits4_inst1.I1"], - ["Mux2xOutBits4_inst3.I0","Mux2xOutBits4_inst1.O"], - ["magma_Bits_2_eq_inst2.out","Mux2xOutBits4_inst1.S"], - ["Mux2xOutBits4_inst7.O","Mux2xOutBits4_inst10.I0"], - ["self.const_","Mux2xOutBits4_inst10.I1"], - ["Mux2xOutBits4_inst13.I0","Mux2xOutBits4_inst10.O"], - ["magma_Bit_and_inst10.out","Mux2xOutBits4_inst10.S"], - ["Mux2xOutBits4_inst8.O","Mux2xOutBits4_inst11.I0"], - ["self.self_register_O","Mux2xOutBits4_inst11.I1"], - ["Mux2xOutBits4_inst14.I0","Mux2xOutBits4_inst11.O"], - ["magma_Bit_and_inst11.out","Mux2xOutBits4_inst11.S"], - ["Mux2xOutBits4_inst9.O","Mux2xOutBits4_inst12.I0"], - ["self.config_data","Mux2xOutBits4_inst12.I1"], - ["self.O0","Mux2xOutBits4_inst12.O"], - ["magma_Bit_not_inst23.out","Mux2xOutBits4_inst12.S"], - ["self.self_register_O","Mux2xOutBits4_inst13.I1"], - ["self.O2","Mux2xOutBits4_inst13.O"], - ["magma_Bit_not_inst25.out","Mux2xOutBits4_inst13.S"], - ["self.self_register_O","Mux2xOutBits4_inst14.I1"], - ["self.O3","Mux2xOutBits4_inst14.O"], - ["magma_Bit_not_inst26.out","Mux2xOutBits4_inst14.S"], - ["self.value","Mux2xOutBits4_inst2.I1"], - ["Mux2xOutBits4_inst4.I0","Mux2xOutBits4_inst2.O"], - ["magma_Bits_2_eq_inst3.out","Mux2xOutBits4_inst2.S"], - ["self.self_register_O","Mux2xOutBits4_inst3.I1"], - ["Mux2xOutBits4_inst5.I0","Mux2xOutBits4_inst3.O"], - ["magma_Bits_2_eq_inst5.out","Mux2xOutBits4_inst3.S"], - ["self.config_data","Mux2xOutBits4_inst4.I1"], - ["magma_Bit_not_inst0.out","Mux2xOutBits4_inst4.S"], - ["self.self_register_O","Mux2xOutBits4_inst5.I1"], - ["magma_Bit_not_inst2.out","Mux2xOutBits4_inst5.S"], - ["self.value","Mux2xOutBits4_inst6.I0"], - ["self.value","Mux2xOutBits4_inst6.I1"], - ["Mux2xOutBits4_inst9.I0","Mux2xOutBits4_inst6.O"], - ["magma_Bit_and_inst1.out","Mux2xOutBits4_inst6.S"], - ["self.self_register_O","Mux2xOutBits4_inst7.I0"], - ["self.value","Mux2xOutBits4_inst7.I1"], - ["magma_Bit_and_inst5.out","Mux2xOutBits4_inst7.S"], - ["self.self_register_O","Mux2xOutBits4_inst8.I0"], - ["self.self_register_O","Mux2xOutBits4_inst8.I1"], - ["magma_Bit_and_inst7.out","Mux2xOutBits4_inst8.S"], - ["self.value","Mux2xOutBits4_inst9.I1"], - ["magma_Bit_and_inst8.out","Mux2xOutBits4_inst9.S"], + ["self.clk_en","Mux2xBit_inst0.I0"], + ["bit_const_0_None.out","Mux2xBit_inst0.I1"], + ["Mux2xBit_inst1.I0","Mux2xBit_inst0.O"], + ["magma_Bits_2_eq_inst1.out","Mux2xBit_inst0.S"], + ["bit_const_0_None.out","Mux2xBit_inst1.I1"], + ["Mux2xBit_inst2.I0","Mux2xBit_inst1.O"], + ["magma_Bits_2_eq_inst4.out","Mux2xBit_inst1.S"], + ["bit_const_1_None.out","Mux2xBit_inst2.I1"], + ["magma_Bit_not_inst1.out","Mux2xBit_inst2.S"], + ["self.clk_en","Mux2xBit_inst3.I0"], + ["bit_const_0_None.out","Mux2xBit_inst3.I1"], + ["Mux2xBit_inst4.I0","Mux2xBit_inst3.O"], + ["magma_Bit_and_inst3.out","Mux2xBit_inst3.S"], + ["bit_const_0_None.out","Mux2xBit_inst4.I1"], + ["Mux2xBit_inst5.I0","Mux2xBit_inst4.O"], + ["magma_Bit_and_inst9.out","Mux2xBit_inst4.S"], + ["bit_const_1_None.out","Mux2xBit_inst5.I1"], + ["self.O1","Mux2xBit_inst5.O"], + ["magma_Bit_not_inst24.out","Mux2xBit_inst5.S"], + ["self.value","Mux2xBits4_inst0.I0"], + ["self.value","Mux2xBits4_inst0.I1"], + ["Mux2xBits4_inst2.I0","Mux2xBits4_inst0.O"], + ["magma_Bits_2_eq_inst0.out","Mux2xBits4_inst0.S"], + ["self.self_register_O","Mux2xBits4_inst1.I0"], + ["self.self_register_O","Mux2xBits4_inst1.I1"], + ["Mux2xBits4_inst3.I0","Mux2xBits4_inst1.O"], + ["magma_Bits_2_eq_inst2.out","Mux2xBits4_inst1.S"], + ["Mux2xBits4_inst7.O","Mux2xBits4_inst10.I0"], + ["self.const_","Mux2xBits4_inst10.I1"], + ["Mux2xBits4_inst13.I0","Mux2xBits4_inst10.O"], + ["magma_Bit_and_inst10.out","Mux2xBits4_inst10.S"], + ["Mux2xBits4_inst8.O","Mux2xBits4_inst11.I0"], + ["self.self_register_O","Mux2xBits4_inst11.I1"], + ["Mux2xBits4_inst14.I0","Mux2xBits4_inst11.O"], + ["magma_Bit_and_inst11.out","Mux2xBits4_inst11.S"], + ["Mux2xBits4_inst9.O","Mux2xBits4_inst12.I0"], + ["self.config_data","Mux2xBits4_inst12.I1"], + ["self.O0","Mux2xBits4_inst12.O"], + ["magma_Bit_not_inst23.out","Mux2xBits4_inst12.S"], + ["self.self_register_O","Mux2xBits4_inst13.I1"], + ["self.O2","Mux2xBits4_inst13.O"], + ["magma_Bit_not_inst25.out","Mux2xBits4_inst13.S"], + ["self.self_register_O","Mux2xBits4_inst14.I1"], + ["self.O3","Mux2xBits4_inst14.O"], + ["magma_Bit_not_inst26.out","Mux2xBits4_inst14.S"], + ["self.value","Mux2xBits4_inst2.I1"], + ["Mux2xBits4_inst4.I0","Mux2xBits4_inst2.O"], + ["magma_Bits_2_eq_inst3.out","Mux2xBits4_inst2.S"], + ["self.self_register_O","Mux2xBits4_inst3.I1"], + ["Mux2xBits4_inst5.I0","Mux2xBits4_inst3.O"], + ["magma_Bits_2_eq_inst5.out","Mux2xBits4_inst3.S"], + ["self.config_data","Mux2xBits4_inst4.I1"], + ["magma_Bit_not_inst0.out","Mux2xBits4_inst4.S"], + ["self.self_register_O","Mux2xBits4_inst5.I1"], + ["magma_Bit_not_inst2.out","Mux2xBits4_inst5.S"], + ["self.value","Mux2xBits4_inst6.I0"], + ["self.value","Mux2xBits4_inst6.I1"], + ["Mux2xBits4_inst9.I0","Mux2xBits4_inst6.O"], + ["magma_Bit_and_inst1.out","Mux2xBits4_inst6.S"], + ["self.self_register_O","Mux2xBits4_inst7.I0"], + ["self.value","Mux2xBits4_inst7.I1"], + ["magma_Bit_and_inst5.out","Mux2xBits4_inst7.S"], + ["self.self_register_O","Mux2xBits4_inst8.I0"], + ["self.self_register_O","Mux2xBits4_inst8.I1"], + ["magma_Bit_and_inst7.out","Mux2xBits4_inst8.S"], + ["self.value","Mux2xBits4_inst9.I1"], + ["magma_Bit_and_inst8.out","Mux2xBits4_inst9.S"], ["magma_Bit_xor_inst0.in1","bit_const_1_None.out"], ["magma_Bit_xor_inst1.in1","bit_const_1_None.out"], ["magma_Bit_xor_inst10.in1","bit_const_1_None.out"], @@ -634,15 +634,15 @@ ["O1",["Array",4,"Bit"]] ]], "instances":{ - "Mux2xOutBits4_inst0":{ - "modref":"global.Mux2xOutBits4" + "Mux2xBits4_inst0":{ + "modref":"global.Mux2xBits4" } }, "connections":[ - ["self.self_value_O","Mux2xOutBits4_inst0.I0"], - ["self.value","Mux2xOutBits4_inst0.I1"], - ["self.O0","Mux2xOutBits4_inst0.O"], - ["self.en","Mux2xOutBits4_inst0.S"], + ["self.self_value_O","Mux2xBits4_inst0.I0"], + ["self.value","Mux2xBits4_inst0.I1"], + ["self.O0","Mux2xBits4_inst0.O"], + ["self.en","Mux2xBits4_inst0.S"], ["self.self_value_O","self.O1"] ] } diff --git a/tests/test_syntax/gold/RegisterModeARST.v b/tests/test_syntax/gold/RegisterModeARST.v index fa04590e9..79db83352 100644 --- a/tests/test_syntax/gold/RegisterModeARST.v +++ b/tests/test_syntax/gold/RegisterModeARST.v @@ -116,7 +116,7 @@ coreir_mux #( assign out = _join_out; endmodule -module Mux2xOutBits4 ( +module Mux2xBits4 ( input [3:0] I0, input [3:0] I1, input S, @@ -141,14 +141,14 @@ module Register_comb ( output [3:0] O0, output [3:0] O1 ); -wire [3:0] Mux2xOutBits4_inst0_O; -Mux2xOutBits4 Mux2xOutBits4_inst0 ( +wire [3:0] Mux2xBits4_inst0_O; +Mux2xBits4 Mux2xBits4_inst0 ( .I0(self_value_O), .I1(value), .S(en), - .O(Mux2xOutBits4_inst0_O) + .O(Mux2xBits4_inst0_O) ); -assign O0 = Mux2xOutBits4_inst0_O; +assign O0 = Mux2xBits4_inst0_O; assign O1 = self_value_O; endmodule @@ -183,7 +183,7 @@ coreir_reg_arst #( assign O = Register_comb_inst0_O1; endmodule -module Mux2xOutBit ( +module Mux2xBit ( input I0, input I1, input S, @@ -214,27 +214,27 @@ module RegisterMode_comb ( output [3:0] O2, output [3:0] O3 ); -wire Mux2xOutBit_inst0_O; -wire Mux2xOutBit_inst1_O; -wire Mux2xOutBit_inst2_O; -wire Mux2xOutBit_inst3_O; -wire Mux2xOutBit_inst4_O; -wire Mux2xOutBit_inst5_O; -wire [3:0] Mux2xOutBits4_inst0_O; -wire [3:0] Mux2xOutBits4_inst1_O; -wire [3:0] Mux2xOutBits4_inst10_O; -wire [3:0] Mux2xOutBits4_inst11_O; -wire [3:0] Mux2xOutBits4_inst12_O; -wire [3:0] Mux2xOutBits4_inst13_O; -wire [3:0] Mux2xOutBits4_inst14_O; -wire [3:0] Mux2xOutBits4_inst2_O; -wire [3:0] Mux2xOutBits4_inst3_O; -wire [3:0] Mux2xOutBits4_inst4_O; -wire [3:0] Mux2xOutBits4_inst5_O; -wire [3:0] Mux2xOutBits4_inst6_O; -wire [3:0] Mux2xOutBits4_inst7_O; -wire [3:0] Mux2xOutBits4_inst8_O; -wire [3:0] Mux2xOutBits4_inst9_O; +wire Mux2xBit_inst0_O; +wire Mux2xBit_inst1_O; +wire Mux2xBit_inst2_O; +wire Mux2xBit_inst3_O; +wire Mux2xBit_inst4_O; +wire Mux2xBit_inst5_O; +wire [3:0] Mux2xBits4_inst0_O; +wire [3:0] Mux2xBits4_inst1_O; +wire [3:0] Mux2xBits4_inst10_O; +wire [3:0] Mux2xBits4_inst11_O; +wire [3:0] Mux2xBits4_inst12_O; +wire [3:0] Mux2xBits4_inst13_O; +wire [3:0] Mux2xBits4_inst14_O; +wire [3:0] Mux2xBits4_inst2_O; +wire [3:0] Mux2xBits4_inst3_O; +wire [3:0] Mux2xBits4_inst4_O; +wire [3:0] Mux2xBits4_inst5_O; +wire [3:0] Mux2xBits4_inst6_O; +wire [3:0] Mux2xBits4_inst7_O; +wire [3:0] Mux2xBits4_inst8_O; +wire [3:0] Mux2xBits4_inst9_O; wire bit_const_0_None_out; wire bit_const_1_None_out; wire [1:0] const_0_2_out; @@ -311,131 +311,131 @@ wire magma_Bits_2_eq_inst6_out; wire magma_Bits_2_eq_inst7_out; wire magma_Bits_2_eq_inst8_out; wire magma_Bits_2_eq_inst9_out; -Mux2xOutBit Mux2xOutBit_inst0 ( +Mux2xBit Mux2xBit_inst0 ( .I0(clk_en), .I1(bit_const_0_None_out), .S(magma_Bits_2_eq_inst1_out), - .O(Mux2xOutBit_inst0_O) + .O(Mux2xBit_inst0_O) ); -Mux2xOutBit Mux2xOutBit_inst1 ( - .I0(Mux2xOutBit_inst0_O), +Mux2xBit Mux2xBit_inst1 ( + .I0(Mux2xBit_inst0_O), .I1(bit_const_0_None_out), .S(magma_Bits_2_eq_inst4_out), - .O(Mux2xOutBit_inst1_O) + .O(Mux2xBit_inst1_O) ); -Mux2xOutBit Mux2xOutBit_inst2 ( - .I0(Mux2xOutBit_inst1_O), +Mux2xBit Mux2xBit_inst2 ( + .I0(Mux2xBit_inst1_O), .I1(bit_const_1_None_out), .S(magma_Bit_not_inst1_out), - .O(Mux2xOutBit_inst2_O) + .O(Mux2xBit_inst2_O) ); -Mux2xOutBit Mux2xOutBit_inst3 ( +Mux2xBit Mux2xBit_inst3 ( .I0(clk_en), .I1(bit_const_0_None_out), .S(magma_Bit_and_inst3_out), - .O(Mux2xOutBit_inst3_O) + .O(Mux2xBit_inst3_O) ); -Mux2xOutBit Mux2xOutBit_inst4 ( - .I0(Mux2xOutBit_inst3_O), +Mux2xBit Mux2xBit_inst4 ( + .I0(Mux2xBit_inst3_O), .I1(bit_const_0_None_out), .S(magma_Bit_and_inst9_out), - .O(Mux2xOutBit_inst4_O) + .O(Mux2xBit_inst4_O) ); -Mux2xOutBit Mux2xOutBit_inst5 ( - .I0(Mux2xOutBit_inst4_O), +Mux2xBit Mux2xBit_inst5 ( + .I0(Mux2xBit_inst4_O), .I1(bit_const_1_None_out), .S(magma_Bit_not_inst24_out), - .O(Mux2xOutBit_inst5_O) + .O(Mux2xBit_inst5_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst0 ( +Mux2xBits4 Mux2xBits4_inst0 ( .I0(value), .I1(value), .S(magma_Bits_2_eq_inst0_out), - .O(Mux2xOutBits4_inst0_O) + .O(Mux2xBits4_inst0_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst1 ( +Mux2xBits4 Mux2xBits4_inst1 ( .I0(self_register_O), .I1(self_register_O), .S(magma_Bits_2_eq_inst2_out), - .O(Mux2xOutBits4_inst1_O) + .O(Mux2xBits4_inst1_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst10 ( - .I0(Mux2xOutBits4_inst7_O), +Mux2xBits4 Mux2xBits4_inst10 ( + .I0(Mux2xBits4_inst7_O), .I1(const_), .S(magma_Bit_and_inst10_out), - .O(Mux2xOutBits4_inst10_O) + .O(Mux2xBits4_inst10_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst11 ( - .I0(Mux2xOutBits4_inst8_O), +Mux2xBits4 Mux2xBits4_inst11 ( + .I0(Mux2xBits4_inst8_O), .I1(self_register_O), .S(magma_Bit_and_inst11_out), - .O(Mux2xOutBits4_inst11_O) + .O(Mux2xBits4_inst11_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst12 ( - .I0(Mux2xOutBits4_inst9_O), +Mux2xBits4 Mux2xBits4_inst12 ( + .I0(Mux2xBits4_inst9_O), .I1(config_data), .S(magma_Bit_not_inst23_out), - .O(Mux2xOutBits4_inst12_O) + .O(Mux2xBits4_inst12_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst13 ( - .I0(Mux2xOutBits4_inst10_O), +Mux2xBits4 Mux2xBits4_inst13 ( + .I0(Mux2xBits4_inst10_O), .I1(self_register_O), .S(magma_Bit_not_inst25_out), - .O(Mux2xOutBits4_inst13_O) + .O(Mux2xBits4_inst13_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst14 ( - .I0(Mux2xOutBits4_inst11_O), +Mux2xBits4 Mux2xBits4_inst14 ( + .I0(Mux2xBits4_inst11_O), .I1(self_register_O), .S(magma_Bit_not_inst26_out), - .O(Mux2xOutBits4_inst14_O) + .O(Mux2xBits4_inst14_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst2 ( - .I0(Mux2xOutBits4_inst0_O), +Mux2xBits4 Mux2xBits4_inst2 ( + .I0(Mux2xBits4_inst0_O), .I1(value), .S(magma_Bits_2_eq_inst3_out), - .O(Mux2xOutBits4_inst2_O) + .O(Mux2xBits4_inst2_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst3 ( - .I0(Mux2xOutBits4_inst1_O), +Mux2xBits4 Mux2xBits4_inst3 ( + .I0(Mux2xBits4_inst1_O), .I1(self_register_O), .S(magma_Bits_2_eq_inst5_out), - .O(Mux2xOutBits4_inst3_O) + .O(Mux2xBits4_inst3_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst4 ( - .I0(Mux2xOutBits4_inst2_O), +Mux2xBits4 Mux2xBits4_inst4 ( + .I0(Mux2xBits4_inst2_O), .I1(config_data), .S(magma_Bit_not_inst0_out), - .O(Mux2xOutBits4_inst4_O) + .O(Mux2xBits4_inst4_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst5 ( - .I0(Mux2xOutBits4_inst3_O), +Mux2xBits4 Mux2xBits4_inst5 ( + .I0(Mux2xBits4_inst3_O), .I1(self_register_O), .S(magma_Bit_not_inst2_out), - .O(Mux2xOutBits4_inst5_O) + .O(Mux2xBits4_inst5_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst6 ( +Mux2xBits4 Mux2xBits4_inst6 ( .I0(value), .I1(value), .S(magma_Bit_and_inst1_out), - .O(Mux2xOutBits4_inst6_O) + .O(Mux2xBits4_inst6_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst7 ( +Mux2xBits4 Mux2xBits4_inst7 ( .I0(self_register_O), .I1(value), .S(magma_Bit_and_inst5_out), - .O(Mux2xOutBits4_inst7_O) + .O(Mux2xBits4_inst7_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst8 ( +Mux2xBits4 Mux2xBits4_inst8 ( .I0(self_register_O), .I1(self_register_O), .S(magma_Bit_and_inst7_out), - .O(Mux2xOutBits4_inst8_O) + .O(Mux2xBits4_inst8_O) ); -Mux2xOutBits4 Mux2xOutBits4_inst9 ( - .I0(Mux2xOutBits4_inst6_O), +Mux2xBits4 Mux2xBits4_inst9 ( + .I0(Mux2xBits4_inst6_O), .I1(value), .S(magma_Bit_and_inst8_out), - .O(Mux2xOutBits4_inst9_O) + .O(Mux2xBits4_inst9_O) ); corebit_const #( .value(1'b0) @@ -828,10 +828,10 @@ coreir_eq #( .in1(const_0_2_out), .out(magma_Bits_2_eq_inst9_out) ); -assign O0 = Mux2xOutBits4_inst12_O; -assign O1 = Mux2xOutBit_inst5_O; -assign O2 = Mux2xOutBits4_inst13_O; -assign O3 = Mux2xOutBits4_inst14_O; +assign O0 = Mux2xBits4_inst12_O; +assign O1 = Mux2xBit_inst5_O; +assign O2 = Mux2xBits4_inst13_O; +assign O3 = Mux2xBits4_inst14_O; endmodule module RegisterMode ( diff --git a/tests/test_syntax/gold/TestNestedProductReg.json b/tests/test_syntax/gold/TestNestedProductReg.json index 9aec0fc0b..a7c1d856c 100644 --- a/tests/test_syntax/gold/TestNestedProductReg.json +++ b/tests/test_syntax/gold/TestNestedProductReg.json @@ -44,7 +44,7 @@ ["self.O","reg_PR_inst0.out.0"] ] }, - "Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8":{ + "Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8":{ "type":["Record",[ ["I0",["Record",[["a0","BitIn"],["a1",["Record",[["c0",["Array",4,"BitIn"]],["c1","BitIn"]]]],["a2",["Array",8,"BitIn"]]]]], ["I1",["Record",[["a0","BitIn"],["a1",["Record",[["c0",["Array",4,"BitIn"]],["c1","BitIn"]]]],["a2",["Array",8,"BitIn"]]]]], @@ -133,16 +133,16 @@ ["O1",["Record",[["a0","Bit"],["a1",["Record",[["c0",["Array",4,"Bit"]],["c1","Bit"]]]],["a2",["Array",8,"Bit"]]]]] ]], "instances":{ - "Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0":{ - "modref":"global.Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8" + "Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0":{ + "modref":"global.Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8" } }, "connections":[ - ["self.self_a_O","Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0.I0"], - ["self.a","Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0.I1"], - ["self.O0","Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0.O"], - ["self.O1","Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0.O"], - ["self.b","Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0.S"] + ["self.self_a_O","Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0.I0"], + ["self.a","Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0.I1"], + ["self.O0","Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0.O"], + ["self.O1","Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0.O"], + ["self.b","Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0.S"] ] } } diff --git a/tests/test_syntax/gold/TestNestedProductReg.v b/tests/test_syntax/gold/TestNestedProductReg.v index 75be3eacb..04394878f 100644 --- a/tests/test_syntax/gold/TestNestedProductReg.v +++ b/tests/test_syntax/gold/TestNestedProductReg.v @@ -91,7 +91,7 @@ coreir_mux #( assign out = _join_out; endmodule -module Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8 ( +module Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8 ( input I0_a0, input [3:0] I0_a1_c0, input I0_a1_c1, @@ -189,11 +189,11 @@ module TestNestedProductReg_comb ( input self_a_O_a1_c1, input [7:0] self_a_O_a2 ); -wire Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0_O_a0; -wire [3:0] Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0_O_a1_c0; -wire Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0_O_a1_c1; -wire [7:0] Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0_O_a2; -Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8 Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0 ( +wire Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0_O_a0; +wire [3:0] Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0_O_a1_c0; +wire Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0_O_a1_c1; +wire [7:0] Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0_O_a2; +Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8 Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0 ( .I0_a0(self_a_O_a0), .I0_a1_c0(self_a_O_a1_c0), .I0_a1_c1(self_a_O_a1_c1), @@ -202,20 +202,20 @@ Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8 Mux2xTuplea0_OutBi .I1_a1_c0(a_a1_c0), .I1_a1_c1(a_a1_c1), .I1_a2(a_a2), - .O_a0(Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0_O_a0), - .O_a1_c0(Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0_O_a1_c0), - .O_a1_c1(Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0_O_a1_c1), - .O_a2(Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0_O_a2), + .O_a0(Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0_O_a0), + .O_a1_c0(Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0_O_a1_c0), + .O_a1_c1(Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0_O_a1_c1), + .O_a2(Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0_O_a2), .S(b) ); -assign O0_a0 = Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0_O_a0; -assign O0_a1_c0 = Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0_O_a1_c0; -assign O0_a1_c1 = Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0_O_a1_c1; -assign O0_a2 = Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0_O_a2; -assign O1_a0 = Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0_O_a0; -assign O1_a1_c0 = Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0_O_a1_c0; -assign O1_a1_c1 = Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0_O_a1_c1; -assign O1_a2 = Mux2xTuplea0_OutBit_a1_Tuplec0_OutUInt4_c1_OutBit_a2_OutSInt8_inst0_O_a2; +assign O0_a0 = Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0_O_a0; +assign O0_a1_c0 = Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0_O_a1_c0; +assign O0_a1_c1 = Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0_O_a1_c1; +assign O0_a2 = Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0_O_a2; +assign O1_a0 = Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0_O_a0; +assign O1_a1_c0 = Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0_O_a1_c0; +assign O1_a1_c1 = Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0_O_a1_c1; +assign O1_a2 = Mux2xTuplea0_Bit_a1_Tuplec0_UInt4_c1_Bit_a2_SInt8_inst0_O_a2; endmodule module DFF_initTrue_has_ceFalse_has_resetFalse_has_async_resetTrue ( diff --git a/tests/test_syntax/gold/TestNoArgs.json b/tests/test_syntax/gold/TestNoArgs.json index f16056d2f..56efe638d 100644 --- a/tests/test_syntax/gold/TestNoArgs.json +++ b/tests/test_syntax/gold/TestNoArgs.json @@ -2,7 +2,7 @@ "namespaces":{ "global":{ "modules":{ - "Mux2xOutUInt3":{ + "Mux2xUInt3":{ "type":["Record",[ ["I0",["Array",3,"BitIn"]], ["I1",["Array",3,"BitIn"]], @@ -64,8 +64,8 @@ ["O2",["Array",3,"Bit"]] ]], "instances":{ - "Mux2xOutUInt3_inst0":{ - "modref":"global.Mux2xOutUInt3" + "Mux2xUInt3_inst0":{ + "modref":"global.Mux2xUInt3" }, "const_1_2":{ "genref":"coreir.const", @@ -96,11 +96,11 @@ } }, "connections":[ - ["self.self_y_O","Mux2xOutUInt3_inst0.I0"], - ["magma_Bits_3_add_inst0.out","Mux2xOutUInt3_inst0.I1"], - ["self.O1","Mux2xOutUInt3_inst0.O"], - ["self.O2","Mux2xOutUInt3_inst0.O"], - ["magma_Bits_2_eq_inst0.out","Mux2xOutUInt3_inst0.S"], + ["self.self_y_O","Mux2xUInt3_inst0.I0"], + ["magma_Bits_3_add_inst0.out","Mux2xUInt3_inst0.I1"], + ["self.O1","Mux2xUInt3_inst0.O"], + ["self.O2","Mux2xUInt3_inst0.O"], + ["magma_Bits_2_eq_inst0.out","Mux2xUInt3_inst0.S"], ["magma_Bits_2_add_inst0.in1","const_1_2.out"], ["magma_Bits_3_add_inst0.in1","const_1_3.out"], ["magma_Bits_2_eq_inst0.in1","const_3_2.out"], diff --git a/tests/test_syntax/gold/TestNoArgs.v b/tests/test_syntax/gold/TestNoArgs.v index c75d8bf88..1fdd57c26 100644 --- a/tests/test_syntax/gold/TestNoArgs.v +++ b/tests/test_syntax/gold/TestNoArgs.v @@ -78,7 +78,7 @@ coreir_mux #( assign out = _join_out; endmodule -module Mux2xOutUInt3 ( +module Mux2xUInt3 ( input [2:0] I0, input [2:0] I1, input S, @@ -103,18 +103,18 @@ module TestNoArgs_comb ( output [2:0] O1, output [2:0] O2 ); -wire [2:0] Mux2xOutUInt3_inst0_O; +wire [2:0] Mux2xUInt3_inst0_O; wire [1:0] const_1_2_out; wire [2:0] const_1_3_out; wire [1:0] const_3_2_out; wire [1:0] magma_Bits_2_add_inst0_out; wire magma_Bits_2_eq_inst0_out; wire [2:0] magma_Bits_3_add_inst0_out; -Mux2xOutUInt3 Mux2xOutUInt3_inst0 ( +Mux2xUInt3 Mux2xUInt3_inst0 ( .I0(self_y_O), .I1(magma_Bits_3_add_inst0_out), .S(magma_Bits_2_eq_inst0_out), - .O(Mux2xOutUInt3_inst0_O) + .O(Mux2xUInt3_inst0_O) ); coreir_const #( .value(2'h1), @@ -156,8 +156,8 @@ coreir_add #( .out(magma_Bits_3_add_inst0_out) ); assign O0 = magma_Bits_2_add_inst0_out; -assign O1 = Mux2xOutUInt3_inst0_O; -assign O2 = Mux2xOutUInt3_inst0_O; +assign O1 = Mux2xUInt3_inst0_O; +assign O2 = Mux2xUInt3_inst0_O; endmodule module TestNoArgs ( diff --git a/tests/test_syntax/gold/TestProductAccess.json b/tests/test_syntax/gold/TestProductAccess.json index b65387b66..d8d9899e6 100644 --- a/tests/test_syntax/gold/TestProductAccess.json +++ b/tests/test_syntax/gold/TestProductAccess.json @@ -2,7 +2,7 @@ "namespaces":{ "global":{ "modules":{ - "Mux2xTuplea0_OutBits8_a1_OutBits8":{ + "Mux2xTuplea0_Bits8_a1_Bits8":{ "type":["Record",[ ["I0",["Record",[["a0",["Array",8,"BitIn"]],["a1",["Array",8,"BitIn"]]]]], ["I1",["Record",[["a0",["Array",8,"BitIn"]],["a1",["Array",8,"BitIn"]]]]], @@ -68,18 +68,18 @@ ["O1",["Record",[["a0",["Array",8,"Bit"]],["a1",["Array",8,"Bit"]]]]] ]], "instances":{ - "Mux2xTuplea0_OutBits8_a1_OutBits8_inst0":{ - "modref":"global.Mux2xTuplea0_OutBits8_a1_OutBits8" + "Mux2xTuplea0_Bits8_a1_Bits8_inst0":{ + "modref":"global.Mux2xTuplea0_Bits8_a1_Bits8" } }, "connections":[ - ["self.self_a_O.a0","Mux2xTuplea0_OutBits8_a1_OutBits8_inst0.I0.a0"], - ["self.value","Mux2xTuplea0_OutBits8_a1_OutBits8_inst0.I0.a1"], - ["self.value","Mux2xTuplea0_OutBits8_a1_OutBits8_inst0.I1.a0"], - ["self.self_a_O.a1","Mux2xTuplea0_OutBits8_a1_OutBits8_inst0.I1.a1"], - ["self.O0","Mux2xTuplea0_OutBits8_a1_OutBits8_inst0.O"], - ["self.O1","Mux2xTuplea0_OutBits8_a1_OutBits8_inst0.O"], - ["self.sel","Mux2xTuplea0_OutBits8_a1_OutBits8_inst0.S"] + ["self.self_a_O.a0","Mux2xTuplea0_Bits8_a1_Bits8_inst0.I0.a0"], + ["self.value","Mux2xTuplea0_Bits8_a1_Bits8_inst0.I0.a1"], + ["self.value","Mux2xTuplea0_Bits8_a1_Bits8_inst0.I1.a0"], + ["self.self_a_O.a1","Mux2xTuplea0_Bits8_a1_Bits8_inst0.I1.a1"], + ["self.O0","Mux2xTuplea0_Bits8_a1_Bits8_inst0.O"], + ["self.O1","Mux2xTuplea0_Bits8_a1_Bits8_inst0.O"], + ["self.sel","Mux2xTuplea0_Bits8_a1_Bits8_inst0.S"] ] } } diff --git a/tests/test_syntax/gold/TestProductAccess.v b/tests/test_syntax/gold/TestProductAccess.v index ad697067f..0d00cca9f 100644 --- a/tests/test_syntax/gold/TestProductAccess.v +++ b/tests/test_syntax/gold/TestProductAccess.v @@ -72,7 +72,7 @@ coreir_mux #( assign out = _join_out; endmodule -module Mux2xTuplea0_OutBits8_a1_OutBits8 ( +module Mux2xTuplea0_Bits8_a1_Bits8 ( input [7:0] I0_a0, input [7:0] I0_a1, input [7:0] I1_a0, @@ -153,21 +153,21 @@ module TestProductAccess_comb ( input [7:0] self_a_O_a1, input [7:0] value ); -wire [7:0] Mux2xTuplea0_OutBits8_a1_OutBits8_inst0_O_a0; -wire [7:0] Mux2xTuplea0_OutBits8_a1_OutBits8_inst0_O_a1; -Mux2xTuplea0_OutBits8_a1_OutBits8 Mux2xTuplea0_OutBits8_a1_OutBits8_inst0 ( +wire [7:0] Mux2xTuplea0_Bits8_a1_Bits8_inst0_O_a0; +wire [7:0] Mux2xTuplea0_Bits8_a1_Bits8_inst0_O_a1; +Mux2xTuplea0_Bits8_a1_Bits8 Mux2xTuplea0_Bits8_a1_Bits8_inst0 ( .I0_a0(self_a_O_a0), .I0_a1(value), .I1_a0(value), .I1_a1(self_a_O_a1), - .O_a0(Mux2xTuplea0_OutBits8_a1_OutBits8_inst0_O_a0), - .O_a1(Mux2xTuplea0_OutBits8_a1_OutBits8_inst0_O_a1), + .O_a0(Mux2xTuplea0_Bits8_a1_Bits8_inst0_O_a0), + .O_a1(Mux2xTuplea0_Bits8_a1_Bits8_inst0_O_a1), .S(sel) ); -assign O0_a0 = Mux2xTuplea0_OutBits8_a1_OutBits8_inst0_O_a0; -assign O0_a1 = Mux2xTuplea0_OutBits8_a1_OutBits8_inst0_O_a1; -assign O1_a0 = Mux2xTuplea0_OutBits8_a1_OutBits8_inst0_O_a0; -assign O1_a1 = Mux2xTuplea0_OutBits8_a1_OutBits8_inst0_O_a1; +assign O0_a0 = Mux2xTuplea0_Bits8_a1_Bits8_inst0_O_a0; +assign O0_a1 = Mux2xTuplea0_Bits8_a1_Bits8_inst0_O_a1; +assign O1_a0 = Mux2xTuplea0_Bits8_a1_Bits8_inst0_O_a0; +assign O1_a1 = Mux2xTuplea0_Bits8_a1_Bits8_inst0_O_a1; endmodule module TestProductAccess ( diff --git a/tests/test_syntax/gold/TestProductReg.json b/tests/test_syntax/gold/TestProductReg.json index c6a16304e..36cfe713c 100644 --- a/tests/test_syntax/gold/TestProductReg.json +++ b/tests/test_syntax/gold/TestProductReg.json @@ -23,7 +23,7 @@ ["self.O","reg_PR_inst0.out.0"] ] }, - "Mux2xTuplea0_OutBit_a1_OutSInt8":{ + "Mux2xTuplea0_Bit_a1_SInt8":{ "type":["Record",[ ["I0",["Record",[["a0","BitIn"],["a1",["Array",8,"BitIn"]]]]], ["I1",["Record",[["a0","BitIn"],["a1",["Array",8,"BitIn"]]]]], @@ -90,16 +90,16 @@ ["O1",["Record",[["a0","Bit"],["a1",["Array",8,"Bit"]]]]] ]], "instances":{ - "Mux2xTuplea0_OutBit_a1_OutSInt8_inst0":{ - "modref":"global.Mux2xTuplea0_OutBit_a1_OutSInt8" + "Mux2xTuplea0_Bit_a1_SInt8_inst0":{ + "modref":"global.Mux2xTuplea0_Bit_a1_SInt8" } }, "connections":[ - ["self.self_a_O","Mux2xTuplea0_OutBit_a1_OutSInt8_inst0.I0"], - ["self.a","Mux2xTuplea0_OutBit_a1_OutSInt8_inst0.I1"], - ["self.O0","Mux2xTuplea0_OutBit_a1_OutSInt8_inst0.O"], - ["self.O1","Mux2xTuplea0_OutBit_a1_OutSInt8_inst0.O"], - ["self.b","Mux2xTuplea0_OutBit_a1_OutSInt8_inst0.S"] + ["self.self_a_O","Mux2xTuplea0_Bit_a1_SInt8_inst0.I0"], + ["self.a","Mux2xTuplea0_Bit_a1_SInt8_inst0.I1"], + ["self.O0","Mux2xTuplea0_Bit_a1_SInt8_inst0.O"], + ["self.O1","Mux2xTuplea0_Bit_a1_SInt8_inst0.O"], + ["self.b","Mux2xTuplea0_Bit_a1_SInt8_inst0.S"] ] } } diff --git a/tests/test_syntax/gold/TestProductReg.v b/tests/test_syntax/gold/TestProductReg.v index 6b20133ae..32ddefcb4 100644 --- a/tests/test_syntax/gold/TestProductReg.v +++ b/tests/test_syntax/gold/TestProductReg.v @@ -77,7 +77,7 @@ coreir_mux #( assign out = _join_out; endmodule -module Mux2xTuplea0_OutBit_a1_OutSInt8 ( +module Mux2xTuplea0_Bit_a1_SInt8 ( input I0_a0, input [7:0] I0_a1, input I1_a0, @@ -144,21 +144,21 @@ module TestProductReg_comb ( input self_a_O_a0, input [7:0] self_a_O_a1 ); -wire Mux2xTuplea0_OutBit_a1_OutSInt8_inst0_O_a0; -wire [7:0] Mux2xTuplea0_OutBit_a1_OutSInt8_inst0_O_a1; -Mux2xTuplea0_OutBit_a1_OutSInt8 Mux2xTuplea0_OutBit_a1_OutSInt8_inst0 ( +wire Mux2xTuplea0_Bit_a1_SInt8_inst0_O_a0; +wire [7:0] Mux2xTuplea0_Bit_a1_SInt8_inst0_O_a1; +Mux2xTuplea0_Bit_a1_SInt8 Mux2xTuplea0_Bit_a1_SInt8_inst0 ( .I0_a0(self_a_O_a0), .I0_a1(self_a_O_a1), .I1_a0(a_a0), .I1_a1(a_a1), - .O_a0(Mux2xTuplea0_OutBit_a1_OutSInt8_inst0_O_a0), - .O_a1(Mux2xTuplea0_OutBit_a1_OutSInt8_inst0_O_a1), + .O_a0(Mux2xTuplea0_Bit_a1_SInt8_inst0_O_a0), + .O_a1(Mux2xTuplea0_Bit_a1_SInt8_inst0_O_a1), .S(b) ); -assign O0_a0 = Mux2xTuplea0_OutBit_a1_OutSInt8_inst0_O_a0; -assign O0_a1 = Mux2xTuplea0_OutBit_a1_OutSInt8_inst0_O_a1; -assign O1_a0 = Mux2xTuplea0_OutBit_a1_OutSInt8_inst0_O_a0; -assign O1_a1 = Mux2xTuplea0_OutBit_a1_OutSInt8_inst0_O_a1; +assign O0_a0 = Mux2xTuplea0_Bit_a1_SInt8_inst0_O_a0; +assign O0_a1 = Mux2xTuplea0_Bit_a1_SInt8_inst0_O_a1; +assign O1_a0 = Mux2xTuplea0_Bit_a1_SInt8_inst0_O_a0; +assign O1_a1 = Mux2xTuplea0_Bit_a1_SInt8_inst0_O_a1; endmodule module DFF_initTrue_has_ceFalse_has_resetFalse_has_async_resetTrue ( diff --git a/tests/test_syntax/gold/TestProtocolComposition.json b/tests/test_syntax/gold/TestProtocolComposition.json index 1fa0d0d76..d2bf2f76f 100644 --- a/tests/test_syntax/gold/TestProtocolComposition.json +++ b/tests/test_syntax/gold/TestProtocolComposition.json @@ -97,29 +97,29 @@ ["O2",["Array",8,"Bit"]] ]], "instances":{ - "Mux2xOutUInt8_inst0":{ - "modref":"global.Mux2xOutUInt8" + "Mux2xUInt8_inst0":{ + "modref":"global.Mux2xUInt8" }, - "Mux2xOutUInt8_inst1":{ - "modref":"global.Mux2xOutUInt8" + "Mux2xUInt8_inst1":{ + "modref":"global.Mux2xUInt8" }, - "Mux2xOutUInt8_inst2":{ - "modref":"global.Mux2xOutUInt8" + "Mux2xUInt8_inst2":{ + "modref":"global.Mux2xUInt8" } }, "connections":[ - ["self.val","Mux2xOutUInt8_inst0.I0"], - ["self.val","Mux2xOutUInt8_inst0.I1"], - ["self.O0","Mux2xOutUInt8_inst0.O"], - ["self.select","Mux2xOutUInt8_inst0.S"], - ["self.val","Mux2xOutUInt8_inst1.I0"], - ["self.val","Mux2xOutUInt8_inst1.I1"], - ["self.O1","Mux2xOutUInt8_inst1.O"], - ["self.select","Mux2xOutUInt8_inst1.S"], - ["self.self_bar_O","Mux2xOutUInt8_inst2.I0"], - ["self.self_foo_O","Mux2xOutUInt8_inst2.I1"], - ["self.O2","Mux2xOutUInt8_inst2.O"], - ["self.select","Mux2xOutUInt8_inst2.S"] + ["self.val","Mux2xUInt8_inst0.I0"], + ["self.val","Mux2xUInt8_inst0.I1"], + ["self.O0","Mux2xUInt8_inst0.O"], + ["self.select","Mux2xUInt8_inst0.S"], + ["self.val","Mux2xUInt8_inst1.I0"], + ["self.val","Mux2xUInt8_inst1.I1"], + ["self.O1","Mux2xUInt8_inst1.O"], + ["self.select","Mux2xUInt8_inst1.S"], + ["self.self_bar_O","Mux2xUInt8_inst2.I0"], + ["self.self_foo_O","Mux2xUInt8_inst2.I1"], + ["self.O2","Mux2xUInt8_inst2.O"], + ["self.select","Mux2xUInt8_inst2.S"] ] }, "Foo_comb":{ @@ -144,7 +144,7 @@ ["self.O","magma_Bits_8_add_inst0.out"] ] }, - "Mux2xOutUInt8":{ + "Mux2xUInt8":{ "type":["Record",[ ["I0",["Array",8,"BitIn"]], ["I1",["Array",8,"BitIn"]], diff --git a/tests/test_syntax/gold/TestProtocolComposition.v b/tests/test_syntax/gold/TestProtocolComposition.v index fb808dfd3..b9eff4877 100644 --- a/tests/test_syntax/gold/TestProtocolComposition.v +++ b/tests/test_syntax/gold/TestProtocolComposition.v @@ -55,7 +55,7 @@ coreir_mux #( assign out = _join_out; endmodule -module Mux2xOutUInt8 ( +module Mux2xUInt8 ( input [7:0] I0, input [7:0] I1, input S, @@ -104,30 +104,30 @@ module FooBar_comb ( output [7:0] O1, output [7:0] O2 ); -wire [7:0] Mux2xOutUInt8_inst0_O; -wire [7:0] Mux2xOutUInt8_inst1_O; -wire [7:0] Mux2xOutUInt8_inst2_O; -Mux2xOutUInt8 Mux2xOutUInt8_inst0 ( +wire [7:0] Mux2xUInt8_inst0_O; +wire [7:0] Mux2xUInt8_inst1_O; +wire [7:0] Mux2xUInt8_inst2_O; +Mux2xUInt8 Mux2xUInt8_inst0 ( .I0(val), .I1(val), .S(select), - .O(Mux2xOutUInt8_inst0_O) + .O(Mux2xUInt8_inst0_O) ); -Mux2xOutUInt8 Mux2xOutUInt8_inst1 ( +Mux2xUInt8 Mux2xUInt8_inst1 ( .I0(val), .I1(val), .S(select), - .O(Mux2xOutUInt8_inst1_O) + .O(Mux2xUInt8_inst1_O) ); -Mux2xOutUInt8 Mux2xOutUInt8_inst2 ( +Mux2xUInt8 Mux2xUInt8_inst2 ( .I0(self_bar_O), .I1(self_foo_O), .S(select), - .O(Mux2xOutUInt8_inst2_O) + .O(Mux2xUInt8_inst2_O) ); -assign O0 = Mux2xOutUInt8_inst0_O; -assign O1 = Mux2xOutUInt8_inst1_O; -assign O2 = Mux2xOutUInt8_inst2_O; +assign O0 = Mux2xUInt8_inst0_O; +assign O1 = Mux2xUInt8_inst1_O; +assign O2 = Mux2xUInt8_inst2_O; endmodule module Foo ( diff --git a/tests/test_syntax/gold/TestSequential2GetItem.v b/tests/test_syntax/gold/TestSequential2GetItem.v index 835f1f486..c3f7fe147 100644 --- a/tests/test_syntax/gold/TestSequential2GetItem.v +++ b/tests/test_syntax/gold/TestSequential2GetItem.v @@ -59,7 +59,7 @@ assign O[1] = reg_P_inst0_out[13:7]; assign O[0] = reg_P_inst0_out[6:0]; endmodule -module Mux8xOutBits7 ( +module Mux8xBits7 ( input [6:0] I0, input [6:0] I1, input [6:0] I2, @@ -101,11 +101,11 @@ module Test2 ( output [6:0] O [1:0], input CLK ); -wire [6:0] Mux8xOutBits7_inst0_O; -wire [6:0] Mux8xOutBits7_inst1_O; +wire [6:0] Mux8xBits7_inst0_O; +wire [6:0] Mux8xBits7_inst1_O; wire [6:0] Register_inst0_O [7:0]; wire [2:0] Register_inst1_O; -Mux8xOutBits7 Mux8xOutBits7_inst0 ( +Mux8xBits7 Mux8xBits7_inst0 ( .I0(Register_inst0_O[0]), .I1(Register_inst0_O[1]), .I2(Register_inst0_O[2]), @@ -115,9 +115,9 @@ Mux8xOutBits7 Mux8xOutBits7_inst0 ( .I6(Register_inst0_O[6]), .I7(Register_inst0_O[7]), .S(index), - .O(Mux8xOutBits7_inst0_O) + .O(Mux8xBits7_inst0_O) ); -Mux8xOutBits7 Mux8xOutBits7_inst1 ( +Mux8xBits7 Mux8xBits7_inst1 ( .I0(Register_inst0_O[0]), .I1(Register_inst0_O[1]), .I2(Register_inst0_O[2]), @@ -127,7 +127,7 @@ Mux8xOutBits7 Mux8xOutBits7_inst1 ( .I6(Register_inst0_O[6]), .I7(Register_inst0_O[7]), .S(Register_inst1_O), - .O(Mux8xOutBits7_inst1_O) + .O(Mux8xBits7_inst1_O) ); wire [6:0] Register_inst0_I [7:0]; assign Register_inst0_I[7] = I[7]; @@ -148,7 +148,7 @@ Register_unq1 Register_inst1 ( .O(Register_inst1_O), .CLK(CLK) ); -assign O[1] = Mux8xOutBits7_inst1_O; -assign O[0] = Mux8xOutBits7_inst0_O; +assign O[1] = Mux8xBits7_inst1_O; +assign O[0] = Mux8xBits7_inst0_O; endmodule diff --git a/tests/test_syntax/gold/TestSequential2Slice.v b/tests/test_syntax/gold/TestSequential2Slice.v index 28d3edd0c..2aa5c6bf3 100644 --- a/tests/test_syntax/gold/TestSequential2Slice.v +++ b/tests/test_syntax/gold/TestSequential2Slice.v @@ -32,7 +32,7 @@ coreir_reg #( ); endmodule -module Mux56xOutBits8 ( +module Mux56xBits8 ( input [7:0] I0, input [7:0] I1, input [7:0] I2, @@ -880,7 +880,7 @@ Mux2xOutBit Mux2xOutBit_inst9 ( .S(magma_Bit_and_inst18_out), .O(Mux2xOutBit_inst9_O) ); -Mux56xOutBits8 Mux56xOutBits8_inst0 ( +Mux56xBits8 Mux56xBits8_inst0 ( .I0(Register_inst0_O[7:0]), .I1(Register_inst0_O[8:1]), .I2(Register_inst0_O[9:2]), diff --git a/tests/test_syntax/gold/basic_function_call.json b/tests/test_syntax/gold/basic_function_call.json index 21380db5e..8b9d1a620 100644 --- a/tests/test_syntax/gold/basic_function_call.json +++ b/tests/test_syntax/gold/basic_function_call.json @@ -2,7 +2,7 @@ "namespaces":{ "global":{ "modules":{ - "Mux2xOutBit":{ + "Mux2xBit":{ "type":["Record",[ ["I0","BitIn"], ["I1","BitIn"], @@ -29,15 +29,15 @@ ["O","Bit"] ]], "instances":{ - "Mux2xOutBit_inst0":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst0":{ + "modref":"global.Mux2xBit" } }, "connections":[ - ["self.I.1","Mux2xOutBit_inst0.I0"], - ["self.I.0","Mux2xOutBit_inst0.I1"], - ["self.O","Mux2xOutBit_inst0.O"], - ["self.S","Mux2xOutBit_inst0.S"] + ["self.I.1","Mux2xBit_inst0.I0"], + ["self.I.0","Mux2xBit_inst0.I1"], + ["self.O","Mux2xBit_inst0.O"], + ["self.S","Mux2xBit_inst0.S"] ] }, "basic_function_call":{ diff --git a/tests/test_syntax/gold/custom_env0.json b/tests/test_syntax/gold/custom_env0.json index edce1c227..2446c3fce 100644 --- a/tests/test_syntax/gold/custom_env0.json +++ b/tests/test_syntax/gold/custom_env0.json @@ -2,7 +2,7 @@ "namespaces":{ "global":{ "modules":{ - "Mux2xOutBit":{ + "Mux2xBit":{ "type":["Record",[ ["I0","BitIn"], ["I1","BitIn"], @@ -29,8 +29,8 @@ ["O","Bit"] ]], "instances":{ - "Mux2xOutBit_inst0":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst0":{ + "modref":"global.Mux2xBit" }, "bit_const_0_None":{ "modref":"corebit.const", @@ -38,10 +38,10 @@ } }, "connections":[ - ["bit_const_0_None.out","Mux2xOutBit_inst0.I0"], - ["self.I","Mux2xOutBit_inst0.I1"], - ["self.O","Mux2xOutBit_inst0.O"], - ["self.S","Mux2xOutBit_inst0.S"] + ["bit_const_0_None.out","Mux2xBit_inst0.I0"], + ["self.I","Mux2xBit_inst0.I1"], + ["self.O","Mux2xBit_inst0.O"], + ["self.S","Mux2xBit_inst0.S"] ] } } diff --git a/tests/test_syntax/gold/custom_env1.json b/tests/test_syntax/gold/custom_env1.json index 3c171a632..81470869e 100644 --- a/tests/test_syntax/gold/custom_env1.json +++ b/tests/test_syntax/gold/custom_env1.json @@ -2,7 +2,7 @@ "namespaces":{ "global":{ "modules":{ - "Mux2xOutBit":{ + "Mux2xBit":{ "type":["Record",[ ["I0","BitIn"], ["I1","BitIn"], @@ -29,8 +29,8 @@ ["O","Bit"] ]], "instances":{ - "Mux2xOutBit_inst0":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst0":{ + "modref":"global.Mux2xBit" }, "bit_const_1_None":{ "modref":"corebit.const", @@ -38,10 +38,10 @@ } }, "connections":[ - ["bit_const_1_None.out","Mux2xOutBit_inst0.I0"], - ["self.I","Mux2xOutBit_inst0.I1"], - ["self.O","Mux2xOutBit_inst0.O"], - ["self.S","Mux2xOutBit_inst0.S"] + ["bit_const_1_None.out","Mux2xBit_inst0.I0"], + ["self.I","Mux2xBit_inst0.I1"], + ["self.O","Mux2xBit_inst0.O"], + ["self.S","Mux2xBit_inst0.S"] ] } } diff --git a/tests/test_syntax/gold/if_statement_basic.json b/tests/test_syntax/gold/if_statement_basic.json index af5fb5f0f..ebd24bd74 100644 --- a/tests/test_syntax/gold/if_statement_basic.json +++ b/tests/test_syntax/gold/if_statement_basic.json @@ -2,7 +2,7 @@ "namespaces":{ "global":{ "modules":{ - "Mux2xOutBit":{ + "Mux2xBit":{ "type":["Record",[ ["I0","BitIn"], ["I1","BitIn"], @@ -29,15 +29,15 @@ ["O","Bit"] ]], "instances":{ - "Mux2xOutBit_inst0":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst0":{ + "modref":"global.Mux2xBit" } }, "connections":[ - ["self.I.1","Mux2xOutBit_inst0.I0"], - ["self.I.0","Mux2xOutBit_inst0.I1"], - ["self.O","Mux2xOutBit_inst0.O"], - ["self.S","Mux2xOutBit_inst0.S"] + ["self.I.1","Mux2xBit_inst0.I0"], + ["self.I.0","Mux2xBit_inst0.I1"], + ["self.O","Mux2xBit_inst0.O"], + ["self.S","Mux2xBit_inst0.S"] ] } } diff --git a/tests/test_syntax/gold/multiple_assign.json b/tests/test_syntax/gold/multiple_assign.json index 4752c7052..e42731c74 100644 --- a/tests/test_syntax/gold/multiple_assign.json +++ b/tests/test_syntax/gold/multiple_assign.json @@ -17,7 +17,7 @@ ["self.a","logic_inst0.a"] ] }, - "Mux2xOutBit":{ + "Mux2xBit":{ "type":["Record",[ ["I0","BitIn"], ["I1","BitIn"], @@ -59,8 +59,8 @@ ["O0","Bit"] ]], "instances":{ - "Mux2xOutBit_inst0":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst0":{ + "modref":"global.Mux2xBit" }, "bit_const_0_None":{ "modref":"corebit.const", @@ -75,10 +75,10 @@ } }, "connections":[ - ["bit_const_1_None.out","Mux2xOutBit_inst0.I0"], - ["bit_const_0_None.out","Mux2xOutBit_inst0.I1"], - ["self.O0","Mux2xOutBit_inst0.O"], - ["eq_inst0.O","Mux2xOutBit_inst0.S"], + ["bit_const_1_None.out","Mux2xBit_inst0.I0"], + ["bit_const_0_None.out","Mux2xBit_inst0.I1"], + ["self.O0","Mux2xBit_inst0.O"], + ["eq_inst0.O","Mux2xBit_inst0.S"], ["eq_inst0.I1","bit_const_0_None.out"], ["self.a","eq_inst0.I0"] ] diff --git a/tests/test_syntax/gold/optional_assignment.json b/tests/test_syntax/gold/optional_assignment.json index 026d9d100..865e0d6b5 100644 --- a/tests/test_syntax/gold/optional_assignment.json +++ b/tests/test_syntax/gold/optional_assignment.json @@ -19,7 +19,7 @@ ["self.a","logic_inst0.a"] ] }, - "Mux2xOutBit":{ + "Mux2xBit":{ "type":["Record",[ ["I0","BitIn"], ["I1","BitIn"], @@ -62,11 +62,11 @@ ["O1","Bit"] ]], "instances":{ - "Mux2xOutBit_inst0":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst0":{ + "modref":"global.Mux2xBit" }, - "Mux2xOutBit_inst1":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst1":{ + "modref":"global.Mux2xBit" }, "bit_const_0_None":{ "modref":"corebit.const", @@ -84,14 +84,14 @@ } }, "connections":[ - ["bit_const_1_None.out","Mux2xOutBit_inst0.I0"], - ["bit_const_1_None.out","Mux2xOutBit_inst0.I1"], - ["self.O1","Mux2xOutBit_inst0.O"], - ["eq_inst0.O","Mux2xOutBit_inst0.S"], - ["bit_const_0_None.out","Mux2xOutBit_inst1.I0"], - ["bit_const_1_None.out","Mux2xOutBit_inst1.I1"], - ["self.O0","Mux2xOutBit_inst1.O"], - ["eq_inst1.O","Mux2xOutBit_inst1.S"], + ["bit_const_1_None.out","Mux2xBit_inst0.I0"], + ["bit_const_1_None.out","Mux2xBit_inst0.I1"], + ["self.O1","Mux2xBit_inst0.O"], + ["eq_inst0.O","Mux2xBit_inst0.S"], + ["bit_const_0_None.out","Mux2xBit_inst1.I0"], + ["bit_const_1_None.out","Mux2xBit_inst1.I1"], + ["self.O0","Mux2xBit_inst1.O"], + ["eq_inst1.O","Mux2xBit_inst1.S"], ["eq_inst0.I1","bit_const_0_None.out"], ["eq_inst1.I1","bit_const_0_None.out"], ["self.a","eq_inst0.I0"], diff --git a/tests/test_syntax/gold/simple_circuit_1.json b/tests/test_syntax/gold/simple_circuit_1.json index 497925b8e..2efd5e325 100644 --- a/tests/test_syntax/gold/simple_circuit_1.json +++ b/tests/test_syntax/gold/simple_circuit_1.json @@ -17,7 +17,7 @@ ["self.a","logic_inst0.a"] ] }, - "Mux2xOutBit":{ + "Mux2xBit":{ "type":["Record",[ ["I0","BitIn"], ["I1","BitIn"], @@ -59,8 +59,8 @@ ["O0","Bit"] ]], "instances":{ - "Mux2xOutBit_inst0":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst0":{ + "modref":"global.Mux2xBit" }, "bit_const_0_None":{ "modref":"corebit.const", @@ -75,10 +75,10 @@ } }, "connections":[ - ["bit_const_0_None.out","Mux2xOutBit_inst0.I0"], - ["bit_const_1_None.out","Mux2xOutBit_inst0.I1"], - ["self.O0","Mux2xOutBit_inst0.O"], - ["eq_inst0.O","Mux2xOutBit_inst0.S"], + ["bit_const_0_None.out","Mux2xBit_inst0.I0"], + ["bit_const_1_None.out","Mux2xBit_inst0.I1"], + ["self.O0","Mux2xBit_inst0.O"], + ["eq_inst0.O","Mux2xBit_inst0.S"], ["eq_inst0.I1","bit_const_0_None.out"], ["self.a","eq_inst0.I0"] ] diff --git a/tests/test_syntax/gold/ternary.json b/tests/test_syntax/gold/ternary.json index cab83e009..e3fcc03ac 100644 --- a/tests/test_syntax/gold/ternary.json +++ b/tests/test_syntax/gold/ternary.json @@ -2,7 +2,7 @@ "namespaces":{ "global":{ "modules":{ - "Mux2xOutBit":{ + "Mux2xBit":{ "type":["Record",[ ["I0","BitIn"], ["I1","BitIn"], @@ -29,15 +29,15 @@ ["O","Bit"] ]], "instances":{ - "Mux2xOutBit_inst0":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst0":{ + "modref":"global.Mux2xBit" } }, "connections":[ - ["self.I.1","Mux2xOutBit_inst0.I0"], - ["self.I.0","Mux2xOutBit_inst0.I1"], - ["self.O","Mux2xOutBit_inst0.O"], - ["self.S","Mux2xOutBit_inst0.S"] + ["self.I.1","Mux2xBit_inst0.I0"], + ["self.I.0","Mux2xBit_inst0.I1"], + ["self.O","Mux2xBit_inst0.O"], + ["self.S","Mux2xBit_inst0.S"] ] } } diff --git a/tests/test_syntax/gold/ternary_nested.json b/tests/test_syntax/gold/ternary_nested.json index 560e073cc..df2478451 100644 --- a/tests/test_syntax/gold/ternary_nested.json +++ b/tests/test_syntax/gold/ternary_nested.json @@ -2,7 +2,7 @@ "namespaces":{ "global":{ "modules":{ - "Mux2xOutBit":{ + "Mux2xBit":{ "type":["Record",[ ["I0","BitIn"], ["I1","BitIn"], @@ -29,21 +29,21 @@ ["O","Bit"] ]], "instances":{ - "Mux2xOutBit_inst0":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst0":{ + "modref":"global.Mux2xBit" }, - "Mux2xOutBit_inst1":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst1":{ + "modref":"global.Mux2xBit" } }, "connections":[ - ["self.I.2","Mux2xOutBit_inst0.I0"], - ["self.I.1","Mux2xOutBit_inst0.I1"], - ["Mux2xOutBit_inst1.I0","Mux2xOutBit_inst0.O"], - ["self.S.1","Mux2xOutBit_inst0.S"], - ["self.I.0","Mux2xOutBit_inst1.I1"], - ["self.O","Mux2xOutBit_inst1.O"], - ["self.S.0","Mux2xOutBit_inst1.S"] + ["self.I.2","Mux2xBit_inst0.I0"], + ["self.I.1","Mux2xBit_inst0.I1"], + ["Mux2xBit_inst1.I0","Mux2xBit_inst0.O"], + ["self.S.1","Mux2xBit_inst0.S"], + ["self.I.0","Mux2xBit_inst1.I1"], + ["self.O","Mux2xBit_inst1.O"], + ["self.S.0","Mux2xBit_inst1.S"] ] } } diff --git a/tests/test_syntax/gold/ternary_nested2.json b/tests/test_syntax/gold/ternary_nested2.json index b69d85aa5..c7de4b123 100644 --- a/tests/test_syntax/gold/ternary_nested2.json +++ b/tests/test_syntax/gold/ternary_nested2.json @@ -2,7 +2,7 @@ "namespaces":{ "global":{ "modules":{ - "Mux2xOutBit":{ + "Mux2xBit":{ "type":["Record",[ ["I0","BitIn"], ["I1","BitIn"], @@ -29,21 +29,21 @@ ["O","Bit"] ]], "instances":{ - "Mux2xOutBit_inst0":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst0":{ + "modref":"global.Mux2xBit" }, - "Mux2xOutBit_inst1":{ - "modref":"global.Mux2xOutBit" + "Mux2xBit_inst1":{ + "modref":"global.Mux2xBit" } }, "connections":[ - ["self.I.1","Mux2xOutBit_inst0.I0"], - ["self.I.0","Mux2xOutBit_inst0.I1"], - ["Mux2xOutBit_inst1.I1","Mux2xOutBit_inst0.O"], - ["self.S.0","Mux2xOutBit_inst0.S"], - ["self.I.2","Mux2xOutBit_inst1.I0"], - ["self.O","Mux2xOutBit_inst1.O"], - ["self.S.1","Mux2xOutBit_inst1.S"] + ["self.I.1","Mux2xBit_inst0.I0"], + ["self.I.0","Mux2xBit_inst0.I1"], + ["Mux2xBit_inst1.I1","Mux2xBit_inst0.O"], + ["self.S.0","Mux2xBit_inst0.S"], + ["self.I.2","Mux2xBit_inst1.I0"], + ["self.O","Mux2xBit_inst1.O"], + ["self.S.1","Mux2xBit_inst1.S"] ] } } diff --git a/tests/test_type/gold/test_ndarray_dynamic_getitem.v b/tests/test_type/gold/test_ndarray_dynamic_getitem.v index 9ba2487cd..e8ba44472 100644 --- a/tests/test_type/gold/test_ndarray_dynamic_getitem.v +++ b/tests/test_type/gold/test_ndarray_dynamic_getitem.v @@ -47,7 +47,7 @@ assign O[0][1] = reg_P_inst0_out[3:2]; assign O[0][0] = reg_P_inst0_out[1:0]; endmodule -module Mux4xArray3_Array2_OutBit ( +module Mux4xArray3_Array2_Bit ( input [1:0] I0 [2:0], input [1:0] I1 [2:0], input [1:0] I2 [2:0], @@ -78,31 +78,31 @@ module Main ( input [1:0] raddr, input CLK ); -wire [1:0] Mux4xArray3_Array2_OutBit_inst0_O [2:0]; +wire [1:0] Mux4xArray3_Array2_Bit_inst0_O [2:0]; wire [1:0] Register_inst0_O [3:0][2:0]; -wire [1:0] Mux4xArray3_Array2_OutBit_inst0_I0 [2:0]; -assign Mux4xArray3_Array2_OutBit_inst0_I0[2] = Register_inst0_O[0][2]; -assign Mux4xArray3_Array2_OutBit_inst0_I0[1] = Register_inst0_O[0][1]; -assign Mux4xArray3_Array2_OutBit_inst0_I0[0] = Register_inst0_O[0][0]; -wire [1:0] Mux4xArray3_Array2_OutBit_inst0_I1 [2:0]; -assign Mux4xArray3_Array2_OutBit_inst0_I1[2] = Register_inst0_O[1][2]; -assign Mux4xArray3_Array2_OutBit_inst0_I1[1] = Register_inst0_O[1][1]; -assign Mux4xArray3_Array2_OutBit_inst0_I1[0] = Register_inst0_O[1][0]; -wire [1:0] Mux4xArray3_Array2_OutBit_inst0_I2 [2:0]; -assign Mux4xArray3_Array2_OutBit_inst0_I2[2] = Register_inst0_O[2][2]; -assign Mux4xArray3_Array2_OutBit_inst0_I2[1] = Register_inst0_O[2][1]; -assign Mux4xArray3_Array2_OutBit_inst0_I2[0] = Register_inst0_O[2][0]; -wire [1:0] Mux4xArray3_Array2_OutBit_inst0_I3 [2:0]; -assign Mux4xArray3_Array2_OutBit_inst0_I3[2] = Register_inst0_O[3][2]; -assign Mux4xArray3_Array2_OutBit_inst0_I3[1] = Register_inst0_O[3][1]; -assign Mux4xArray3_Array2_OutBit_inst0_I3[0] = Register_inst0_O[3][0]; -Mux4xArray3_Array2_OutBit Mux4xArray3_Array2_OutBit_inst0 ( - .I0(Mux4xArray3_Array2_OutBit_inst0_I0), - .I1(Mux4xArray3_Array2_OutBit_inst0_I1), - .I2(Mux4xArray3_Array2_OutBit_inst0_I2), - .I3(Mux4xArray3_Array2_OutBit_inst0_I3), +wire [1:0] Mux4xArray3_Array2_Bit_inst0_I0 [2:0]; +assign Mux4xArray3_Array2_Bit_inst0_I0[2] = Register_inst0_O[0][2]; +assign Mux4xArray3_Array2_Bit_inst0_I0[1] = Register_inst0_O[0][1]; +assign Mux4xArray3_Array2_Bit_inst0_I0[0] = Register_inst0_O[0][0]; +wire [1:0] Mux4xArray3_Array2_Bit_inst0_I1 [2:0]; +assign Mux4xArray3_Array2_Bit_inst0_I1[2] = Register_inst0_O[1][2]; +assign Mux4xArray3_Array2_Bit_inst0_I1[1] = Register_inst0_O[1][1]; +assign Mux4xArray3_Array2_Bit_inst0_I1[0] = Register_inst0_O[1][0]; +wire [1:0] Mux4xArray3_Array2_Bit_inst0_I2 [2:0]; +assign Mux4xArray3_Array2_Bit_inst0_I2[2] = Register_inst0_O[2][2]; +assign Mux4xArray3_Array2_Bit_inst0_I2[1] = Register_inst0_O[2][1]; +assign Mux4xArray3_Array2_Bit_inst0_I2[0] = Register_inst0_O[2][0]; +wire [1:0] Mux4xArray3_Array2_Bit_inst0_I3 [2:0]; +assign Mux4xArray3_Array2_Bit_inst0_I3[2] = Register_inst0_O[3][2]; +assign Mux4xArray3_Array2_Bit_inst0_I3[1] = Register_inst0_O[3][1]; +assign Mux4xArray3_Array2_Bit_inst0_I3[0] = Register_inst0_O[3][0]; +Mux4xArray3_Array2_Bit Mux4xArray3_Array2_Bit_inst0 ( + .I0(Mux4xArray3_Array2_Bit_inst0_I0), + .I1(Mux4xArray3_Array2_Bit_inst0_I1), + .I2(Mux4xArray3_Array2_Bit_inst0_I2), + .I3(Mux4xArray3_Array2_Bit_inst0_I3), .S(raddr), - .O(Mux4xArray3_Array2_OutBit_inst0_O) + .O(Mux4xArray3_Array2_Bit_inst0_O) ); wire [1:0] Register_inst0_I [3:0][2:0]; assign Register_inst0_I[3][2] = Register_inst0_O[3][2]; @@ -122,8 +122,8 @@ Register Register_inst0 ( .O(Register_inst0_O), .CLK(CLK) ); -assign rdata[2] = Mux4xArray3_Array2_OutBit_inst0_O[2]; -assign rdata[1] = Mux4xArray3_Array2_OutBit_inst0_O[1]; -assign rdata[0] = Mux4xArray3_Array2_OutBit_inst0_O[0]; +assign rdata[2] = Mux4xArray3_Array2_Bit_inst0_O[2]; +assign rdata[1] = Mux4xArray3_Array2_Bit_inst0_O[1]; +assign rdata[0] = Mux4xArray3_Array2_Bit_inst0_O[0]; endmodule diff --git a/tests/test_type/gold/test_ndarray_dynamic_getitem2.v b/tests/test_type/gold/test_ndarray_dynamic_getitem2.v index 7c2f936ed..c20f427f9 100644 --- a/tests/test_type/gold/test_ndarray_dynamic_getitem2.v +++ b/tests/test_type/gold/test_ndarray_dynamic_getitem2.v @@ -59,7 +59,7 @@ assign O[0][0][1] = reg_P_inst0_out[3:2]; assign O[0][0][0] = reg_P_inst0_out[1:0]; endmodule -module Mux4xArray3_Array2_OutBit ( +module Mux4xArray3_Array2_Bit ( input [1:0] I0 [2:0], input [1:0] I1 [2:0], input [1:0] I2 [2:0], @@ -92,56 +92,56 @@ module Main ( input [1:0] raddr1, input CLK ); -wire [1:0] Mux4xArray3_Array2_OutBit_inst0_O [2:0]; -wire [1:0] Mux4xArray3_Array2_OutBit_inst1_O [2:0]; +wire [1:0] Mux4xArray3_Array2_Bit_inst0_O [2:0]; +wire [1:0] Mux4xArray3_Array2_Bit_inst1_O [2:0]; wire [1:0] Register_inst0_O [1:0][3:0][2:0]; -wire [1:0] Mux4xArray3_Array2_OutBit_inst0_I0 [2:0]; -assign Mux4xArray3_Array2_OutBit_inst0_I0[2] = Register_inst0_O[0][0][2]; -assign Mux4xArray3_Array2_OutBit_inst0_I0[1] = Register_inst0_O[0][0][1]; -assign Mux4xArray3_Array2_OutBit_inst0_I0[0] = Register_inst0_O[0][0][0]; -wire [1:0] Mux4xArray3_Array2_OutBit_inst0_I1 [2:0]; -assign Mux4xArray3_Array2_OutBit_inst0_I1[2] = Register_inst0_O[0][1][2]; -assign Mux4xArray3_Array2_OutBit_inst0_I1[1] = Register_inst0_O[0][1][1]; -assign Mux4xArray3_Array2_OutBit_inst0_I1[0] = Register_inst0_O[0][1][0]; -wire [1:0] Mux4xArray3_Array2_OutBit_inst0_I2 [2:0]; -assign Mux4xArray3_Array2_OutBit_inst0_I2[2] = Register_inst0_O[0][2][2]; -assign Mux4xArray3_Array2_OutBit_inst0_I2[1] = Register_inst0_O[0][2][1]; -assign Mux4xArray3_Array2_OutBit_inst0_I2[0] = Register_inst0_O[0][2][0]; -wire [1:0] Mux4xArray3_Array2_OutBit_inst0_I3 [2:0]; -assign Mux4xArray3_Array2_OutBit_inst0_I3[2] = Register_inst0_O[0][3][2]; -assign Mux4xArray3_Array2_OutBit_inst0_I3[1] = Register_inst0_O[0][3][1]; -assign Mux4xArray3_Array2_OutBit_inst0_I3[0] = Register_inst0_O[0][3][0]; -Mux4xArray3_Array2_OutBit Mux4xArray3_Array2_OutBit_inst0 ( - .I0(Mux4xArray3_Array2_OutBit_inst0_I0), - .I1(Mux4xArray3_Array2_OutBit_inst0_I1), - .I2(Mux4xArray3_Array2_OutBit_inst0_I2), - .I3(Mux4xArray3_Array2_OutBit_inst0_I3), +wire [1:0] Mux4xArray3_Array2_Bit_inst0_I0 [2:0]; +assign Mux4xArray3_Array2_Bit_inst0_I0[2] = Register_inst0_O[0][0][2]; +assign Mux4xArray3_Array2_Bit_inst0_I0[1] = Register_inst0_O[0][0][1]; +assign Mux4xArray3_Array2_Bit_inst0_I0[0] = Register_inst0_O[0][0][0]; +wire [1:0] Mux4xArray3_Array2_Bit_inst0_I1 [2:0]; +assign Mux4xArray3_Array2_Bit_inst0_I1[2] = Register_inst0_O[0][1][2]; +assign Mux4xArray3_Array2_Bit_inst0_I1[1] = Register_inst0_O[0][1][1]; +assign Mux4xArray3_Array2_Bit_inst0_I1[0] = Register_inst0_O[0][1][0]; +wire [1:0] Mux4xArray3_Array2_Bit_inst0_I2 [2:0]; +assign Mux4xArray3_Array2_Bit_inst0_I2[2] = Register_inst0_O[0][2][2]; +assign Mux4xArray3_Array2_Bit_inst0_I2[1] = Register_inst0_O[0][2][1]; +assign Mux4xArray3_Array2_Bit_inst0_I2[0] = Register_inst0_O[0][2][0]; +wire [1:0] Mux4xArray3_Array2_Bit_inst0_I3 [2:0]; +assign Mux4xArray3_Array2_Bit_inst0_I3[2] = Register_inst0_O[0][3][2]; +assign Mux4xArray3_Array2_Bit_inst0_I3[1] = Register_inst0_O[0][3][1]; +assign Mux4xArray3_Array2_Bit_inst0_I3[0] = Register_inst0_O[0][3][0]; +Mux4xArray3_Array2_Bit Mux4xArray3_Array2_Bit_inst0 ( + .I0(Mux4xArray3_Array2_Bit_inst0_I0), + .I1(Mux4xArray3_Array2_Bit_inst0_I1), + .I2(Mux4xArray3_Array2_Bit_inst0_I2), + .I3(Mux4xArray3_Array2_Bit_inst0_I3), .S(raddr0), - .O(Mux4xArray3_Array2_OutBit_inst0_O) + .O(Mux4xArray3_Array2_Bit_inst0_O) ); -wire [1:0] Mux4xArray3_Array2_OutBit_inst1_I0 [2:0]; -assign Mux4xArray3_Array2_OutBit_inst1_I0[2] = Register_inst0_O[1][0][2]; -assign Mux4xArray3_Array2_OutBit_inst1_I0[1] = Register_inst0_O[1][0][1]; -assign Mux4xArray3_Array2_OutBit_inst1_I0[0] = Register_inst0_O[1][0][0]; -wire [1:0] Mux4xArray3_Array2_OutBit_inst1_I1 [2:0]; -assign Mux4xArray3_Array2_OutBit_inst1_I1[2] = Register_inst0_O[1][1][2]; -assign Mux4xArray3_Array2_OutBit_inst1_I1[1] = Register_inst0_O[1][1][1]; -assign Mux4xArray3_Array2_OutBit_inst1_I1[0] = Register_inst0_O[1][1][0]; -wire [1:0] Mux4xArray3_Array2_OutBit_inst1_I2 [2:0]; -assign Mux4xArray3_Array2_OutBit_inst1_I2[2] = Register_inst0_O[1][2][2]; -assign Mux4xArray3_Array2_OutBit_inst1_I2[1] = Register_inst0_O[1][2][1]; -assign Mux4xArray3_Array2_OutBit_inst1_I2[0] = Register_inst0_O[1][2][0]; -wire [1:0] Mux4xArray3_Array2_OutBit_inst1_I3 [2:0]; -assign Mux4xArray3_Array2_OutBit_inst1_I3[2] = Register_inst0_O[1][3][2]; -assign Mux4xArray3_Array2_OutBit_inst1_I3[1] = Register_inst0_O[1][3][1]; -assign Mux4xArray3_Array2_OutBit_inst1_I3[0] = Register_inst0_O[1][3][0]; -Mux4xArray3_Array2_OutBit Mux4xArray3_Array2_OutBit_inst1 ( - .I0(Mux4xArray3_Array2_OutBit_inst1_I0), - .I1(Mux4xArray3_Array2_OutBit_inst1_I1), - .I2(Mux4xArray3_Array2_OutBit_inst1_I2), - .I3(Mux4xArray3_Array2_OutBit_inst1_I3), +wire [1:0] Mux4xArray3_Array2_Bit_inst1_I0 [2:0]; +assign Mux4xArray3_Array2_Bit_inst1_I0[2] = Register_inst0_O[1][0][2]; +assign Mux4xArray3_Array2_Bit_inst1_I0[1] = Register_inst0_O[1][0][1]; +assign Mux4xArray3_Array2_Bit_inst1_I0[0] = Register_inst0_O[1][0][0]; +wire [1:0] Mux4xArray3_Array2_Bit_inst1_I1 [2:0]; +assign Mux4xArray3_Array2_Bit_inst1_I1[2] = Register_inst0_O[1][1][2]; +assign Mux4xArray3_Array2_Bit_inst1_I1[1] = Register_inst0_O[1][1][1]; +assign Mux4xArray3_Array2_Bit_inst1_I1[0] = Register_inst0_O[1][1][0]; +wire [1:0] Mux4xArray3_Array2_Bit_inst1_I2 [2:0]; +assign Mux4xArray3_Array2_Bit_inst1_I2[2] = Register_inst0_O[1][2][2]; +assign Mux4xArray3_Array2_Bit_inst1_I2[1] = Register_inst0_O[1][2][1]; +assign Mux4xArray3_Array2_Bit_inst1_I2[0] = Register_inst0_O[1][2][0]; +wire [1:0] Mux4xArray3_Array2_Bit_inst1_I3 [2:0]; +assign Mux4xArray3_Array2_Bit_inst1_I3[2] = Register_inst0_O[1][3][2]; +assign Mux4xArray3_Array2_Bit_inst1_I3[1] = Register_inst0_O[1][3][1]; +assign Mux4xArray3_Array2_Bit_inst1_I3[0] = Register_inst0_O[1][3][0]; +Mux4xArray3_Array2_Bit Mux4xArray3_Array2_Bit_inst1 ( + .I0(Mux4xArray3_Array2_Bit_inst1_I0), + .I1(Mux4xArray3_Array2_Bit_inst1_I1), + .I2(Mux4xArray3_Array2_Bit_inst1_I2), + .I3(Mux4xArray3_Array2_Bit_inst1_I3), .S(raddr1), - .O(Mux4xArray3_Array2_OutBit_inst1_O) + .O(Mux4xArray3_Array2_Bit_inst1_O) ); wire [1:0] Register_inst0_I [1:0][3:0][2:0]; assign Register_inst0_I[1][3][2] = Register_inst0_O[1][3][2]; @@ -173,11 +173,11 @@ Register Register_inst0 ( .O(Register_inst0_O), .CLK(CLK) ); -assign rdata0[2] = Mux4xArray3_Array2_OutBit_inst0_O[2]; -assign rdata0[1] = Mux4xArray3_Array2_OutBit_inst0_O[1]; -assign rdata0[0] = Mux4xArray3_Array2_OutBit_inst0_O[0]; -assign rdata1[2] = Mux4xArray3_Array2_OutBit_inst1_O[2]; -assign rdata1[1] = Mux4xArray3_Array2_OutBit_inst1_O[1]; -assign rdata1[0] = Mux4xArray3_Array2_OutBit_inst1_O[0]; +assign rdata0[2] = Mux4xArray3_Array2_Bit_inst0_O[2]; +assign rdata0[1] = Mux4xArray3_Array2_Bit_inst0_O[1]; +assign rdata0[0] = Mux4xArray3_Array2_Bit_inst0_O[0]; +assign rdata1[2] = Mux4xArray3_Array2_Bit_inst1_O[2]; +assign rdata1[1] = Mux4xArray3_Array2_Bit_inst1_O[1]; +assign rdata1[0] = Mux4xArray3_Array2_Bit_inst1_O[0]; endmodule diff --git a/tests/test_type/gold/test_ndarray_dynamic_getitem3.v b/tests/test_type/gold/test_ndarray_dynamic_getitem3.v index 68d0ff30e..cc4dfcde6 100644 --- a/tests/test_type/gold/test_ndarray_dynamic_getitem3.v +++ b/tests/test_type/gold/test_ndarray_dynamic_getitem3.v @@ -59,7 +59,7 @@ assign O[0][0][1] = reg_P_inst0_out[3:2]; assign O[0][0][0] = reg_P_inst0_out[1:0]; endmodule -module Mux4xArray2_Array3_Array2_OutBit ( +module Mux4xArray2_Array3_Array2_Bit ( input [1:0] I0 [1:0][2:0], input [1:0] I1 [1:0][2:0], input [1:0] I2 [1:0][2:0], @@ -95,80 +95,80 @@ module Main ( input [1:0] raddr1, input CLK ); -wire [1:0] Mux4xArray2_Array3_Array2_OutBit_inst0_O [1:0][2:0]; -wire [1:0] Mux4xArray2_Array3_Array2_OutBit_inst1_O [1:0][2:0]; +wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_O [1:0][2:0]; +wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst1_O [1:0][2:0]; wire [1:0] Register_inst0_O [3:0][1:0][2:0]; -wire [1:0] Mux4xArray2_Array3_Array2_OutBit_inst0_I0 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I0[1][2] = Register_inst0_O[0][1][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I0[1][1] = Register_inst0_O[0][1][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I0[1][0] = Register_inst0_O[0][1][0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I0[0][2] = Register_inst0_O[0][0][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I0[0][1] = Register_inst0_O[0][0][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I0[0][0] = Register_inst0_O[0][0][0]; -wire [1:0] Mux4xArray2_Array3_Array2_OutBit_inst0_I1 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I1[1][2] = Register_inst0_O[1][1][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I1[1][1] = Register_inst0_O[1][1][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I1[1][0] = Register_inst0_O[1][1][0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I1[0][2] = Register_inst0_O[1][0][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I1[0][1] = Register_inst0_O[1][0][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I1[0][0] = Register_inst0_O[1][0][0]; -wire [1:0] Mux4xArray2_Array3_Array2_OutBit_inst0_I2 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I2[1][2] = Register_inst0_O[2][1][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I2[1][1] = Register_inst0_O[2][1][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I2[1][0] = Register_inst0_O[2][1][0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I2[0][2] = Register_inst0_O[2][0][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I2[0][1] = Register_inst0_O[2][0][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I2[0][0] = Register_inst0_O[2][0][0]; -wire [1:0] Mux4xArray2_Array3_Array2_OutBit_inst0_I3 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I3[1][2] = Register_inst0_O[3][1][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I3[1][1] = Register_inst0_O[3][1][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I3[1][0] = Register_inst0_O[3][1][0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I3[0][2] = Register_inst0_O[3][0][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I3[0][1] = Register_inst0_O[3][0][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I3[0][0] = Register_inst0_O[3][0][0]; -Mux4xArray2_Array3_Array2_OutBit Mux4xArray2_Array3_Array2_OutBit_inst0 ( - .I0(Mux4xArray2_Array3_Array2_OutBit_inst0_I0), - .I1(Mux4xArray2_Array3_Array2_OutBit_inst0_I1), - .I2(Mux4xArray2_Array3_Array2_OutBit_inst0_I2), - .I3(Mux4xArray2_Array3_Array2_OutBit_inst0_I3), +wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_I0 [1:0][2:0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[1][2] = Register_inst0_O[0][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[1][1] = Register_inst0_O[0][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[1][0] = Register_inst0_O[0][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[0][2] = Register_inst0_O[0][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[0][1] = Register_inst0_O[0][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[0][0] = Register_inst0_O[0][0][0]; +wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_I1 [1:0][2:0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[1][2] = Register_inst0_O[1][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[1][1] = Register_inst0_O[1][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[1][0] = Register_inst0_O[1][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[0][2] = Register_inst0_O[1][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[0][1] = Register_inst0_O[1][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[0][0] = Register_inst0_O[1][0][0]; +wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_I2 [1:0][2:0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[1][2] = Register_inst0_O[2][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[1][1] = Register_inst0_O[2][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[1][0] = Register_inst0_O[2][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[0][2] = Register_inst0_O[2][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[0][1] = Register_inst0_O[2][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[0][0] = Register_inst0_O[2][0][0]; +wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_I3 [1:0][2:0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[1][2] = Register_inst0_O[3][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[1][1] = Register_inst0_O[3][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[1][0] = Register_inst0_O[3][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[0][2] = Register_inst0_O[3][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[0][1] = Register_inst0_O[3][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[0][0] = Register_inst0_O[3][0][0]; +Mux4xArray2_Array3_Array2_Bit Mux4xArray2_Array3_Array2_Bit_inst0 ( + .I0(Mux4xArray2_Array3_Array2_Bit_inst0_I0), + .I1(Mux4xArray2_Array3_Array2_Bit_inst0_I1), + .I2(Mux4xArray2_Array3_Array2_Bit_inst0_I2), + .I3(Mux4xArray2_Array3_Array2_Bit_inst0_I3), .S(raddr0), - .O(Mux4xArray2_Array3_Array2_OutBit_inst0_O) + .O(Mux4xArray2_Array3_Array2_Bit_inst0_O) ); -wire [1:0] Mux4xArray2_Array3_Array2_OutBit_inst1_I0 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I0[1][2] = Register_inst0_O[0][1][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I0[1][1] = Register_inst0_O[0][1][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I0[1][0] = Register_inst0_O[0][1][0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I0[0][2] = Register_inst0_O[0][0][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I0[0][1] = Register_inst0_O[0][0][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I0[0][0] = Register_inst0_O[0][0][0]; -wire [1:0] Mux4xArray2_Array3_Array2_OutBit_inst1_I1 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I1[1][2] = Register_inst0_O[1][1][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I1[1][1] = Register_inst0_O[1][1][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I1[1][0] = Register_inst0_O[1][1][0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I1[0][2] = Register_inst0_O[1][0][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I1[0][1] = Register_inst0_O[1][0][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I1[0][0] = Register_inst0_O[1][0][0]; -wire [1:0] Mux4xArray2_Array3_Array2_OutBit_inst1_I2 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I2[1][2] = Register_inst0_O[2][1][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I2[1][1] = Register_inst0_O[2][1][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I2[1][0] = Register_inst0_O[2][1][0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I2[0][2] = Register_inst0_O[2][0][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I2[0][1] = Register_inst0_O[2][0][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I2[0][0] = Register_inst0_O[2][0][0]; -wire [1:0] Mux4xArray2_Array3_Array2_OutBit_inst1_I3 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I3[1][2] = Register_inst0_O[3][1][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I3[1][1] = Register_inst0_O[3][1][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I3[1][0] = Register_inst0_O[3][1][0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I3[0][2] = Register_inst0_O[3][0][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I3[0][1] = Register_inst0_O[3][0][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst1_I3[0][0] = Register_inst0_O[3][0][0]; -Mux4xArray2_Array3_Array2_OutBit Mux4xArray2_Array3_Array2_OutBit_inst1 ( - .I0(Mux4xArray2_Array3_Array2_OutBit_inst1_I0), - .I1(Mux4xArray2_Array3_Array2_OutBit_inst1_I1), - .I2(Mux4xArray2_Array3_Array2_OutBit_inst1_I2), - .I3(Mux4xArray2_Array3_Array2_OutBit_inst1_I3), +wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst1_I0 [1:0][2:0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[1][2] = Register_inst0_O[0][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[1][1] = Register_inst0_O[0][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[1][0] = Register_inst0_O[0][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[0][2] = Register_inst0_O[0][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[0][1] = Register_inst0_O[0][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[0][0] = Register_inst0_O[0][0][0]; +wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst1_I1 [1:0][2:0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[1][2] = Register_inst0_O[1][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[1][1] = Register_inst0_O[1][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[1][0] = Register_inst0_O[1][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[0][2] = Register_inst0_O[1][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[0][1] = Register_inst0_O[1][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[0][0] = Register_inst0_O[1][0][0]; +wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst1_I2 [1:0][2:0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[1][2] = Register_inst0_O[2][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[1][1] = Register_inst0_O[2][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[1][0] = Register_inst0_O[2][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[0][2] = Register_inst0_O[2][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[0][1] = Register_inst0_O[2][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[0][0] = Register_inst0_O[2][0][0]; +wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst1_I3 [1:0][2:0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[1][2] = Register_inst0_O[3][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[1][1] = Register_inst0_O[3][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[1][0] = Register_inst0_O[3][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[0][2] = Register_inst0_O[3][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[0][1] = Register_inst0_O[3][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[0][0] = Register_inst0_O[3][0][0]; +Mux4xArray2_Array3_Array2_Bit Mux4xArray2_Array3_Array2_Bit_inst1 ( + .I0(Mux4xArray2_Array3_Array2_Bit_inst1_I0), + .I1(Mux4xArray2_Array3_Array2_Bit_inst1_I1), + .I2(Mux4xArray2_Array3_Array2_Bit_inst1_I2), + .I3(Mux4xArray2_Array3_Array2_Bit_inst1_I3), .S(raddr1), - .O(Mux4xArray2_Array3_Array2_OutBit_inst1_O) + .O(Mux4xArray2_Array3_Array2_Bit_inst1_O) ); wire [1:0] Register_inst0_I [3:0][1:0][2:0]; assign Register_inst0_I[3][1][2] = Register_inst0_O[3][1][2]; @@ -200,11 +200,11 @@ Register Register_inst0 ( .O(Register_inst0_O), .CLK(CLK) ); -assign rdata0[2] = Mux4xArray2_Array3_Array2_OutBit_inst0_O[0][2]; -assign rdata0[1] = Mux4xArray2_Array3_Array2_OutBit_inst0_O[0][1]; -assign rdata0[0] = Mux4xArray2_Array3_Array2_OutBit_inst0_O[0][0]; -assign rdata1[2] = Mux4xArray2_Array3_Array2_OutBit_inst1_O[1][2]; -assign rdata1[1] = Mux4xArray2_Array3_Array2_OutBit_inst1_O[1][1]; -assign rdata1[0] = Mux4xArray2_Array3_Array2_OutBit_inst1_O[1][0]; +assign rdata0[2] = Mux4xArray2_Array3_Array2_Bit_inst0_O[0][2]; +assign rdata0[1] = Mux4xArray2_Array3_Array2_Bit_inst0_O[0][1]; +assign rdata0[0] = Mux4xArray2_Array3_Array2_Bit_inst0_O[0][0]; +assign rdata1[2] = Mux4xArray2_Array3_Array2_Bit_inst1_O[1][2]; +assign rdata1[1] = Mux4xArray2_Array3_Array2_Bit_inst1_O[1][1]; +assign rdata1[0] = Mux4xArray2_Array3_Array2_Bit_inst1_O[1][0]; endmodule diff --git a/tests/test_type/gold/test_ndarray_get_slice.v b/tests/test_type/gold/test_ndarray_get_slice.v index 3bbedb754..4fe6d3f1a 100644 --- a/tests/test_type/gold/test_ndarray_get_slice.v +++ b/tests/test_type/gold/test_ndarray_get_slice.v @@ -1,4 +1,4 @@ -module Mux4xArray2_Array3_Array2_OutBit ( +module Mux4xArray2_Array3_Array2_Bit ( input [1:0] I0 [1:0][2:0], input [1:0] I1 [1:0][2:0], input [1:0] I2 [1:0][2:0], @@ -32,48 +32,48 @@ module Main ( input [1:0] x, output [1:0] O [1:0][2:0] ); -wire [1:0] Mux4xArray2_Array3_Array2_OutBit_inst0_O [1:0][2:0]; -wire [1:0] Mux4xArray2_Array3_Array2_OutBit_inst0_I0 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I0[1][2] = I[1][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I0[1][1] = I[1][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I0[1][0] = I[1][0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I0[0][2] = I[0][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I0[0][1] = I[0][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I0[0][0] = I[0][0]; -wire [1:0] Mux4xArray2_Array3_Array2_OutBit_inst0_I1 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I1[1][2] = I[2][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I1[1][1] = I[2][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I1[1][0] = I[2][0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I1[0][2] = I[1][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I1[0][1] = I[1][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I1[0][0] = I[1][0]; -wire [1:0] Mux4xArray2_Array3_Array2_OutBit_inst0_I2 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I2[1][2] = I[3][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I2[1][1] = I[3][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I2[1][0] = I[3][0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I2[0][2] = I[2][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I2[0][1] = I[2][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I2[0][0] = I[2][0]; -wire [1:0] Mux4xArray2_Array3_Array2_OutBit_inst0_I3 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I3[1][2] = I[4][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I3[1][1] = I[4][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I3[1][0] = I[4][0]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I3[0][2] = I[3][2]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I3[0][1] = I[3][1]; -assign Mux4xArray2_Array3_Array2_OutBit_inst0_I3[0][0] = I[3][0]; -Mux4xArray2_Array3_Array2_OutBit Mux4xArray2_Array3_Array2_OutBit_inst0 ( - .I0(Mux4xArray2_Array3_Array2_OutBit_inst0_I0), - .I1(Mux4xArray2_Array3_Array2_OutBit_inst0_I1), - .I2(Mux4xArray2_Array3_Array2_OutBit_inst0_I2), - .I3(Mux4xArray2_Array3_Array2_OutBit_inst0_I3), +wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_O [1:0][2:0]; +wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_I0 [1:0][2:0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[1][2] = I[1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[1][1] = I[1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[1][0] = I[1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[0][2] = I[0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[0][1] = I[0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[0][0] = I[0][0]; +wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_I1 [1:0][2:0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[1][2] = I[2][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[1][1] = I[2][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[1][0] = I[2][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[0][2] = I[1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[0][1] = I[1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[0][0] = I[1][0]; +wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_I2 [1:0][2:0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[1][2] = I[3][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[1][1] = I[3][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[1][0] = I[3][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[0][2] = I[2][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[0][1] = I[2][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[0][0] = I[2][0]; +wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_I3 [1:0][2:0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[1][2] = I[4][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[1][1] = I[4][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[1][0] = I[4][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[0][2] = I[3][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[0][1] = I[3][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[0][0] = I[3][0]; +Mux4xArray2_Array3_Array2_Bit Mux4xArray2_Array3_Array2_Bit_inst0 ( + .I0(Mux4xArray2_Array3_Array2_Bit_inst0_I0), + .I1(Mux4xArray2_Array3_Array2_Bit_inst0_I1), + .I2(Mux4xArray2_Array3_Array2_Bit_inst0_I2), + .I3(Mux4xArray2_Array3_Array2_Bit_inst0_I3), .S(x), - .O(Mux4xArray2_Array3_Array2_OutBit_inst0_O) + .O(Mux4xArray2_Array3_Array2_Bit_inst0_O) ); -assign O[1][2] = Mux4xArray2_Array3_Array2_OutBit_inst0_O[1][2]; -assign O[1][1] = Mux4xArray2_Array3_Array2_OutBit_inst0_O[1][1]; -assign O[1][0] = Mux4xArray2_Array3_Array2_OutBit_inst0_O[1][0]; -assign O[0][2] = Mux4xArray2_Array3_Array2_OutBit_inst0_O[0][2]; -assign O[0][1] = Mux4xArray2_Array3_Array2_OutBit_inst0_O[0][1]; -assign O[0][0] = Mux4xArray2_Array3_Array2_OutBit_inst0_O[0][0]; +assign O[1][2] = Mux4xArray2_Array3_Array2_Bit_inst0_O[1][2]; +assign O[1][1] = Mux4xArray2_Array3_Array2_Bit_inst0_O[1][1]; +assign O[1][0] = Mux4xArray2_Array3_Array2_Bit_inst0_O[1][0]; +assign O[0][2] = Mux4xArray2_Array3_Array2_Bit_inst0_O[0][2]; +assign O[0][1] = Mux4xArray2_Array3_Array2_Bit_inst0_O[0][1]; +assign O[0][0] = Mux4xArray2_Array3_Array2_Bit_inst0_O[0][0]; endmodule diff --git a/tests/test_type/gold/test_ndarray_set_slice.v b/tests/test_type/gold/test_ndarray_set_slice.v index ecefe173f..5e07c4625 100644 --- a/tests/test_type/gold/test_ndarray_set_slice.v +++ b/tests/test_type/gold/test_ndarray_set_slice.v @@ -18,23 +18,43 @@ assign O[1] = coreir_commonlib_mux2x6_inst0_out_unq1[3:2]; assign O[0] = coreir_commonlib_mux2x6_inst0_out_unq1[1:0]; endmodule +module Mux2xArray3_Array2_Bit ( + input [1:0] I0 [2:0], + input [1:0] I1 [2:0], + input S, + output [1:0] O [2:0] +); +reg [5:0] coreir_commonlib_mux2x6_inst0_out_unq1; +always @(*) begin +if (S == 0) begin + coreir_commonlib_mux2x6_inst0_out_unq1 = {I0[2][1:0],I0[1][1:0],I0[0][1:0]}; +end else begin + coreir_commonlib_mux2x6_inst0_out_unq1 = {I1[2][1:0],I1[1][1:0],I1[0][1:0]}; +end +end + +assign O[2] = coreir_commonlib_mux2x6_inst0_out_unq1[5:4]; +assign O[1] = coreir_commonlib_mux2x6_inst0_out_unq1[3:2]; +assign O[0] = coreir_commonlib_mux2x6_inst0_out_unq1[1:0]; +endmodule + module Main ( input [1:0] I [1:0][2:0], input [1:0] x, output [1:0] O [5:0][2:0] ); +wire [1:0] Mux2xArray3_Array2_Bit_inst0_O [2:0]; +wire [1:0] Mux2xArray3_Array2_Bit_inst1_O [2:0]; +wire [1:0] Mux2xArray3_Array2_Bit_inst2_O [2:0]; +wire [1:0] Mux2xArray3_Array2_Bit_inst3_O [2:0]; +wire [1:0] Mux2xArray3_Array2_Bit_inst4_O [2:0]; +wire [1:0] Mux2xArray3_Array2_Bit_inst5_O [2:0]; wire [1:0] Mux2xArray3_Array2_OutBit_inst0_O [2:0]; wire [1:0] Mux2xArray3_Array2_OutBit_inst1_O [2:0]; -wire [1:0] Mux2xArray3_Array2_OutBit_inst10_O [2:0]; -wire [1:0] Mux2xArray3_Array2_OutBit_inst11_O [2:0]; wire [1:0] Mux2xArray3_Array2_OutBit_inst2_O [2:0]; wire [1:0] Mux2xArray3_Array2_OutBit_inst3_O [2:0]; wire [1:0] Mux2xArray3_Array2_OutBit_inst4_O [2:0]; wire [1:0] Mux2xArray3_Array2_OutBit_inst5_O [2:0]; -wire [1:0] Mux2xArray3_Array2_OutBit_inst6_O [2:0]; -wire [1:0] Mux2xArray3_Array2_OutBit_inst7_O [2:0]; -wire [1:0] Mux2xArray3_Array2_OutBit_inst8_O [2:0]; -wire [1:0] Mux2xArray3_Array2_OutBit_inst9_O [2:0]; wire magma_Bit_and_inst0_out; wire magma_Bit_and_inst2_out; wire magma_Bit_and_inst4_out; @@ -47,18 +67,102 @@ wire [2:0] magma_Bits_3_sub_inst2_out; wire [2:0] magma_Bits_3_sub_inst4_out; wire [2:0] magma_Bits_3_sub_inst6_out; wire [2:0] magma_Bits_3_sub_inst8_out; +wire [1:0] Mux2xArray3_Array2_Bit_inst0_I0 [2:0]; +assign Mux2xArray3_Array2_Bit_inst0_I0[2] = I[0][2]; +assign Mux2xArray3_Array2_Bit_inst0_I0[1] = I[0][1]; +assign Mux2xArray3_Array2_Bit_inst0_I0[0] = I[0][0]; +wire [1:0] Mux2xArray3_Array2_Bit_inst0_I1 [2:0]; +assign Mux2xArray3_Array2_Bit_inst0_I1[2] = I[1][2]; +assign Mux2xArray3_Array2_Bit_inst0_I1[1] = I[1][1]; +assign Mux2xArray3_Array2_Bit_inst0_I1[0] = I[1][0]; +Mux2xArray3_Array2_Bit Mux2xArray3_Array2_Bit_inst0 ( + .I0(Mux2xArray3_Array2_Bit_inst0_I0), + .I1(Mux2xArray3_Array2_Bit_inst0_I1), + .S(magma_Bits_3_sub_inst0_out[0]), + .O(Mux2xArray3_Array2_Bit_inst0_O) +); +wire [1:0] Mux2xArray3_Array2_Bit_inst1_I0 [2:0]; +assign Mux2xArray3_Array2_Bit_inst1_I0[2] = I[0][2]; +assign Mux2xArray3_Array2_Bit_inst1_I0[1] = I[0][1]; +assign Mux2xArray3_Array2_Bit_inst1_I0[0] = I[0][0]; +wire [1:0] Mux2xArray3_Array2_Bit_inst1_I1 [2:0]; +assign Mux2xArray3_Array2_Bit_inst1_I1[2] = I[1][2]; +assign Mux2xArray3_Array2_Bit_inst1_I1[1] = I[1][1]; +assign Mux2xArray3_Array2_Bit_inst1_I1[0] = I[1][0]; +Mux2xArray3_Array2_Bit Mux2xArray3_Array2_Bit_inst1 ( + .I0(Mux2xArray3_Array2_Bit_inst1_I0), + .I1(Mux2xArray3_Array2_Bit_inst1_I1), + .S(magma_Bits_3_sub_inst2_out[0]), + .O(Mux2xArray3_Array2_Bit_inst1_O) +); +wire [1:0] Mux2xArray3_Array2_Bit_inst2_I0 [2:0]; +assign Mux2xArray3_Array2_Bit_inst2_I0[2] = I[0][2]; +assign Mux2xArray3_Array2_Bit_inst2_I0[1] = I[0][1]; +assign Mux2xArray3_Array2_Bit_inst2_I0[0] = I[0][0]; +wire [1:0] Mux2xArray3_Array2_Bit_inst2_I1 [2:0]; +assign Mux2xArray3_Array2_Bit_inst2_I1[2] = I[1][2]; +assign Mux2xArray3_Array2_Bit_inst2_I1[1] = I[1][1]; +assign Mux2xArray3_Array2_Bit_inst2_I1[0] = I[1][0]; +Mux2xArray3_Array2_Bit Mux2xArray3_Array2_Bit_inst2 ( + .I0(Mux2xArray3_Array2_Bit_inst2_I0), + .I1(Mux2xArray3_Array2_Bit_inst2_I1), + .S(magma_Bits_3_sub_inst4_out[0]), + .O(Mux2xArray3_Array2_Bit_inst2_O) +); +wire [1:0] Mux2xArray3_Array2_Bit_inst3_I0 [2:0]; +assign Mux2xArray3_Array2_Bit_inst3_I0[2] = I[0][2]; +assign Mux2xArray3_Array2_Bit_inst3_I0[1] = I[0][1]; +assign Mux2xArray3_Array2_Bit_inst3_I0[0] = I[0][0]; +wire [1:0] Mux2xArray3_Array2_Bit_inst3_I1 [2:0]; +assign Mux2xArray3_Array2_Bit_inst3_I1[2] = I[1][2]; +assign Mux2xArray3_Array2_Bit_inst3_I1[1] = I[1][1]; +assign Mux2xArray3_Array2_Bit_inst3_I1[0] = I[1][0]; +Mux2xArray3_Array2_Bit Mux2xArray3_Array2_Bit_inst3 ( + .I0(Mux2xArray3_Array2_Bit_inst3_I0), + .I1(Mux2xArray3_Array2_Bit_inst3_I1), + .S(magma_Bits_3_sub_inst6_out[0]), + .O(Mux2xArray3_Array2_Bit_inst3_O) +); +wire [1:0] Mux2xArray3_Array2_Bit_inst4_I0 [2:0]; +assign Mux2xArray3_Array2_Bit_inst4_I0[2] = I[0][2]; +assign Mux2xArray3_Array2_Bit_inst4_I0[1] = I[0][1]; +assign Mux2xArray3_Array2_Bit_inst4_I0[0] = I[0][0]; +wire [1:0] Mux2xArray3_Array2_Bit_inst4_I1 [2:0]; +assign Mux2xArray3_Array2_Bit_inst4_I1[2] = I[1][2]; +assign Mux2xArray3_Array2_Bit_inst4_I1[1] = I[1][1]; +assign Mux2xArray3_Array2_Bit_inst4_I1[0] = I[1][0]; +Mux2xArray3_Array2_Bit Mux2xArray3_Array2_Bit_inst4 ( + .I0(Mux2xArray3_Array2_Bit_inst4_I0), + .I1(Mux2xArray3_Array2_Bit_inst4_I1), + .S(magma_Bits_3_sub_inst8_out[0]), + .O(Mux2xArray3_Array2_Bit_inst4_O) +); +wire [1:0] Mux2xArray3_Array2_Bit_inst5_I0 [2:0]; +assign Mux2xArray3_Array2_Bit_inst5_I0[2] = I[0][2]; +assign Mux2xArray3_Array2_Bit_inst5_I0[1] = I[0][1]; +assign Mux2xArray3_Array2_Bit_inst5_I0[0] = I[0][0]; +wire [1:0] Mux2xArray3_Array2_Bit_inst5_I1 [2:0]; +assign Mux2xArray3_Array2_Bit_inst5_I1[2] = I[1][2]; +assign Mux2xArray3_Array2_Bit_inst5_I1[1] = I[1][1]; +assign Mux2xArray3_Array2_Bit_inst5_I1[0] = I[1][0]; +Mux2xArray3_Array2_Bit Mux2xArray3_Array2_Bit_inst5 ( + .I0(Mux2xArray3_Array2_Bit_inst5_I0), + .I1(Mux2xArray3_Array2_Bit_inst5_I1), + .S(magma_Bits_3_sub_inst10_out[0]), + .O(Mux2xArray3_Array2_Bit_inst5_O) +); wire [1:0] Mux2xArray3_Array2_OutBit_inst0_I0 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst0_I0[2] = I[0][2]; -assign Mux2xArray3_Array2_OutBit_inst0_I0[1] = I[0][1]; -assign Mux2xArray3_Array2_OutBit_inst0_I0[0] = I[0][0]; +assign Mux2xArray3_Array2_OutBit_inst0_I0[2] = {1'b0,1'b0}; +assign Mux2xArray3_Array2_OutBit_inst0_I0[1] = {1'b0,1'b0}; +assign Mux2xArray3_Array2_OutBit_inst0_I0[0] = {1'b0,1'b0}; wire [1:0] Mux2xArray3_Array2_OutBit_inst0_I1 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst0_I1[2] = I[1][2]; -assign Mux2xArray3_Array2_OutBit_inst0_I1[1] = I[1][1]; -assign Mux2xArray3_Array2_OutBit_inst0_I1[0] = I[1][0]; +assign Mux2xArray3_Array2_OutBit_inst0_I1[2] = Mux2xArray3_Array2_Bit_inst0_O[2]; +assign Mux2xArray3_Array2_OutBit_inst0_I1[1] = Mux2xArray3_Array2_Bit_inst0_O[1]; +assign Mux2xArray3_Array2_OutBit_inst0_I1[0] = Mux2xArray3_Array2_Bit_inst0_O[0]; Mux2xArray3_Array2_OutBit Mux2xArray3_Array2_OutBit_inst0 ( .I0(Mux2xArray3_Array2_OutBit_inst0_I0), .I1(Mux2xArray3_Array2_OutBit_inst0_I1), - .S(magma_Bits_3_sub_inst0_out[0]), + .S(magma_Bit_and_inst0_out), .O(Mux2xArray3_Array2_OutBit_inst0_O) ); wire [1:0] Mux2xArray3_Array2_OutBit_inst1_I0 [2:0]; @@ -66,55 +170,27 @@ assign Mux2xArray3_Array2_OutBit_inst1_I0[2] = {1'b0,1'b0}; assign Mux2xArray3_Array2_OutBit_inst1_I0[1] = {1'b0,1'b0}; assign Mux2xArray3_Array2_OutBit_inst1_I0[0] = {1'b0,1'b0}; wire [1:0] Mux2xArray3_Array2_OutBit_inst1_I1 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst1_I1[2] = Mux2xArray3_Array2_OutBit_inst0_O[2]; -assign Mux2xArray3_Array2_OutBit_inst1_I1[1] = Mux2xArray3_Array2_OutBit_inst0_O[1]; -assign Mux2xArray3_Array2_OutBit_inst1_I1[0] = Mux2xArray3_Array2_OutBit_inst0_O[0]; +assign Mux2xArray3_Array2_OutBit_inst1_I1[2] = Mux2xArray3_Array2_Bit_inst1_O[2]; +assign Mux2xArray3_Array2_OutBit_inst1_I1[1] = Mux2xArray3_Array2_Bit_inst1_O[1]; +assign Mux2xArray3_Array2_OutBit_inst1_I1[0] = Mux2xArray3_Array2_Bit_inst1_O[0]; Mux2xArray3_Array2_OutBit Mux2xArray3_Array2_OutBit_inst1 ( .I0(Mux2xArray3_Array2_OutBit_inst1_I0), .I1(Mux2xArray3_Array2_OutBit_inst1_I1), - .S(magma_Bit_and_inst0_out), + .S(magma_Bit_and_inst2_out), .O(Mux2xArray3_Array2_OutBit_inst1_O) ); -wire [1:0] Mux2xArray3_Array2_OutBit_inst10_I0 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst10_I0[2] = I[0][2]; -assign Mux2xArray3_Array2_OutBit_inst10_I0[1] = I[0][1]; -assign Mux2xArray3_Array2_OutBit_inst10_I0[0] = I[0][0]; -wire [1:0] Mux2xArray3_Array2_OutBit_inst10_I1 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst10_I1[2] = I[1][2]; -assign Mux2xArray3_Array2_OutBit_inst10_I1[1] = I[1][1]; -assign Mux2xArray3_Array2_OutBit_inst10_I1[0] = I[1][0]; -Mux2xArray3_Array2_OutBit Mux2xArray3_Array2_OutBit_inst10 ( - .I0(Mux2xArray3_Array2_OutBit_inst10_I0), - .I1(Mux2xArray3_Array2_OutBit_inst10_I1), - .S(magma_Bits_3_sub_inst10_out[0]), - .O(Mux2xArray3_Array2_OutBit_inst10_O) -); -wire [1:0] Mux2xArray3_Array2_OutBit_inst11_I0 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst11_I0[2] = {1'b0,1'b0}; -assign Mux2xArray3_Array2_OutBit_inst11_I0[1] = {1'b0,1'b0}; -assign Mux2xArray3_Array2_OutBit_inst11_I0[0] = {1'b0,1'b0}; -wire [1:0] Mux2xArray3_Array2_OutBit_inst11_I1 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst11_I1[2] = Mux2xArray3_Array2_OutBit_inst10_O[2]; -assign Mux2xArray3_Array2_OutBit_inst11_I1[1] = Mux2xArray3_Array2_OutBit_inst10_O[1]; -assign Mux2xArray3_Array2_OutBit_inst11_I1[0] = Mux2xArray3_Array2_OutBit_inst10_O[0]; -Mux2xArray3_Array2_OutBit Mux2xArray3_Array2_OutBit_inst11 ( - .I0(Mux2xArray3_Array2_OutBit_inst11_I0), - .I1(Mux2xArray3_Array2_OutBit_inst11_I1), - .S(magma_Bit_and_inst7_out), - .O(Mux2xArray3_Array2_OutBit_inst11_O) -); wire [1:0] Mux2xArray3_Array2_OutBit_inst2_I0 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst2_I0[2] = I[0][2]; -assign Mux2xArray3_Array2_OutBit_inst2_I0[1] = I[0][1]; -assign Mux2xArray3_Array2_OutBit_inst2_I0[0] = I[0][0]; +assign Mux2xArray3_Array2_OutBit_inst2_I0[2] = {1'b0,1'b0}; +assign Mux2xArray3_Array2_OutBit_inst2_I0[1] = {1'b0,1'b0}; +assign Mux2xArray3_Array2_OutBit_inst2_I0[0] = {1'b0,1'b0}; wire [1:0] Mux2xArray3_Array2_OutBit_inst2_I1 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst2_I1[2] = I[1][2]; -assign Mux2xArray3_Array2_OutBit_inst2_I1[1] = I[1][1]; -assign Mux2xArray3_Array2_OutBit_inst2_I1[0] = I[1][0]; +assign Mux2xArray3_Array2_OutBit_inst2_I1[2] = Mux2xArray3_Array2_Bit_inst2_O[2]; +assign Mux2xArray3_Array2_OutBit_inst2_I1[1] = Mux2xArray3_Array2_Bit_inst2_O[1]; +assign Mux2xArray3_Array2_OutBit_inst2_I1[0] = Mux2xArray3_Array2_Bit_inst2_O[0]; Mux2xArray3_Array2_OutBit Mux2xArray3_Array2_OutBit_inst2 ( .I0(Mux2xArray3_Array2_OutBit_inst2_I0), .I1(Mux2xArray3_Array2_OutBit_inst2_I1), - .S(magma_Bits_3_sub_inst2_out[0]), + .S(magma_Bit_and_inst4_out), .O(Mux2xArray3_Array2_OutBit_inst2_O) ); wire [1:0] Mux2xArray3_Array2_OutBit_inst3_I0 [2:0]; @@ -122,27 +198,27 @@ assign Mux2xArray3_Array2_OutBit_inst3_I0[2] = {1'b0,1'b0}; assign Mux2xArray3_Array2_OutBit_inst3_I0[1] = {1'b0,1'b0}; assign Mux2xArray3_Array2_OutBit_inst3_I0[0] = {1'b0,1'b0}; wire [1:0] Mux2xArray3_Array2_OutBit_inst3_I1 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst3_I1[2] = Mux2xArray3_Array2_OutBit_inst2_O[2]; -assign Mux2xArray3_Array2_OutBit_inst3_I1[1] = Mux2xArray3_Array2_OutBit_inst2_O[1]; -assign Mux2xArray3_Array2_OutBit_inst3_I1[0] = Mux2xArray3_Array2_OutBit_inst2_O[0]; +assign Mux2xArray3_Array2_OutBit_inst3_I1[2] = Mux2xArray3_Array2_Bit_inst3_O[2]; +assign Mux2xArray3_Array2_OutBit_inst3_I1[1] = Mux2xArray3_Array2_Bit_inst3_O[1]; +assign Mux2xArray3_Array2_OutBit_inst3_I1[0] = Mux2xArray3_Array2_Bit_inst3_O[0]; Mux2xArray3_Array2_OutBit Mux2xArray3_Array2_OutBit_inst3 ( .I0(Mux2xArray3_Array2_OutBit_inst3_I0), .I1(Mux2xArray3_Array2_OutBit_inst3_I1), - .S(magma_Bit_and_inst2_out), + .S(magma_Bit_and_inst5_out), .O(Mux2xArray3_Array2_OutBit_inst3_O) ); wire [1:0] Mux2xArray3_Array2_OutBit_inst4_I0 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst4_I0[2] = I[0][2]; -assign Mux2xArray3_Array2_OutBit_inst4_I0[1] = I[0][1]; -assign Mux2xArray3_Array2_OutBit_inst4_I0[0] = I[0][0]; +assign Mux2xArray3_Array2_OutBit_inst4_I0[2] = {1'b0,1'b0}; +assign Mux2xArray3_Array2_OutBit_inst4_I0[1] = {1'b0,1'b0}; +assign Mux2xArray3_Array2_OutBit_inst4_I0[0] = {1'b0,1'b0}; wire [1:0] Mux2xArray3_Array2_OutBit_inst4_I1 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst4_I1[2] = I[1][2]; -assign Mux2xArray3_Array2_OutBit_inst4_I1[1] = I[1][1]; -assign Mux2xArray3_Array2_OutBit_inst4_I1[0] = I[1][0]; +assign Mux2xArray3_Array2_OutBit_inst4_I1[2] = Mux2xArray3_Array2_Bit_inst4_O[2]; +assign Mux2xArray3_Array2_OutBit_inst4_I1[1] = Mux2xArray3_Array2_Bit_inst4_O[1]; +assign Mux2xArray3_Array2_OutBit_inst4_I1[0] = Mux2xArray3_Array2_Bit_inst4_O[0]; Mux2xArray3_Array2_OutBit Mux2xArray3_Array2_OutBit_inst4 ( .I0(Mux2xArray3_Array2_OutBit_inst4_I0), .I1(Mux2xArray3_Array2_OutBit_inst4_I1), - .S(magma_Bits_3_sub_inst4_out[0]), + .S(magma_Bit_and_inst6_out), .O(Mux2xArray3_Array2_OutBit_inst4_O) ); wire [1:0] Mux2xArray3_Array2_OutBit_inst5_I0 [2:0]; @@ -150,71 +226,15 @@ assign Mux2xArray3_Array2_OutBit_inst5_I0[2] = {1'b0,1'b0}; assign Mux2xArray3_Array2_OutBit_inst5_I0[1] = {1'b0,1'b0}; assign Mux2xArray3_Array2_OutBit_inst5_I0[0] = {1'b0,1'b0}; wire [1:0] Mux2xArray3_Array2_OutBit_inst5_I1 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst5_I1[2] = Mux2xArray3_Array2_OutBit_inst4_O[2]; -assign Mux2xArray3_Array2_OutBit_inst5_I1[1] = Mux2xArray3_Array2_OutBit_inst4_O[1]; -assign Mux2xArray3_Array2_OutBit_inst5_I1[0] = Mux2xArray3_Array2_OutBit_inst4_O[0]; +assign Mux2xArray3_Array2_OutBit_inst5_I1[2] = Mux2xArray3_Array2_Bit_inst5_O[2]; +assign Mux2xArray3_Array2_OutBit_inst5_I1[1] = Mux2xArray3_Array2_Bit_inst5_O[1]; +assign Mux2xArray3_Array2_OutBit_inst5_I1[0] = Mux2xArray3_Array2_Bit_inst5_O[0]; Mux2xArray3_Array2_OutBit Mux2xArray3_Array2_OutBit_inst5 ( .I0(Mux2xArray3_Array2_OutBit_inst5_I0), .I1(Mux2xArray3_Array2_OutBit_inst5_I1), - .S(magma_Bit_and_inst4_out), + .S(magma_Bit_and_inst7_out), .O(Mux2xArray3_Array2_OutBit_inst5_O) ); -wire [1:0] Mux2xArray3_Array2_OutBit_inst6_I0 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst6_I0[2] = I[0][2]; -assign Mux2xArray3_Array2_OutBit_inst6_I0[1] = I[0][1]; -assign Mux2xArray3_Array2_OutBit_inst6_I0[0] = I[0][0]; -wire [1:0] Mux2xArray3_Array2_OutBit_inst6_I1 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst6_I1[2] = I[1][2]; -assign Mux2xArray3_Array2_OutBit_inst6_I1[1] = I[1][1]; -assign Mux2xArray3_Array2_OutBit_inst6_I1[0] = I[1][0]; -Mux2xArray3_Array2_OutBit Mux2xArray3_Array2_OutBit_inst6 ( - .I0(Mux2xArray3_Array2_OutBit_inst6_I0), - .I1(Mux2xArray3_Array2_OutBit_inst6_I1), - .S(magma_Bits_3_sub_inst6_out[0]), - .O(Mux2xArray3_Array2_OutBit_inst6_O) -); -wire [1:0] Mux2xArray3_Array2_OutBit_inst7_I0 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst7_I0[2] = {1'b0,1'b0}; -assign Mux2xArray3_Array2_OutBit_inst7_I0[1] = {1'b0,1'b0}; -assign Mux2xArray3_Array2_OutBit_inst7_I0[0] = {1'b0,1'b0}; -wire [1:0] Mux2xArray3_Array2_OutBit_inst7_I1 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst7_I1[2] = Mux2xArray3_Array2_OutBit_inst6_O[2]; -assign Mux2xArray3_Array2_OutBit_inst7_I1[1] = Mux2xArray3_Array2_OutBit_inst6_O[1]; -assign Mux2xArray3_Array2_OutBit_inst7_I1[0] = Mux2xArray3_Array2_OutBit_inst6_O[0]; -Mux2xArray3_Array2_OutBit Mux2xArray3_Array2_OutBit_inst7 ( - .I0(Mux2xArray3_Array2_OutBit_inst7_I0), - .I1(Mux2xArray3_Array2_OutBit_inst7_I1), - .S(magma_Bit_and_inst5_out), - .O(Mux2xArray3_Array2_OutBit_inst7_O) -); -wire [1:0] Mux2xArray3_Array2_OutBit_inst8_I0 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst8_I0[2] = I[0][2]; -assign Mux2xArray3_Array2_OutBit_inst8_I0[1] = I[0][1]; -assign Mux2xArray3_Array2_OutBit_inst8_I0[0] = I[0][0]; -wire [1:0] Mux2xArray3_Array2_OutBit_inst8_I1 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst8_I1[2] = I[1][2]; -assign Mux2xArray3_Array2_OutBit_inst8_I1[1] = I[1][1]; -assign Mux2xArray3_Array2_OutBit_inst8_I1[0] = I[1][0]; -Mux2xArray3_Array2_OutBit Mux2xArray3_Array2_OutBit_inst8 ( - .I0(Mux2xArray3_Array2_OutBit_inst8_I0), - .I1(Mux2xArray3_Array2_OutBit_inst8_I1), - .S(magma_Bits_3_sub_inst8_out[0]), - .O(Mux2xArray3_Array2_OutBit_inst8_O) -); -wire [1:0] Mux2xArray3_Array2_OutBit_inst9_I0 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst9_I0[2] = {1'b0,1'b0}; -assign Mux2xArray3_Array2_OutBit_inst9_I0[1] = {1'b0,1'b0}; -assign Mux2xArray3_Array2_OutBit_inst9_I0[0] = {1'b0,1'b0}; -wire [1:0] Mux2xArray3_Array2_OutBit_inst9_I1 [2:0]; -assign Mux2xArray3_Array2_OutBit_inst9_I1[2] = Mux2xArray3_Array2_OutBit_inst8_O[2]; -assign Mux2xArray3_Array2_OutBit_inst9_I1[1] = Mux2xArray3_Array2_OutBit_inst8_O[1]; -assign Mux2xArray3_Array2_OutBit_inst9_I1[0] = Mux2xArray3_Array2_OutBit_inst8_O[0]; -Mux2xArray3_Array2_OutBit Mux2xArray3_Array2_OutBit_inst9 ( - .I0(Mux2xArray3_Array2_OutBit_inst9_I0), - .I1(Mux2xArray3_Array2_OutBit_inst9_I1), - .S(magma_Bit_and_inst6_out), - .O(Mux2xArray3_Array2_OutBit_inst9_O) -); assign magma_Bit_and_inst0_out = 1'b1 & (({1'b0,x[1:0]}) <= 3'h0); assign magma_Bit_and_inst2_out = (1'b1 & (({1'b0,x[1:0]}) <= 3'h1)) & ((3'((3'(({1'b0,x[1:0]}) + 3'h2)) - 3'h1)) >= 3'h1); assign magma_Bit_and_inst4_out = (1'b1 & (({1'b0,x[1:0]}) <= 3'h2)) & ((3'((3'(({1'b0,x[1:0]}) + 3'h2)) - 3'h1)) >= 3'h2); @@ -227,23 +247,23 @@ assign magma_Bits_3_sub_inst2_out = 3'(3'h1 - ({1'b0,x[1:0]})); assign magma_Bits_3_sub_inst4_out = 3'(3'h2 - ({1'b0,x[1:0]})); assign magma_Bits_3_sub_inst6_out = 3'(3'h3 - ({1'b0,x[1:0]})); assign magma_Bits_3_sub_inst8_out = 3'(3'h4 - ({1'b0,x[1:0]})); -assign O[5][2] = Mux2xArray3_Array2_OutBit_inst11_O[2]; -assign O[5][1] = Mux2xArray3_Array2_OutBit_inst11_O[1]; -assign O[5][0] = Mux2xArray3_Array2_OutBit_inst11_O[0]; -assign O[4][2] = Mux2xArray3_Array2_OutBit_inst9_O[2]; -assign O[4][1] = Mux2xArray3_Array2_OutBit_inst9_O[1]; -assign O[4][0] = Mux2xArray3_Array2_OutBit_inst9_O[0]; -assign O[3][2] = Mux2xArray3_Array2_OutBit_inst7_O[2]; -assign O[3][1] = Mux2xArray3_Array2_OutBit_inst7_O[1]; -assign O[3][0] = Mux2xArray3_Array2_OutBit_inst7_O[0]; -assign O[2][2] = Mux2xArray3_Array2_OutBit_inst5_O[2]; -assign O[2][1] = Mux2xArray3_Array2_OutBit_inst5_O[1]; -assign O[2][0] = Mux2xArray3_Array2_OutBit_inst5_O[0]; -assign O[1][2] = Mux2xArray3_Array2_OutBit_inst3_O[2]; -assign O[1][1] = Mux2xArray3_Array2_OutBit_inst3_O[1]; -assign O[1][0] = Mux2xArray3_Array2_OutBit_inst3_O[0]; -assign O[0][2] = Mux2xArray3_Array2_OutBit_inst1_O[2]; -assign O[0][1] = Mux2xArray3_Array2_OutBit_inst1_O[1]; -assign O[0][0] = Mux2xArray3_Array2_OutBit_inst1_O[0]; +assign O[5][2] = Mux2xArray3_Array2_OutBit_inst5_O[2]; +assign O[5][1] = Mux2xArray3_Array2_OutBit_inst5_O[1]; +assign O[5][0] = Mux2xArray3_Array2_OutBit_inst5_O[0]; +assign O[4][2] = Mux2xArray3_Array2_OutBit_inst4_O[2]; +assign O[4][1] = Mux2xArray3_Array2_OutBit_inst4_O[1]; +assign O[4][0] = Mux2xArray3_Array2_OutBit_inst4_O[0]; +assign O[3][2] = Mux2xArray3_Array2_OutBit_inst3_O[2]; +assign O[3][1] = Mux2xArray3_Array2_OutBit_inst3_O[1]; +assign O[3][0] = Mux2xArray3_Array2_OutBit_inst3_O[0]; +assign O[2][2] = Mux2xArray3_Array2_OutBit_inst2_O[2]; +assign O[2][1] = Mux2xArray3_Array2_OutBit_inst2_O[1]; +assign O[2][0] = Mux2xArray3_Array2_OutBit_inst2_O[0]; +assign O[1][2] = Mux2xArray3_Array2_OutBit_inst1_O[2]; +assign O[1][1] = Mux2xArray3_Array2_OutBit_inst1_O[1]; +assign O[1][0] = Mux2xArray3_Array2_OutBit_inst1_O[0]; +assign O[0][2] = Mux2xArray3_Array2_OutBit_inst0_O[2]; +assign O[0][1] = Mux2xArray3_Array2_OutBit_inst0_O[1]; +assign O[0][0] = Mux2xArray3_Array2_OutBit_inst0_O[0]; endmodule diff --git a/tests/test_verilog/gold/test_inline_simple.json b/tests/test_verilog/gold/test_inline_simple.json deleted file mode 100644 index 66f89abe3..000000000 --- a/tests/test_verilog/gold/test_inline_simple.json +++ /dev/null @@ -1,86 +0,0 @@ -{"top":"global.Main", -"namespaces":{ - "global":{ - "modules":{ - "FF":{ - "type":["Record",[ - ["I","BitIn"], - ["O","Bit"], - ["CLK",["Named","coreir.clkIn"]] - ]], - "metadata":{"verilog":{"verilog_string":"module FF(input I, output reg O, input CLK);\nalways @(posedge CLK) begin\n O <= I;\nend\nendmodule"}} - }, - "Main":{ - "type":["Record",[ - ["I","BitIn"], - ["O","Bit"], - ["arr",["Array",2,"BitIn"]], - ["CLK",["Named","coreir.clkIn"]] - ]], - "instances":{ - "FF_inst0":{ - "modref":"global.FF" - }, - "Main_inline_verilog_inst_0":{ - "modref":"global.Main_inline_verilog_0" - }, - "Main_inline_verilog_inst_1":{ - "modref":"global.Main_inline_verilog_1" - }, - "_magma_inline_wire0":{ - "modref":"corebit.wire" - } - }, - "connections":[ - ["self.CLK","FF_inst0.CLK"], - ["self.I","FF_inst0.I"], - ["_magma_inline_wire0.in","FF_inst0.O"], - ["self.O","FF_inst0.O"], - ["_magma_inline_wire0.out","Main_inline_verilog_inst_0.__magma_inline_value_0"], - ["self.I","Main_inline_verilog_inst_0.__magma_inline_value_1"], - ["self.arr.0","Main_inline_verilog_inst_1.__magma_inline_value_0"], - ["self.arr.1","Main_inline_verilog_inst_1.__magma_inline_value_1"] - ] - }, - "Main_inline_verilog_0":{ - "type":["Record",[ - ["__magma_inline_value_0","BitIn"], - ["__magma_inline_value_1","BitIn"] - ]], - "instances":{ - "corebit_term_inst0":{ - "modref":"corebit.term" - }, - "corebit_term_inst1":{ - "modref":"corebit.term" - } - }, - "connections":[ - ["self.__magma_inline_value_0","corebit_term_inst0.in"], - ["self.__magma_inline_value_1","corebit_term_inst1.in"] - ], - "metadata":{"inline_verilog":{"connect_references":{"__magma_inline_value_0":"self.__magma_inline_value_0","__magma_inline_value_1":"self.__magma_inline_value_1"},"str":"\nassert property (@(posedge CLK) {__magma_inline_value_1} |-> ##1 {__magma_inline_value_0});\n"}} - }, - "Main_inline_verilog_1":{ - "type":["Record",[ - ["__magma_inline_value_0","BitIn"], - ["__magma_inline_value_1","BitIn"] - ]], - "instances":{ - "corebit_term_inst0":{ - "modref":"corebit.term" - }, - "corebit_term_inst1":{ - "modref":"corebit.term" - } - }, - "connections":[ - ["self.__magma_inline_value_0","corebit_term_inst0.in"], - ["self.__magma_inline_value_1","corebit_term_inst1.in"] - ], - "metadata":{"inline_verilog":{"connect_references":{"__magma_inline_value_0":"self.__magma_inline_value_0","__magma_inline_value_1":"self.__magma_inline_value_1"},"str":"\nassert property (@(posedge CLK) {__magma_inline_value_0} |-> ##1 {__magma_inline_value_1});\n"}} - } - } - } -} -}