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* .vcd
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* .d
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build /
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+ /docs /_site
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+ /docs /.sass-cache
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- theme : jekyll-theme-slate
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+ theme : jekyll-theme-slate
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+ title : FPGA tutorial
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+ defaults :
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+ - scope :
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+ path : " " # an empty string here means all files in the project
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+ values :
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+ layout : " default"
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+ ---
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+ title : FPGA
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+ ---
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# FPGA
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We'll be working in the ` verilog ` directory.
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# FPGA tutorial
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Here are some materials for my FPGA workshop. The workshop uses the open source
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+ title : Verilog basics
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# Verilog basics
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We'll be working in the ` verilog ` directory.
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