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1 parent e4e8714 commit b7603d3Copy full SHA for b7603d3
verilog/oled.v
@@ -123,6 +123,7 @@ module oled_controller(input wire clk,
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reg [7:0] data_rgb_lower_byte;
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reg [3:0] state = STATE_RESET;
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+ reg [9:0] reset_counter = 0;
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integer i;
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@@ -227,11 +228,14 @@ module oled_controller(input wire clk,
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pin_res <= 1;
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case (state)
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STATE_RESET: begin
- if (spi_ready) begin
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- pin_res <= 0;
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- state <= STATE_INIT;
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- command_idx <= 0;
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- end
+ pin_res <= 0;
+ reset_counter <= reset_counter + 1;
+ if (&reset_counter)
+ if (spi_ready) begin
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+ state <= STATE_INIT;
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+ command_idx <= 0;
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+ end
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end
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STATE_INIT: begin
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if (spi_ready) begin
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