Skip to content

Commit f0af9d7

Browse files
committed
Reword
1 parent d70b713 commit f0af9d7

File tree

1 file changed

+1
-1
lines changed

1 file changed

+1
-1
lines changed

verilog/README.md

+1-1
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ Now, use half-adders to construct an adder. An adder adds two bits and a carry-i
5151
1 1 0 0 1
5252
1 1 1 1 1
5353

54-
Finally, use the adders to add a 4-bit number:
54+
Finally, use the adders to construct a 4-bit adder:
5555

5656
x y s c
5757

0 commit comments

Comments
 (0)