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pwmarczpwmarcz
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Add demo for OLED displays
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‎fpga/README.md

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# FPGA
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TODO:
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oled
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## Setup
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You will need Verilog setup from the [previous step](../verilog/README.md).
@@ -151,15 +147,13 @@ developed by Tim Goddard](https://github.com/cyrozap/osdvu).
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I have two OLED screens:
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- "Two-color" (actually monochrome) 128x64 screen. The data is laid out in 8
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"pages" of 128 bytes each. Each page describes a 128x8 strip, each byte is a
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1x8 segment.
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rows of 128 bytes each. Each row describes a 128x8 strip, each byte is a 1x8
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segment.
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- 65536-color 96x64 screen. Each pixel is 16 bits. Note that this is more
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memory that Icestick has on board (12 KB; the Icestick's block RAMs hold 8 KB
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total).
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(TODO get the color display running)
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See `oled_mono.v` and `oled_color.v` for details on how to use.
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See `oled_pattern.v` and `oled_pattern_color.v` for details on how to use.
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You might want to load some initial data into memory. You can use the
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[`$readmemh`

‎fpga/oled.v

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`include "ssd1306.v"
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`include "ssd1331.v"
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module oled(input wire clk,
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input wire pin_din,
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input wire pin_clk,
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input wire pin_cs,
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input wire pin_dc,
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input wire pin_res,
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output wire read,
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output wire [5:0] row_idx,
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output wire [6:0] column_idx,
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// mono: 8-pixel vertical strip
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input wire [7:0] data,
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// color: 5+6+5 bit RGB value
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input wire [15:0] data_rgb,
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input wire ack);
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parameter color = 0;
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wire transmit;
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wire is_data;
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wire [7:0] tx_byte;
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wire ready;
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oled_spi spi(.clk(clk),
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.transmit(transmit),
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.is_data(is_data),
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.tx_byte(tx_byte),
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.ready(ready),
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.pin_din(pin_din),
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.pin_clk(pin_clk),
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.pin_cs(pin_cs),
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.pin_dc(pin_dc));
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oled_controller #(.color(color))
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controller(.clk(clk),
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.pin_res(pin_res),
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.spi_transmit(transmit),
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.spi_is_data(is_data),
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.spi_tx_byte(tx_byte),
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.spi_ready(ready),
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.read(read),
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.row_idx(row_idx),
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.column_idx(column_idx),
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.data(data),
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.data_rgb(data_rgb),
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.ack(ack));
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endmodule
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module oled_spi(input wire clk,
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input wire transmit,
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input wire is_data,
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input wire [7:0] tx_byte,
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output wire ready,
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output wire pin_din,
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output wire pin_clk,
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output wire pin_cs,
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output reg pin_dc);
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assign pin_clk = clk;
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reg [7:0] data;
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reg [3:0] data_counter = 0;
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wire transmitting = data_counter > 0;
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assign pin_din = data[7];
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assign pin_cs = !transmitting;
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assign ready = !transmit && !transmitting;
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always @(posedge clk) begin
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if (transmit && !transmitting) begin
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data <= tx_byte;
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pin_dc <= is_data;
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data_counter <= 8;
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end
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if (transmitting) begin
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data <= data << 1;
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data_counter <= data_counter - 1;
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end
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end
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endmodule
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module oled_controller(input wire clk,
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output reg pin_res,
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output reg spi_transmit,
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output reg spi_is_data,
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output reg [7:0] spi_tx_byte,
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input wire spi_ready,
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output reg read,
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output reg [5:0] row_idx,
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output reg [6:0] column_idx,
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input wire [7:0] data,
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input wire [15:0] data_rgb,
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input wire ack);
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parameter color = 0;
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localparam N_INIT_COMMANDS = color ? 38 : 25;
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localparam N_REFRESH_COMMANDS = 6;
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localparam WIDTH = color ? 96 : 128;
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localparam HEIGHT = color ? 64 : 8;
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localparam
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STATE_RESET = 0,
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STATE_INIT = 1,
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STATE_IDLE = 2,
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STATE_REFRESH_BEGIN = 3,
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STATE_REFRESH_DATA = 4,
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STATE_TRANSMIT_LOWER_BYTE = 5,
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STATE_ADVANCE = 6;
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reg [7:0] commands[0:N_INIT_COMMANDS+N_REFRESH_COMMANDS-1];
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reg [8:0] command_idx = 0;
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reg [7:0] command;
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reg send_command = 0;
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reg [7:0] data_rgb_lower_byte;
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reg [3:0] state = STATE_RESET;
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integer i;
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initial begin
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i = -1;
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if (color) begin
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// Init commands
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i++; commands[i] <= `SSD1331_DISPLAY_OFF;
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i++; commands[i] <= `SSD1331_SET_CONTRAST_A;
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i++; commands[i] <= 'hFF;
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i++; commands[i] <= `SSD1331_SET_CONTRAST_B;
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i++; commands[i] <= 'hFF;
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i++; commands[i] <= `SSD1331_SET_CONTRAST_C;
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i++; commands[i] <= 'hFF;
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i++; commands[i] <= `SSD1331_MASTER_CURRENT_CONTROL;
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i++; commands[i] <= 'h06;
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i++; commands[i] <= `SSD1331_SET_PRECHARGE_SPEED_A;
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i++; commands[i] <= 'h64;
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i++; commands[i] <= `SSD1331_SET_PRECHARGE_SPEED_B;
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i++; commands[i] <= 'h78;
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i++; commands[i] <= `SSD1331_SET_PRECHARGE_SPEED_C;
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i++; commands[i] <= 'h64;
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i++; commands[i] <= `SSD1331_SET_REMAP;
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i++; commands[i] <= 'h72;
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i++; commands[i] <= `SSD1331_SET_DISPLAY_START_LINE;
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i++; commands[i] <= 'h00;
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i++; commands[i] <= `SSD1331_SET_DISPLAY_OFFSET;
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i++; commands[i] <= 'h00;
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i++; commands[i] <= `SSD1331_NORMAL_DISPLAY;
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i++; commands[i] <= `SSD1331_SET_MULTIPLEX_RATIO;
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i++; commands[i] <= 'h3F;
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i++; commands[i] <= `SSD1331_SET_MASTER_CONFIGURE;
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i++; commands[i] <= 'h8E;
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i++; commands[i] <= `SSD1331_POWER_SAVE_MODE;
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i++; commands[i] <= 'h00;
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i++; commands[i] <= `SSD1331_PHASE_PERIOD_ADJUSTMENT;
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i++; commands[i] <= 'h31;
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i++; commands[i] <= `SSD1331_DISPLAY_CLOCK_DIV;
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i++; commands[i] <= 'hF0;
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i++; commands[i] <= `SSD1331_SET_PRECHARGE_VOLTAGE;
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i++; commands[i] <= 'h3A;
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i++; commands[i] <= `SSD1331_SET_V_VOLTAGE;
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i++; commands[i] <= 'h3E;
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i++; commands[i] <= `SSD1331_DEACTIVE_SCROLLING;
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i++; commands[i] <= `SSD1331_NORMAL_BRIGHTNESS_DISPLAY_ON;
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// Refresh commands
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i++; commands[i] <= `SSD1331_SET_COLUMN_ADDRESS;
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i++; commands[i] <= 0;
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i++; commands[i] <= WIDTH - 1;
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i++; commands[i] <= `SSD1331_SET_ROW_ADDRESS;
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i++; commands[i] <= 0;
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i++; commands[i] <= HEIGHT - 1;
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end else begin
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// Init commands
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i++; commands[i] <= `SSD1306_DISPLAYOFF;
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i++; commands[i] <= `SSD1306_SETDISPLAYCLOCKDIV;
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i++; commands[i] <= 'h80;
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i++; commands[i] <= `SSD1306_SETMULTIPLEX;
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i++; commands[i] <= 'h3F;
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i++; commands[i] <= `SSD1306_SETDISPLAYOFFSET;
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i++; commands[i] <= 'h00;
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i++; commands[i] <= `SSD1306_SETSTARTLINE | 'h00;
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i++; commands[i] <= `SSD1306_CHARGEPUMP;
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i++; commands[i] <= 'h14;
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i++; commands[i] <= `SSD1306_MEMORYMODE;
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i++; commands[i] <= 'h00;
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i++; commands[i] <= `SSD1306_SEGREMAP | 'h01;
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i++; commands[i] <= `SSD1306_COMSCANDEC;
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i++; commands[i] <= `SSD1306_SETCOMPINS;
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i++; commands[i] <= 'h12;
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i++; commands[i] <= `SSD1306_SETCONTRAST;
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i++; commands[i] <= 'h70;
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i++; commands[i] <= `SSD1306_SETPRECHARGE;
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i++; commands[i] <= 'hF1;
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i++; commands[i] <= `SSD1306_SETVCOMDETECT;
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i++; commands[i] <= 'h40;
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i++; commands[i] <= `SSD1306_DISPLAYALLON_RESUME;
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i++; commands[i] <= `SSD1306_NORMALDISPLAY;
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i++; commands[i] <= `SSD1306_DISPLAYON;
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// Refresh commands
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i++; commands[i] <= `SSD1306_COLUMNADDR;
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i++; commands[i] <= 0;
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i++; commands[i] <= WIDTH - 1;
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i++; commands[i] <= `SSD1306_PAGEADDR;
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i++; commands[i] <= 0;
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i++; commands[i] <= HEIGHT - 1;
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end
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end
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always @(posedge clk) begin
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command <= commands[command_idx];
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if (send_command) begin
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send_command <= 0;
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spi_transmit <= 1;
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spi_is_data <= 0;
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spi_tx_byte <= command;
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end else begin
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spi_transmit <= 0;
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pin_res <= 1;
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case (state)
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STATE_RESET: begin
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if (spi_ready) begin
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pin_res <= 0;
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state <= STATE_INIT;
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command_idx <= 0;
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end
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end
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STATE_INIT: begin
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if (spi_ready) begin
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send_command <= 1;
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command_idx <= command_idx + 1;
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if (command_idx+1 == N_INIT_COMMANDS) begin
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state <= STATE_REFRESH_BEGIN;
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end
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end
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end
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STATE_REFRESH_BEGIN: begin
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if (spi_ready) begin
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if (command_idx < N_INIT_COMMANDS + N_REFRESH_COMMANDS) begin
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send_command <= 1;
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command_idx <= command_idx + 1;
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end else begin
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state <= STATE_REFRESH_DATA;
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row_idx <= 0;
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column_idx <= 0;
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read <= 1;
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end
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end
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end
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STATE_REFRESH_DATA: begin
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read <= 0;
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if (ack) begin
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spi_transmit <= 1;
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spi_is_data <= 1;
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if (color) begin
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spi_tx_byte <= data_rgb[15:8];
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data_rgb_lower_byte <= data_rgb[7:0];
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state <= STATE_TRANSMIT_LOWER_BYTE;
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end else begin
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spi_tx_byte <= data;
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state <= STATE_ADVANCE;
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end
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end
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end
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STATE_TRANSMIT_LOWER_BYTE: begin
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if (color) begin
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if (spi_ready) begin
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spi_transmit <= 1;
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spi_is_data <= 1;
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spi_tx_byte <= data_rgb_lower_byte;
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state <= STATE_ADVANCE;
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end
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end
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end
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STATE_ADVANCE: begin
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if (spi_ready) begin
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if (column_idx == WIDTH - 1 && row_idx == HEIGHT - 1) begin
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state <= STATE_REFRESH_BEGIN;
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command_idx <= N_INIT_COMMANDS;
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end else begin
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read <= 1;
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state <= STATE_REFRESH_DATA;
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column_idx <= column_idx + 1;
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if (column_idx == WIDTH - 1) begin
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column_idx <= 0;
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if (color)
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row_idx <= row_idx + 1;
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else
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row_idx <= row_idx + 1;
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end
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end
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end
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end
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endcase
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end
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end
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endmodule

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