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Ashkan Aliabadi
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Upstream the cpuinfo updates in XNNPACK/third_party/cpuinfo.patch. Author: The XNNPACK Team.
1 parent 9778505 commit 0e6bde9

22 files changed

+1419
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lines changed

‎CMakeLists.txt

+2-1
Original file line numberDiff line numberDiff line change
@@ -121,7 +121,8 @@ ENDIF()
121121
# ---[ cpuinfo library
122122
SET(CPUINFO_SRCS
123123
src/init.c
124-
src/api.c)
124+
src/api.c
125+
src/cache.c)
125126

126127
IF(CPUINFO_SUPPORTED_PLATFORM)
127128
IF(CMAKE_SYSTEM_PROCESSOR MATCHES "^(i[3-6]86|AMD64|x86(_64)?)$" OR IOS_ARCH MATCHES "^(i386|x86_64)$")

‎CMakeLists.txt.orig

+819
Large diffs are not rendered by default.

‎LICENSE

+1
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
Copyright (c) 2019 Google LLC
12
Copyright (c) 2017-2018 Facebook Inc.
23
Copyright (C) 2012-2017 Georgia Institute of Technology
34
Copyright (C) 2010-2012 Marat Dukhan

‎include/cpuinfo.h

+91-21
Original file line numberDiff line numberDiff line change
@@ -38,10 +38,18 @@
3838
#define CPUINFO_ARCH_PNACL 1
3939
#endif
4040

41-
#if defined(EMSCRIPTEN)
41+
#if defined(__asmjs__)
4242
#define CPUINFO_ARCH_ASMJS 1
4343
#endif
4444

45+
#if defined(__wasm__)
46+
#if defined(__wasm_simd128__)
47+
#define CPUINFO_ARCH_WASMSIMD 1
48+
#else
49+
#define CPUINFO_ARCH_WASM 1
50+
#endif
51+
#endif
52+
4553
#if CPUINFO_ARCH_X86 && defined(_MSC_VER)
4654
#define CPUINFO_ABI __cdecl
4755
#elif CPUINFO_ARCH_X86 && defined(__GNUC__)
@@ -80,6 +88,14 @@
8088
#define CPUINFO_ARCH_ASMJS 0
8189
#endif
8290

91+
#ifndef CPUINFO_ARCH_WASM
92+
#define CPUINFO_ARCH_WASM 0
93+
#endif
94+
95+
#ifndef CPUINFO_ARCH_WASMSIMD
96+
#define CPUINFO_ARCH_WASMSIMD 0
97+
#endif
98+
8399
#define CPUINFO_CACHE_UNIFIED 0x00000001
84100
#define CPUINFO_CACHE_INCLUSIVE 0x00000002
85101
#define CPUINFO_CACHE_COMPLEX_INDEXING 0x00000004
@@ -278,24 +294,32 @@ enum cpuinfo_uarch {
278294
cpuinfo_uarch_haswell = 0x00100208,
279295
/** Intel Broadwell microarchitecture. */
280296
cpuinfo_uarch_broadwell = 0x00100209,
281-
/** Intel Sky Lake microarchitecture. */
297+
/** Intel Sky Lake microarchitecture (14 nm, including Kaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake). */
282298
cpuinfo_uarch_sky_lake = 0x0010020A,
283-
/** Intel Kaby Lake microarchitecture. */
284-
cpuinfo_uarch_kaby_lake = 0x0010020B,
299+
/** DEPRECATED (Intel Kaby Lake microarchitecture). */
300+
cpuinfo_uarch_kaby_lake = 0x0010020A,
301+
/** Intel Palm Cove microarchitecture (10 nm, Cannon Lake). */
302+
cpuinfo_uarch_palm_cove = 0x0010020B,
303+
/** Intel Sunny Cove microarchitecture (10 nm, Ice Lake). */
304+
cpuinfo_uarch_sunny_cove = 0x0010020C,
285305

286306
/** Pentium 4 with Willamette, Northwood, or Foster cores. */
287307
cpuinfo_uarch_willamette = 0x00100300,
288308
/** Pentium 4 with Prescott and later cores. */
289309
cpuinfo_uarch_prescott = 0x00100301,
290310

291311
/** Intel Atom on 45 nm process. */
292-
cpuinfo_uarch_bonnell = 0x00100400,
312+
cpuinfo_uarch_bonnell = 0x00100400,
293313
/** Intel Atom on 32 nm process. */
294-
cpuinfo_uarch_saltwell = 0x00100401,
314+
cpuinfo_uarch_saltwell = 0x00100401,
295315
/** Intel Silvermont microarchitecture (22 nm out-of-order Atom). */
296-
cpuinfo_uarch_silvermont = 0x00100402,
316+
cpuinfo_uarch_silvermont = 0x00100402,
297317
/** Intel Airmont microarchitecture (14 nm out-of-order Atom). */
298-
cpuinfo_uarch_airmont = 0x00100403,
318+
cpuinfo_uarch_airmont = 0x00100403,
319+
/** Intel Goldmont microarchitecture (Denverton, Apollo Lake). */
320+
cpuinfo_uarch_goldmont = 0x00100404,
321+
/** Intel Goldmont Plus microarchitecture (Gemini Lake). */
322+
cpuinfo_uarch_goldmont_plus = 0x00100405,
299323

300324
/** Intel Knights Ferry HPC boards. */
301325
cpuinfo_uarch_knights_ferry = 0x00100500,
@@ -335,8 +359,10 @@ enum cpuinfo_uarch {
335359
cpuinfo_uarch_steamroller = 0x00200107,
336360
/** AMD Excavator microarchitecture (Carizzo APUs). */
337361
cpuinfo_uarch_excavator = 0x00200108,
338-
/** AMD Zen microarchitecture (Ryzen CPUs). */
362+
/** AMD Zen microarchitecture (12/14 nm Ryzen and EPYC CPUs). */
339363
cpuinfo_uarch_zen = 0x00200109,
364+
/** AMD Zen 2 microarchitecture (7 nm Ryzen and EPYC CPUs). */
365+
cpuinfo_uarch_zen2 = 0x0020010A,
340366

341367
/** NSC Geode and AMD Geode GX and LX. */
342368
cpuinfo_uarch_geode = 0x00200200,
@@ -370,23 +396,34 @@ enum cpuinfo_uarch {
370396
cpuinfo_uarch_cortex_a17 = 0x00300217,
371397

372398
/** ARM Cortex-A32. */
373-
cpuinfo_uarch_cortex_a32 = 0x00300332,
399+
cpuinfo_uarch_cortex_a32 = 0x00300332,
374400
/** ARM Cortex-A35. */
375-
cpuinfo_uarch_cortex_a35 = 0x00300335,
401+
cpuinfo_uarch_cortex_a35 = 0x00300335,
376402
/** ARM Cortex-A53. */
377-
cpuinfo_uarch_cortex_a53 = 0x00300353,
403+
cpuinfo_uarch_cortex_a53 = 0x00300353,
378404
/** ARM Cortex-A55. */
379-
cpuinfo_uarch_cortex_a55 = 0x00300355,
405+
cpuinfo_uarch_cortex_a55 = 0x00300355,
380406
/** ARM Cortex-A57. */
381-
cpuinfo_uarch_cortex_a57 = 0x00300357,
407+
cpuinfo_uarch_cortex_a57 = 0x00300357,
408+
/** ARM Cortex-A65. */
409+
cpuinfo_uarch_cortex_a65 = 0x00300365,
382410
/** ARM Cortex-A72. */
383-
cpuinfo_uarch_cortex_a72 = 0x00300372,
411+
cpuinfo_uarch_cortex_a72 = 0x00300372,
384412
/** ARM Cortex-A73. */
385-
cpuinfo_uarch_cortex_a73 = 0x00300373,
413+
cpuinfo_uarch_cortex_a73 = 0x00300373,
386414
/** ARM Cortex-A75. */
387-
cpuinfo_uarch_cortex_a75 = 0x00300375,
415+
cpuinfo_uarch_cortex_a75 = 0x00300375,
388416
/** ARM Cortex-A76. */
389-
cpuinfo_uarch_cortex_a76 = 0x00300376,
417+
cpuinfo_uarch_cortex_a76 = 0x00300376,
418+
/** ARM Cortex-A76AE. */
419+
cpuinfo_uarch_cortex_a76ae = 0x00300378,
420+
/** ARM Cortex-A77. */
421+
cpuinfo_uarch_cortex_a77 = 0x00300377,
422+
423+
/** ARM Neoverse N1. */
424+
cpuinfo_uarch_neoverse_n1 = 0x00300400,
425+
/** ARM Neoverse E1. */
426+
cpuinfo_uarch_neoverse_e1 = 0x00300401,
390427

391428
/** Qualcomm Scorpion. */
392429
cpuinfo_uarch_scorpion = 0x00400100,
@@ -406,12 +443,22 @@ enum cpuinfo_uarch {
406443
/** Nvidia Carmel. */
407444
cpuinfo_uarch_carmel = 0x00500102,
408445

409-
/** Samsung Mongoose M1 (Exynos 8890 big cores). */
446+
/** Samsung Exynos M1 (Exynos 8890 big cores). */
447+
cpuinfo_uarch_exynos_m1 = 0x00600100,
448+
/** Samsung Exynos M2 (Exynos 8895 big cores). */
449+
cpuinfo_uarch_exynos_m2 = 0x00600101,
450+
/** Samsung Exynos M3 (Exynos 9810 big cores). */
451+
cpuinfo_uarch_exynos_m3 = 0x00600102,
452+
/** Samsung Exynos M4 (Exynos 9820 big cores). */
453+
cpuinfo_uarch_exynos_m4 = 0x00600103,
454+
/** Samsung Exynos M5 (Exynos 9830 big cores). */
455+
cpuinfo_uarch_exynos_m5 = 0x00600104,
456+
457+
/* Old names for Exynos. */
410458
cpuinfo_uarch_mongoose_m1 = 0x00600100,
411-
/** Samsung Mongoose M2 (Exynos 8895 big cores). */
412459
cpuinfo_uarch_mongoose_m2 = 0x00600101,
413-
/** Samsung Meerkat M3 (Exynos 9810 big cores). */
414460
cpuinfo_uarch_meerkat_m3 = 0x00600102,
461+
cpuinfo_uarch_meerkat_m4 = 0x00600103,
415462

416463
/** Apple A6 and A6X processors. */
417464
cpuinfo_uarch_swift = 0x00700100,
@@ -640,6 +687,8 @@ void CPUINFO_ABI cpuinfo_deinitialize(void);
640687
bool avx512bitalg;
641688
bool avx512vpopcntdq;
642689
bool avx512vnni;
690+
bool avx512bf16;
691+
bool avx512vp2intersect;
643692
bool avx512_4vnniw;
644693
bool avx512_4fmaps;
645694
bool hle;
@@ -1110,6 +1159,22 @@ static inline bool cpuinfo_has_x86_avx512vnni(void) {
11101159
#endif
11111160
}
11121161

1162+
static inline bool cpuinfo_has_x86_avx512bf16(void) {
1163+
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1164+
return cpuinfo_isa.avx512bf16;
1165+
#else
1166+
return false;
1167+
#endif
1168+
}
1169+
1170+
static inline bool cpuinfo_has_x86_avx512vp2intersect(void) {
1171+
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
1172+
return cpuinfo_isa.avx512vp2intersect;
1173+
#else
1174+
return false;
1175+
#endif
1176+
}
1177+
11131178
static inline bool cpuinfo_has_x86_avx512_4vnniw(void) {
11141179
#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
11151180
return cpuinfo_isa.avx512_4vnniw;
@@ -1682,6 +1747,11 @@ uint32_t CPUINFO_ABI cpuinfo_get_l2_caches_count(void);
16821747
uint32_t CPUINFO_ABI cpuinfo_get_l3_caches_count(void);
16831748
uint32_t CPUINFO_ABI cpuinfo_get_l4_caches_count(void);
16841749

1750+
/**
1751+
* Returns upper bound on cache size.
1752+
*/
1753+
uint32_t CPUINFO_ABI cpuinfo_get_max_cache_size(void);
1754+
16851755
const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_current_processor(void);
16861756
const struct cpuinfo_core* CPUINFO_ABI cpuinfo_get_current_core(void);
16871757

‎src/api.c

+8
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@ uint32_t cpuinfo_cores_count = 0;
1818
uint32_t cpuinfo_clusters_count = 0;
1919
uint32_t cpuinfo_packages_count = 0;
2020
uint32_t cpuinfo_cache_count[cpuinfo_cache_level_max] = { 0 };
21+
uint32_t cpuinfo_max_cache_size = 0;
2122

2223

2324
const struct cpuinfo_processor* cpuinfo_get_processors(void) {
@@ -244,3 +245,10 @@ uint32_t CPUINFO_ABI cpuinfo_get_l4_caches_count(void) {
244245
}
245246
return cpuinfo_cache_count[cpuinfo_cache_level_4];
246247
}
248+
249+
uint32_t CPUINFO_ABI cpuinfo_get_max_cache_size(void) {
250+
if (!cpuinfo_is_initialized) {
251+
cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "max_cache_size");
252+
}
253+
return cpuinfo_max_cache_size;
254+
}

‎src/arm/api.h

+3
Original file line numberDiff line numberDiff line change
@@ -104,6 +104,9 @@ CPUINFO_INTERNAL void cpuinfo_arm_decode_cache(
104104
struct cpuinfo_cache l1d[restrict static 1],
105105
struct cpuinfo_cache l2[restrict static 1],
106106
struct cpuinfo_cache l3[restrict static 1]);
107+
108+
CPUINFO_INTERNAL uint32_t cpuinfo_arm_compute_max_cache_size(
109+
const struct cpuinfo_processor processor[restrict static 1]);
107110
#else /* defined(__cplusplus) */
108111
CPUINFO_INTERNAL void cpuinfo_arm_decode_cache(
109112
enum cpuinfo_uarch uarch,

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