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InterpreterNodes.cpp
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/**
* Copyright (c) Glow Contributors. See CONTRIBUTORS file.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "glow/Backends/Interpreter/Interpreter.h"
#include "glow/Base/TensorSerialization.h"
#include "glow/Base/Type.h"
#include "glow/Flags/Flags.h"
#include "glow/IR/Instrs.h"
#include "glow/Quantization/Base/Base.h"
#include "glow/Quantization/Base/Profile.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/raw_ostream.h"
#include <chrono>
#include <cmath>
#include <numeric>
#include <random>
#include <type_traits>
#ifdef WIN32
#include <corecrt_math_defines.h>
#endif
using namespace glow;
namespace IntNBitSplitEmbeddingBagsHelper {
inline int32_t unpaddedRowSizeInBytes(int32_t dim,
SplitEmbeddingSparseType weight_ty) {
if (weight_ty == SplitEmbeddingSparseType::EST_FLOAT) {
return dim * sizeof(float);
}
if (weight_ty == SplitEmbeddingSparseType::EST_FLOAT16) {
return dim * sizeof(float16_t);
}
int32_t sizeOfFusedScaleOffset = glow::flags::ConvertFusedScaleOffsetToFP32
? sizeof(float)
: sizeof(float16_t);
if (weight_ty == SplitEmbeddingSparseType::EST_INT8) {
return dim + 2 * sizeOfFusedScaleOffset;
}
if (weight_ty == SplitEmbeddingSparseType::EST_INT4) {
return dim / 2 + 2 * sizeOfFusedScaleOffset;
}
if (weight_ty == SplitEmbeddingSparseType::EST_INT2) {
return dim / 4 + 2 * sizeOfFusedScaleOffset;
}
llvm_unreachable("Unsupported SparseType");
}
uint32_t roundUp(uint32_t a, uint32_t b) { return ((a + b - 1) / b) * b; }
inline int32_t paddedRowSizeInBytes(int32_t dim,
SplitEmbeddingSparseType weight_ty) {
auto r = unpaddedRowSizeInBytes(dim, weight_ty);
return roundUp(r, glow::interpreter::flags::RowAlignmentBytes);
}
template <typename SumTy>
SumTy add(SumTy a, const uint8_t *row, const uint8_t *data,
SplitEmbeddingSparseType dataTy, bool isMSB, float weight) {
float sum = a;
if (dataTy == SplitEmbeddingSparseType::EST_FLOAT) {
return sum + weight * static_cast<float>(
*(reinterpret_cast<const float *>(data)));
}
if (dataTy == SplitEmbeddingSparseType::EST_FLOAT16) {
return sum + weight * static_cast<float>(
*(reinterpret_cast<const float16_t *>(data)));
}
float scale, offset;
if (glow::flags::ConvertFusedScaleOffsetToFP32) {
scale = *(reinterpret_cast<const float *>(row));
offset = *(reinterpret_cast<const float *>(row) + 1);
} else {
scale = *(reinterpret_cast<const float16_t *>(row));
offset = *(reinterpret_cast<const float16_t *>(row) + 1);
}
if (dataTy == SplitEmbeddingSparseType::EST_INT8) {
return sum + weight * (static_cast<float>(*data) * scale + offset);
}
if (dataTy == SplitEmbeddingSparseType::EST_INT4) {
if (isMSB) {
return sum + weight * (static_cast<float>(*data >> 4) * scale + offset);
}
return sum + weight * (static_cast<float>(*data & 0xF) * scale + offset);
}
llvm_unreachable("Unsuppored SplitEmbeddingSparseType");
}
} // namespace IntNBitSplitEmbeddingBagsHelper
#define dispatchImpl(functionName, elemTy, ...) \
switch (elemTy) { \
case ElemKind::FloatTy: \
functionName<float>(__VA_ARGS__); \
break; \
case ElemKind::Float16Ty: \
functionName<float16_t>(__VA_ARGS__); \
break; \
case ElemKind::BFloat16Ty: \
functionName<bfloat16_t>(__VA_ARGS__); \
break; \
case ElemKind::Int8QTy: \
functionName<int8_t>(__VA_ARGS__); \
break; \
case ElemKind::Int16QTy: \
functionName<int16_t>(__VA_ARGS__); \
break; \
case ElemKind::Int32QTy: \
functionName<int32_t>(__VA_ARGS__); \
break; \
case ElemKind::Int32ITy: \
functionName<int32_t>(__VA_ARGS__); \
break; \
case ElemKind::Int64ITy: \
functionName<int64_t>(__VA_ARGS__); \
break; \
case ElemKind::BoolTy: \
functionName<bool>(__VA_ARGS__); \
break; \
default: \
llvm_unreachable("Type is not supported"); \
}
#define dispatchFloatingPointImpl(functionName, elemTy, ...) \
switch (elemTy) { \
case ElemKind::FloatTy: \
functionName<float>(__VA_ARGS__); \
break; \
case ElemKind::Float16Ty: \
functionName<float16_t>(__VA_ARGS__); \
break; \
case ElemKind::BFloat16Ty: \
functionName<bfloat16_t>(__VA_ARGS__); \
break; \
default: \
llvm_unreachable("Type is not supported"); \
}
#define dispatchFloatingPointAndInt32Impl(functionName, elemTy, ...) \
switch (elemTy) { \
case ElemKind::FloatTy: \
functionName<float>(__VA_ARGS__); \
break; \
case ElemKind::Float16Ty: \
functionName<float16_t>(__VA_ARGS__); \
break; \
case ElemKind::BFloat16Ty: \
functionName<bfloat16_t>(__VA_ARGS__); \
break; \
case ElemKind::Int32ITy: \
functionName<int>(__VA_ARGS__); \
break; \
default: \
llvm_unreachable("Type is not supported"); \
}
#define dispatchFloatingPointAndIndexImpl(functionName, elemTy, elemTyIndex, \
...) \
switch (elemTy) { \
case ElemKind::FloatTy: \
if (elemTyIndex == ElemKind::Int64ITy) { \
functionName<float, int64_t>(__VA_ARGS__); \
} else if (elemTyIndex == ElemKind::Int32ITy) { \
functionName<float, int32_t>(__VA_ARGS__); \
} \
break; \
case ElemKind::Float16Ty: \
if (elemTyIndex == ElemKind::Int64ITy) { \
functionName<float16, int64_t>(__VA_ARGS__); \
} else if (elemTyIndex == ElemKind::Int32ITy) { \
functionName<float16, int32_t>(__VA_ARGS__); \
} \
break; \
case ElemKind::BFloat16Ty: \
if (elemTyIndex == ElemKind::Int64ITy) { \
functionName<bfloat16, int64_t>(__VA_ARGS__); \
} else if (elemTyIndex == ElemKind::Int32ITy) { \
functionName<bfloat16, int32_t>(__VA_ARGS__); \
} \
break; \
default: \
llvm_unreachable("Type is not supported"); \
}
#define dispatchIndexTypeImpl(functionName, elemTy, ...) \
switch (elemTy) { \
case ElemKind::Int32ITy: \
functionName<int32_t>(__VA_ARGS__); \
break; \
case ElemKind::Int64ITy: \
functionName<int64_t>(__VA_ARGS__); \
break; \
default: \
llvm_unreachable("Type is not supported"); \
}
#define dispatchSplitEmbeddingTypeImpl(functionName, indexTy, outputTy, \
weightsOffsetTy, ...) \
switch (indexTy) { \
case ElemKind::Int32ITy: \
if (outputTy == SplitEmbeddingSparseType::EST_FLOAT) { \
if (weightsOffsetTy == ElemKind::Int32ITy) { \
functionName<int32_t, float, int32_t>(__VA_ARGS__); \
} else if (weightsOffsetTy == ElemKind::Int64ITy) { \
functionName<int32_t, float, int64_t>(__VA_ARGS__); \
} \
} else if (outputTy == SplitEmbeddingSparseType::EST_FLOAT16) { \
if (weightsOffsetTy == ElemKind::Int32ITy) { \
functionName<int32_t, float16, int32_t>(__VA_ARGS__); \
} else if (weightsOffsetTy == ElemKind::Int64ITy) { \
functionName<int32_t, float16, int64_t>(__VA_ARGS__); \
} \
} \
break; \
case ElemKind::Int64ITy: \
if (outputTy == SplitEmbeddingSparseType::EST_FLOAT) { \
if (weightsOffsetTy == ElemKind::Int32ITy) { \
functionName<int64_t, float, int32_t>(__VA_ARGS__); \
} else if (weightsOffsetTy == ElemKind::Int64ITy) { \
functionName<int64_t, float, int64_t>(__VA_ARGS__); \
} \
} else if (outputTy == SplitEmbeddingSparseType::EST_FLOAT16) { \
if (weightsOffsetTy == ElemKind::Int32ITy) { \
functionName<int64_t, float16, int32_t>(__VA_ARGS__); \
} else if (weightsOffsetTy == ElemKind::Int64ITy) { \
functionName<int64_t, float16, int64_t>(__VA_ARGS__); \
} \
} \
break; \
default: \
llvm_unreachable("Type is not supported"); \
}
#define dispatchArithmeticImpl(functionName, elemTy, ...) \
switch (elemTy) { \
case ElemKind::FloatTy: \
functionName<float>(__VA_ARGS__); \
break; \
case ElemKind::Float16Ty: \
functionName<float16_t>(__VA_ARGS__); \
break; \
case ElemKind::BFloat16Ty: \
functionName<bfloat16_t>(__VA_ARGS__); \
break; \
case ElemKind::Int32ITy: \
functionName<int32_t>(__VA_ARGS__); \
break; \
case ElemKind::Int64ITy: \
functionName<int64_t>(__VA_ARGS__); \
break; \
default: \
llvm_unreachable("Type is not supported"); \
}
#define dispatchBitwiseImpl(functionName, elemTy, ...) \
switch (elemTy) { \
case ElemKind::Int32ITy: \
functionName<int32_t>(__VA_ARGS__); \
break; \
case ElemKind::Int64ITy: \
functionName<int64_t>(__VA_ARGS__); \
break; \
case ElemKind::BoolTy: \
functionName<bool>(__VA_ARGS__); \
break; \
default: \
llvm_unreachable("Type is not supported"); \
}
#define dispatchQuantizedImpl(functionName, elemTy, ...) \
switch (elemTy) { \
case ElemKind::Int8QTy: \
functionName<int8_t>(__VA_ARGS__); \
break; \
case ElemKind::Int16QTy: \
functionName<int16_t>(__VA_ARGS__); \
break; \
case ElemKind::Int32QTy: \
functionName<int32_t>(__VA_ARGS__); \
break; \
default: \
llvm_unreachable("Type is not supported"); \
}
#define dispatchQuantizedWithAccumulationImpl(functionName, elemTy, ...) \
switch (elemTy) { \
case ElemKind::Int8QTy: \
functionName<int8_t, int32_t>(__VA_ARGS__); \
break; \
case ElemKind::Int16QTy: \
functionName<int16_t, int64_t>(__VA_ARGS__); \
break; \
default: \
llvm_unreachable("Type is not supported"); \
}
#define dispatchQuantizedWithAccumulationAndBiasImpl(functionName, elemTy, \
biasElemType, ...) \
if (elemTy == ElemKind::Int8QTy && biasElemType == ElemKind::Int8QTy) { \
functionName<int8_t, int32_t, int8_t>(__VA_ARGS__); \
} else if (elemTy == ElemKind::Int8QTy && \
biasElemType == ElemKind::Int32QTy) { \
functionName<int8_t, int32_t, int32_t>(__VA_ARGS__); \
} else if (elemTy == ElemKind::Int16QTy && \
biasElemType == ElemKind::Int16QTy) { \
functionName<int16_t, int64_t, int16_t>(__VA_ARGS__); \
} else if (elemTy == ElemKind::Int16QTy && \
biasElemType == ElemKind::Int32QTy) { \
functionName<int16_t, int64_t, int32_t>(__VA_ARGS__); \
} else { \
llvm_unreachable("Type is not supported"); \
}
#define staticAssertFloatingPointType(ElemTy) \
static_assert( \
std::is_floating_point<ElemTy>::value || \
std::is_same<float16_t, \
typename std::remove_cv<ElemTy>::type>::value || \
std::is_same<bfloat16_t, \
typename std::remove_cv<ElemTy>::type>::value, \
"This implementation is for floating-point values only")
#define staticAssertArithmeticType(ElemTy) \
static_assert( \
std::is_arithmetic<ElemTy>::value || \
std::is_same<float16_t, \
typename std::remove_cv<ElemTy>::type>::value || \
std::is_same<bfloat16_t, \
typename std::remove_cv<ElemTy>::type>::value, \
"This implementation is for arithmetic values only")
#ifndef MIN
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#ifndef MAX
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
// Provides a bitwise `and` that isn't concerned about bools
template <typename T> T safe_bitwise_and(const T &a, const T &b) {
return a & b;
}
template <> bool safe_bitwise_and(const bool &a, const bool &b) {
return a && b;
}
// Provides a bitwise `or` that isn't concerned about bools
template <typename T> T safe_bitwise_or(const T &a, const T &b) {
return a | b;
}
template <> bool safe_bitwise_or(const bool &a, const bool &b) {
return a || b;
}
//===----------------------------------------------------------------------===//
// Convolution
//===----------------------------------------------------------------------===//
/// This is the floating point implementation of Convolution.
template <typename ElemTy>
void BoundInterpreterFunction::fwdConvolutionInstFloatImpl(
Value *inV, Value *outV, Value *filterV, Value *biasV,
llvm::ArrayRef<unsigned_t> kernelSizes, llvm::ArrayRef<unsigned_t> strides,
llvm::ArrayRef<unsigned_t> pads, size_t group,
llvm::ArrayRef<unsigned_t> dilation) {
staticAssertFloatingPointType(ElemTy);
auto inW = getWeightHandle<ElemTy>(inV);
auto outW = getWeightHandle<ElemTy>(outV);
auto filterW = getWeightHandle<ElemTy>(filterV);
auto biasW = getWeightHandle<ElemTy>(biasV);
ShapeNHWC odim(outW.dims());
ShapeNHWC idim(inW.dims());
ShapeHW kdim(kernelSizes);
ShapeHW sdim(strides);
assert(idim.c % group == 0 && "Input channels must be divisible by group.");
assert(odim.c % group == 0 && "Output channels must be divisible by group.");
dim_t inCperG = idim.c / group;
dim_t outCperG = odim.c / group;
PaddingTLBR pdim(pads);
// For each input in the batch:
for (dim_t n = 0; n < idim.n; n++) {
// For each group of input channels:
for (dim_t g = 0; g < group; g++) {
// For each output channel in the group:
for (dim_t d = g * outCperG; d < (g + 1) * outCperG; d++) {
// For each convolution 'jump' in the input tensor:
ssize_t x = -ssize_t(pdim.top);
for (dim_t ax = 0; ax < odim.h; x += sdim.height, ax++) {
ssize_t y = -ssize_t(pdim.left);
for (dim_t ay = 0; ay < odim.w; y += sdim.width, ay++) {
// For each element in the convolution-filter:
float sum = 0;
for (dim_t fx = 0; fx < kdim.height; fx++) {
for (dim_t fy = 0; fy < kdim.width; fy++) {
sdim_t ox = x + fx * dilation[0];
sdim_t oy = y + fy * dilation[1];
// Ignore index access below zero (this is due to padding).
if (ox < 0 || oy < 0 || ox >= ssize_t(idim.h) ||
oy >= ssize_t(idim.w)) {
continue;
}
for (dim_t fd = 0; fd < inCperG; fd++) {
sum += float(
filterW.at({d, fx, fy, fd}) *
inW.at({n, (dim_t)ox, (dim_t)oy, g * inCperG + fd}));
}
}
}
sum += float(biasW.at({d}));
outW.at({n, ax, ay, d}) = ElemTy(sum);
} // W
} // H
} // C
} // G
} // N
}
/// This is the quantized implementation of Convolution.
template <typename ElemTy, typename AccumulatorTy, typename BiasElemTy>
void BoundInterpreterFunction::fwdConvolutionInstQuantizedImpl(
Value *inV, Value *outV, Value *filterV, Value *biasV,
llvm::ArrayRef<unsigned_t> kernelSizes, llvm::ArrayRef<unsigned_t> strides,
llvm::ArrayRef<unsigned_t> pads, size_t group,
llvm::ArrayRef<unsigned_t> dilation) {
auto inW = getWeightHandle<ElemTy>(inV);
auto outW = getWeightHandle<ElemTy>(outV);
auto filterW = getWeightHandle<ElemTy>(filterV);
auto biasW = getWeightHandle<BiasElemTy>(biasV);
ShapeNHWC odim(outW.dims());
ShapeNHWC idim(inW.dims());
ShapeHW kdim(kernelSizes);
ShapeHW sdim(strides);
assert(idim.c % group == 0 && "Input channels must be divisible by group.");
assert(odim.c % group == 0 && "Output channels must be divisible by group.");
dim_t inCperG = idim.c / group;
dim_t outCperG = odim.c / group;
PaddingTLBR pdim(pads);
auto outTy = outV->getType();
auto inTy = inV->getType();
auto filterTy = filterV->getType();
auto biasTy = biasV->getType();
int32_t outOffset = outTy->getOffset();
int32_t inOffset = inTy->getOffset();
int32_t filterOffset = filterTy->getOffset();
int32_t biasOffset = biasTy->getOffset();
float outScale = outTy->getScale();
float inScale = inTy->getScale();
float filterScale = filterTy->getScale();
float biasScale = biasTy->getScale();
// Calculate the scale of the values that come out of the matrix
// multiplication part of the calculation.
float matMulScale = inScale * filterScale;
// For each input in the batch:
for (dim_t n = 0; n < idim.n; n++) {
// For each group of input channels:
for (dim_t g = 0; g < group; g++) {
// For each output channel in the group:
for (dim_t d = g * outCperG; d < (g + 1) * outCperG; d++) {
// For each convolution 'jump' in the input tensor:
ssize_t x = -ssize_t(pdim.top);
for (dim_t ax = 0; ax < odim.h; x += sdim.height, ax++) {
ssize_t y = -ssize_t(pdim.left);
for (dim_t ay = 0; ay < odim.w; y += sdim.width, ay++) {
// For each element in the convolution-filter:
AccumulatorTy sum = 0;
for (dim_t fx = 0; fx < kdim.height; fx++) {
for (dim_t fy = 0; fy < kdim.width; fy++) {
sdim_t ox = x + fx * dilation[0];
sdim_t oy = y + fy * dilation[1];
// Ignore index access below zero (this is due to padding).
if (ox < 0 || oy < 0 || ox >= ssize_t(idim.h) ||
oy >= sdim_t(idim.w)) {
continue;
}
for (dim_t fd = 0; fd < inCperG; fd++) {
AccumulatorTy F = filterW.at({d, fx, fy, fd});
AccumulatorTy I =
inW.at({n, (dim_t)ox, (dim_t)oy, g * inCperG + fd});
// We represent the element multiplication with offset as
// (value - offset).
sum += (F - filterOffset) * (I - inOffset);
}
}
}
// Scale the bias to match the scale of the matrix multiplication.
AccumulatorTy B = std::round(float(biasW.at({d}) - biasOffset) *
(biasScale / matMulScale));
// Add the bias.
sum += B;
// Scale the result back to the expected destination scale.
outW.at({n, ax, ay, d}) = quantization::clip<AccumulatorTy, ElemTy>(
std::round(float(sum) * (matMulScale / outScale) + outOffset));
} // W
} // H
} // C
} // G
} // N
}
/// This is the floating point implementation of ConvTranspose.
template <typename ElemTy>
void BoundInterpreterFunction::fwdConvTransposeInstFloatImpl(
Value *inV, Value *outV, Value *filterV, Value *biasV,
llvm::ArrayRef<unsigned_t> kernelSizes, llvm::ArrayRef<unsigned_t> strides,
llvm::ArrayRef<unsigned_t> pads, size_t group,
llvm::ArrayRef<unsigned_t> dilation) {
staticAssertFloatingPointType(ElemTy);
auto inW = getWeightHandle<ElemTy>(inV);
auto outW = getWeightHandle<ElemTy>(outV);
auto filterW = getWeightHandle<ElemTy>(filterV);
auto biasW = getWeightHandle<ElemTy>(biasV);
ShapeNHWC odim(outW.dims());
ShapeNHWC idim(inW.dims());
ShapeHW kdim(kernelSizes);
ShapeHW sdim(strides);
assert(idim.c % group == 0 && "Input channels must be divisible by group.");
assert(odim.c % group == 0 && "Output channels must be divisible by group.");
dim_t inCperG = idim.c / group;
dim_t outCperG = odim.c / group;
PaddingTLBR pdim(pads);
// For each input in the batch:
for (dim_t n = 0; n < idim.n; n++) {
// Initialize bias (TODO take out to a separate function when quant is in).
for (dim_t ax = 0; ax < odim.h; ax++) {
for (dim_t ay = 0; ay < odim.w; ay++) {
for (dim_t d = 0; d < odim.c; d++) {
outW.at({n, ax, ay, d}) = static_cast<ElemTy>(biasW.at({d}));
}
}
}
// For each group of input channels:
for (dim_t g = 0; g < group; g++) {
// For each input channel in the group:
for (dim_t d = g * inCperG; d < (g + 1) * inCperG; d++) {
// For each transposed convolution 'jump' in the input tensor:
ssize_t x = -ssize_t(pdim.top);
for (dim_t bx = 0; bx < idim.h; bx++, x += sdim.height) {
ssize_t y = -ssize_t(pdim.left);
for (dim_t by = 0; by < idim.w; by++, y += sdim.width) {
// For each element in the each transposed convolution filter:
ElemTy input = inW.at({n, bx, by, d});
for (dim_t kx = 0; kx < kdim.height; kx++) {
for (dim_t ky = 0; ky < kdim.width; ky++) {
ssize_t ax = x + kx * dilation[0];
ssize_t ay = y + ky * dilation[1];
// Ignore index access below zero (this is due to padding).
if (ax < 0 || ay < 0 || ax >= ssize_t(odim.h) ||
ay >= ssize_t(odim.w)) {
continue;
}
for (dim_t c = 0; c < outCperG; c++) {
outW.at({n, (dim_t)ax, (dim_t)ay, g * outCperG + c}) +=
filterW.at({c, kx, ky, d}) * input;
}
}
}
} // W
} // H
} // C
} // G
} // N
}
void BoundInterpreterFunction::fwdConvTransposeInst(
const ConvTransposeInst *I) {
auto kernelSizes = I->getKernels();
auto pads = I->getPads();
auto strides = I->getStrides();
size_t group = I->getGroup();
if (I->getSrc()->getType()->isQuantizedType()) {
llvm_unreachable("Quantized ConvTranspose not supported");
return;
}
dispatchFloatingPointImpl(
fwdConvTransposeInstFloatImpl, I->getSrc()->getElementType(), I->getSrc(),
I->getDest(), I->getFilter(), I->getBias(), kernelSizes, strides, pads,
group, I->getDilation());
}
void BoundInterpreterFunction::fwdConvolutionInst(const ConvolutionInst *I) {
auto kernelSizes = I->getKernels();
auto pads = I->getPads();
auto strides = I->getStrides();
size_t group = I->getGroup();
if (I->getSrc()->getType()->isQuantizedType()) {
dispatchQuantizedWithAccumulationAndBiasImpl(
fwdConvolutionInstQuantizedImpl, I->getSrc()->getElementType(),
I->getBias()->getElementType(), I->getSrc(), I->getDest(),
I->getFilter(), I->getBias(), kernelSizes, strides, pads, group,
I->getDilation());
return;
}
dispatchFloatingPointImpl(
fwdConvolutionInstFloatImpl, I->getSrc()->getElementType(), I->getSrc(),
I->getDest(), I->getFilter(), I->getBias(), kernelSizes, strides, pads,
group, I->getDilation());
}
void BoundInterpreterFunction::fwdFusionGroupInst(
const glow::FusionGroupInst *p) {
llvm_unreachable(
"Fusion Group instruction not supported on Inrerpretter backend\n");
}
void BoundInterpreterFunction::fwdConcatInst(const ConcatInst *I) {
(void)I;
// TODO
llvm_unreachable("not yet implemented");
}
void BoundInterpreterFunction::fwdConvolutionGradInst(
const ConvolutionGradInst *I) {
auto inW = getWeightHandle(I->getSrc());
auto inG = getWeightHandle(I->getSrcGrad());
auto outG = getWeightHandle(I->getDestGrad());
auto filterW = getWeightHandle(I->getFilter());
auto filterG = getWeightHandle(I->getFilterGrad());
auto biasG = getWeightHandle(I->getBiasGrad());
size_t group = I->getGroup();
auto dilation = I->getDilation();
inG.clear();
filterG.clear();
biasG.clear();
ShapeNHWC odim(outG.dims());
ShapeNHWC idim(inW.dims());
ShapeHW kdim(I->getKernels());
ShapeHW sdim(I->getStrides());
PaddingTLBR pdim(I->getPads());
assert(idim.c % group == 0 && "Input channels must be divisible by group.");
assert(odim.c % group == 0 && "Output channels must be divisible by group.");
dim_t inCperG = idim.c / group;
dim_t outCperG = odim.c / group;
// For each input in the batch:
for (dim_t n = 0; n < odim.n; n++) {
// For each group of input channels:
for (dim_t g = 0; g < group; g++) {
// Compute the gradient. For each layer in the output tensor:
for (dim_t d = g * outCperG; d < (g + 1) * outCperG; d++) {
// For each convolution 'jump' in the input tensor:
sdim_t x = -sdim_t(pdim.top);
for (dim_t ax = 0; ax < odim.h; x += sdim.height, ax++) {
sdim_t y = -sdim_t(pdim.left);
for (dim_t ay = 0; ay < odim.w; y += sdim.width, ay++) {
float chainGrad = outG.at({n, ax, ay, d});
// For each element in the convolution-filter:
for (dim_t fx = 0; fx < kdim.height; fx++) {
for (dim_t fy = 0; fy < kdim.width; fy++) {
sdim_t ox = x + fx * dilation[0];
sdim_t oy = y + fy * dilation[1];
// Ignore index access below zero (this is due to padding).
if (ox < 0 || oy < 0 || ox >= ssize_t(idim.h) ||
oy >= sdim_t(idim.w)) {
continue;
}
for (dim_t fd = 0; fd < inCperG; fd++) {
filterG.at({d, fx, fy, fd}) +=
inW.at({n, (dim_t)ox, (dim_t)oy, g * inCperG + fd}) *
chainGrad;
inG.at({n, (dim_t)ox, (dim_t)oy, g * inCperG + fd}) +=
filterW.at({d, fx, fy, fd}) * chainGrad;
}
}
}
biasG.at({d}) += chainGrad;
} // W
} // H
} // C
} // G
} // N
}
/// This is the floating point implementation of Convolution3D.
template <typename ElemTy>
void BoundInterpreterFunction::fwdConvolution3DInstFloatImpl(
Value *inV, Value *outV, Value *filterV, Value *biasV,
llvm::ArrayRef<unsigned_t> kernelSizes, llvm::ArrayRef<unsigned_t> strides,
llvm::ArrayRef<unsigned_t> pads, size_t group) {
staticAssertFloatingPointType(ElemTy);
auto inW = getWeightHandle<ElemTy>(inV);
auto outW = getWeightHandle<ElemTy>(outV);
auto filterW = getWeightHandle<ElemTy>(filterV);
auto biasW = getWeightHandle<ElemTy>(biasV);
ShapeNTHWC odim(outW.dims());
ShapeNTHWC idim(inW.dims());
ShapeTHW kdim(kernelSizes);
ShapeTHW sdim(strides);
assert(idim.c % group == 0 && "Input channels must be divisible by group.");
assert(odim.c % group == 0 && "Output channels must be divisible by group.");
dim_t inCperG = idim.c / group;
dim_t outCperG = odim.c / group;
PaddingNFTBLR pdim(pads);
// For each input in the batch:
for (dim_t n = 0; n < idim.n; n++) {
// For each group of input channels:
for (dim_t ig = 0; ig < group; ig++) {
// For each output channel in the group:
for (dim_t og = ig * outCperG; og < (ig + 1) * outCperG; og++) {
ssize_t t = -ssize_t(pdim.near);
for (dim_t at = 0; at < odim.t; t += sdim.temporal_frames, at++) {
// For each convolution 'jump' in the input tensor:
ssize_t x = -ssize_t(pdim.top);
for (dim_t ax = 0; ax < odim.h; x += sdim.height, ax++) {
ssize_t y = -ssize_t(pdim.left);
for (dim_t ay = 0; ay < odim.w; y += sdim.width, ay++) {
// For each element in the 3D convolution-filter:
float sum = 0;
for (dim_t ft = 0; ft < kdim.temporal_frames; ft++) {
for (dim_t fx = 0; fx < kdim.height; fx++) {
for (dim_t fy = 0; fy < kdim.width; fy++) {
sdim_t ot = t + ft;
sdim_t ox = x + fx;
sdim_t oy = y + fy;
// Ignore index access below zero (this is due to padding).
if (ot < 0 || ox < 0 || oy < 0 || ot >= ssize_t(idim.t) ||
ox >= ssize_t(idim.h) || oy >= ssize_t(idim.w)) {
continue;
}
for (dim_t fg = 0; fg < inCperG; fg++) {
sum += float(filterW.at({og, ft, fx, fy, fg}) *
inW.at({n, (dim_t)ot, (dim_t)ox, (dim_t)oy,
ig * inCperG + fg}));
}
}
}
}
sum += float(biasW.at({og}));
outW.at({n, at, ax, ay, og}) = ElemTy(sum);
} // D
} // W
} // H
} // C
} // G
} // N
}
/// This is the quantized implementation of Convolution3D.
template <typename ElemTy, typename AccumulatorTy, typename BiasElemTy>
void BoundInterpreterFunction::fwdConvolution3DInstQuantizedImpl(
Value *inV, Value *outV, Value *filterV, Value *biasV,
llvm::ArrayRef<unsigned_t> kernelSizes, llvm::ArrayRef<unsigned_t> strides,
llvm::ArrayRef<unsigned_t> pads, size_t group) {
auto inW = getWeightHandle<ElemTy>(inV);
auto outW = getWeightHandle<ElemTy>(outV);
auto filterW = getWeightHandle<ElemTy>(filterV);
auto biasW = getWeightHandle<BiasElemTy>(biasV);
ShapeNTHWC odim(outW.dims());
ShapeNTHWC idim(inW.dims());
ShapeTHW kdim(kernelSizes);
ShapeTHW sdim(strides);
assert(idim.c % group == 0 && "Input channels must be divisible by group.");
assert(odim.c % group == 0 && "Output channels must be divisible by group.");
dim_t inCperG = idim.c / group;
dim_t outCperG = odim.c / group;
PaddingNFTBLR pdim(pads);
auto outTy = outV->getType();
auto inTy = inV->getType();
auto filterTy = filterV->getType();
auto biasTy = biasV->getType();
int32_t outOffset = outTy->getOffset();
int32_t inOffset = inTy->getOffset();
int32_t filterOffset = filterTy->getOffset();
int32_t biasOffset = biasTy->getOffset();
float outScale = outTy->getScale();
float inScale = inTy->getScale();
float filterScale = filterTy->getScale();
float biasScale = biasTy->getScale();
// Calculate the scale of the values that come out of the matrix
// multiplication part of the calculation.
float matMulScale = inScale * filterScale;
// For each input in the batch:
for (dim_t n = 0; n < idim.n; n++) {
// For each group of input channels:
for (dim_t ig = 0; ig < group; ig++) {
// For each output channel in the group:
for (dim_t og = ig * outCperG; og < (ig + 1) * outCperG; og++) {
// For each convolution 'jump' in the input tensor:
ssize_t t = -ssize_t(pdim.near);
for (dim_t at = 0; at < odim.t; t += sdim.temporal_frames, at++) {
ssize_t x = -ssize_t(pdim.top);
for (dim_t ax = 0; ax < odim.h; x += sdim.height, ax++) {
ssize_t y = -ssize_t(pdim.left);
for (dim_t ay = 0; ay < odim.w; y += sdim.width, ay++) {
// For each element in the convolution-filter:
AccumulatorTy sum = 0;
for (dim_t ft = 0; ft < kdim.temporal_frames; ft++) {
for (dim_t fx = 0; fx < kdim.height; fx++) {
for (dim_t fy = 0; fy < kdim.width; fy++) {
ssize_t ot = t + ft;
ssize_t ox = x + fx;
ssize_t oy = y + fy;
// Ignore index access below zero (this is due to padding).
if (ot < 0 || ox < 0 || oy < 0 || ot >= ssize_t(idim.t) ||
ox >= ssize_t(idim.h) || oy >= ssize_t(idim.w)) {
continue;
}
for (dim_t fg = 0; fg < inCperG; fg++) {
AccumulatorTy F = filterW.at({og, ft, fx, fy, fg});
AccumulatorTy I = inW.at({n, (dim_t)ot, (dim_t)ox,
(dim_t)oy, ig * inCperG + fg});
// We represent the element multiplication with offset as
// (value - offset).
sum += (F - filterOffset) * (I - inOffset);
}
}
}
}
// Scale the bias to match the scale of the matrix multiplication.
AccumulatorTy B = std::round(float(biasW.at({og}) - biasOffset) *
(biasScale / matMulScale));
// Add the bias:
sum += B;
// Scale the result back to the expected destination scale.
outW.at({n, at, ax, ay, og}) =
quantization::clip<AccumulatorTy, ElemTy>(std::round(
float(sum) * (matMulScale / outScale) + outOffset));
} // D
} // W
} // H
} // C
} // G
} // N
}
void BoundInterpreterFunction::fwdConvolution3DInst(
const Convolution3DInst *I) {
auto kernelSizes = I->getKernels();
auto pads = I->getPads();
auto strides = I->getStrides();
size_t group = I->getGroup();
if (I->getSrc()->getType()->isQuantizedType()) {
dispatchQuantizedWithAccumulationAndBiasImpl(
fwdConvolution3DInstQuantizedImpl, I->getSrc()->getElementType(),
I->getBias()->getElementType(), I->getSrc(), I->getDest(),
I->getFilter(), I->getBias(), kernelSizes, strides, pads, group);
return;
}
dispatchFloatingPointImpl(fwdConvolution3DInstFloatImpl,
I->getSrc()->getElementType(), I->getSrc(),
I->getDest(), I->getFilter(), I->getBias(),
kernelSizes, strides, pads, group);
}
void BoundInterpreterFunction::fwdConvolution3DGradInst(
const Convolution3DGradInst *I) {
(void)I;
// TODO
llvm_unreachable("not yet implemented");
}
//===----------------------------------------------------------------------===//
// Channelwise quantized Convolution
//===----------------------------------------------------------------------===//
template <typename ElemTy, typename AccumulatorTy, typename BiasElemTy>
void BoundInterpreterFunction::fwdChannelwiseQuantizedConv2DInstImpl(
const ChannelwiseQuantizedConvolutionInst *I) {
auto inW = getWeightHandle<ElemTy>(I->getSrc());
auto outW = getWeightHandle<ElemTy>(I->getDest());
auto filterW = getWeightHandle<ElemTy>(I->getFilter());
auto biasW = getWeightHandle<BiasElemTy>(I->getBias());
auto filterScales = getWeightHandle<float>(I->getFilterScales());
auto filterOffsets = getWeightHandle<int32_t>(I->getFilterOffsets());
auto biasScales = getWeightHandle<float>(I->getBiasScales());
auto biasOffsets = getWeightHandle<int32_t>(I->getBiasOffsets());
llvm::ArrayRef<unsigned_t> kernelSizes = I->getKernels();
llvm::ArrayRef<unsigned_t> pads = I->getPads();
llvm::ArrayRef<unsigned_t> strides = I->getStrides();
dim_t group = I->getGroup();
llvm::ArrayRef<unsigned_t> dilation = I->getDilation();
ShapeNHWC odim(outW.dims());
ShapeNHWC idim(inW.dims());
ShapeHW kdim(kernelSizes);
ShapeHW sdim(strides);
assert(idim.c % group == 0 && "Input channels must be divisible by group.");
assert(odim.c % group == 0 && "Output channels must be divisible by group.");
dim_t inCperG = idim.c / group;
dim_t outCperG = odim.c / group;
PaddingTLBR pdim(pads);
auto &inTy = inW.getType();
auto &outTy = outW.getType();
float inScale = inTy.getScale();
float outScale = outTy.getScale();