Skip to content

Commit 6e0024f

Browse files
committed
enable 6 chip selects on SPI0
1 parent beea6d9 commit 6e0024f

File tree

3 files changed

+93
-0
lines changed

3 files changed

+93
-0
lines changed

arch/arm/boot/dts/overlays/Makefile

+1
Original file line numberDiff line numberDiff line change
@@ -265,6 +265,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
265265
spi0-1cs.dtbo \
266266
spi0-1cs-inverted.dtbo \
267267
spi0-2cs.dtbo \
268+
spi0-6cs.dtbo \
268269
spi1-1cs.dtbo \
269270
spi1-2cs.dtbo \
270271
spi1-3cs.dtbo \

arch/arm/boot/dts/overlays/README

+13
Original file line numberDiff line numberDiff line change
@@ -4716,6 +4716,19 @@ Params: cs0_pin GPIO pin for CS0 (default 8)
47164716
it for other uses.
47174717

47184718

4719+
Name: spi0-6cs
4720+
Info: Change the CS pins for SPI0
4721+
Load: dtoverlay=spi0-6cs,<param>=<val>
4722+
Params: cs0_pin GPIO pin for CS0 (default 8)
4723+
cs1_pin GPIO pin for CS1 (default 13)
4724+
cs2_pin GPIO pin for CS1 (default 16)
4725+
cs3_pin GPIO pin for CS1 (default 17)
4726+
cs4_pin GPIO pin for CS1 (default 18)
4727+
cs5_pin GPIO pin for CS1 (default 19)
4728+
no_miso Don't claim and use the MISO pin (9), freeing
4729+
it for other uses.
4730+
4731+
47194732
Name: spi0-cs
47204733
Info: This overlay has been renamed spi0-2cs, keeping spi0-cs as an
47214734
alias for backwards compatibility.
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
1+
/dts-v1/;
2+
/plugin/;
3+
4+
5+
/ {
6+
compatible = "brcm,bcm2835";
7+
8+
fragment@0 {
9+
target = <&spi0_cs_pins>;
10+
frag0: __overlay__ {
11+
brcm,pins = <8 13 16 17 18 19>;
12+
};
13+
};
14+
15+
fragment@1 {
16+
target = <&spi0>;
17+
frag1: __overlay__ {
18+
cs-gpios = <&gpio 8 1>, <&gpio 13 1>, <&gpio 16 1>, <&gpio 17 1>, <&gpio 18 1>, <&gpio 19 1>;
19+
status = "okay";
20+
};
21+
};
22+
23+
fragment@2 {
24+
target = <&spi0_pins>;
25+
__dormant__ {
26+
brcm,pins = <9 10 11>;
27+
};
28+
};
29+
30+
fragment@3 {
31+
target = <&spi0>;
32+
frag3: __overlay__ {
33+
spidev2: spidev@2 {
34+
compatible = "spidev";
35+
reg = <2>; /* CE2 */
36+
#address-cells = <1>;
37+
#size-cells = <0>;
38+
spi-max-frequency = <125000000>;
39+
};
40+
spidev3: spidev@3 {
41+
compatible = "spidev";
42+
reg = <3>; /* CE3 */
43+
#address-cells = <1>;
44+
#size-cells = <0>;
45+
spi-max-frequency = <125000000>;
46+
};
47+
spidev4: spidev@4 {
48+
compatible = "spidev";
49+
reg = <4>; /* CE4 */
50+
#address-cells = <1>;
51+
#size-cells = <0>;
52+
spi-max-frequency = <125000000>;
53+
};
54+
spidev5: spidev@5 {
55+
compatible = "spidev";
56+
reg = <5>; /* CE5 */
57+
#address-cells = <1>;
58+
#size-cells = <0>;
59+
spi-max-frequency = <125000000>;
60+
};
61+
};
62+
};
63+
64+
__overrides__ {
65+
cs0_pin = <&frag0>,"brcm,pins:0",
66+
<&frag1>,"cs-gpios:4";
67+
cs1_pin = <&frag0>,"brcm,pins:4",
68+
<&frag1>,"cs-gpios:16";
69+
cs2_pin = <&frag0>,"brcm,pins:8",
70+
<&frag1>,"cs-gpios:28";
71+
cs3_pin = <&frag0>,"brcm,pins:12",
72+
<&frag1>,"cs-gpios:40";
73+
cs4_pin = <&frag0>,"brcm,pins:16",
74+
<&frag1>,"cs-gpios:52";
75+
cs5_pin = <&frag0>,"brcm,pins:20",
76+
<&frag1>,"cs-gpios:64";
77+
no_miso = <0>,"=2";
78+
};
79+
};

0 commit comments

Comments
 (0)