Skip to content

Commit 88fa831

Browse files
tarek-bochkatitom-van
tarek-bochkati
authored and
tom-van
committed
flash/stm32l4x: introduce stm32l4_part_info.flags for devices features
instead of adding a new member into stm32l4_part_info for every relevant feature, .flags serves as container for the devices' features. identified features: F_HAS_DUAL_BANK, F_USE_ALL_WRPXX, F_HAS_TZ Change-Id: I3093e54c6509dec33043ebe6f87675198bf1967a Signed-off-by: Tarek BOCHKATI <[email protected]> Reviewed-on: http://openocd.zylin.com/5540 Tested-by: jenkins Reviewed-by: Tomas Vanek <[email protected]>
1 parent 03e2bc0 commit 88fa831

File tree

1 file changed

+33
-39
lines changed

1 file changed

+33
-39
lines changed

‎src/flash/nor/stm32l4x.c

+33-39
Original file line numberDiff line numberDiff line change
@@ -116,6 +116,19 @@
116116

117117
#define FLASH_ERASE_TIMEOUT 250
118118

119+
120+
/* relevant STM32L4 flags ****************************************************/
121+
#define F_NONE 0
122+
/* this flag indicates if the device flash is with dual bank architecture */
123+
#define F_HAS_DUAL_BANK BIT(0)
124+
/* this flags is used for dual bank devices only, it indicates if the
125+
* 4 WRPxx are usable if the device is configured in single-bank mode */
126+
#define F_USE_ALL_WRPXX BIT(1)
127+
/* this flag indicates if the device embeds a TrustZone security feature */
128+
#define F_HAS_TZ BIT(2)
129+
/* end of STM32L4 flags ******************************************************/
130+
131+
119132
enum stm32l4_flash_reg_index {
120133
STM32_FLASH_ACR_INDEX,
121134
STM32_FLASH_KEYR_INDEX,
@@ -167,10 +180,7 @@ struct stm32l4_part_info {
167180
const struct stm32l4_rev *revs;
168181
const size_t num_revs;
169182
const uint16_t max_flash_size_kb;
170-
const bool has_dual_bank;
171-
/* this field is used for dual bank devices only, it indicates if the
172-
* 4 WRPxx are usable if the device is configured in single-bank mode */
173-
const bool use_all_wrpxx;
183+
const uint32_t flags; /* one bit per feature, see STM32L4 flags: macros F_XXX */
174184
const uint32_t flash_regs_base;
175185
const uint32_t *default_flash_regs;
176186
const uint32_t fsize_addr;
@@ -280,8 +290,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
280290
.num_revs = ARRAY_SIZE(stm32_415_revs),
281291
.device_str = "STM32L47/L48xx",
282292
.max_flash_size_kb = 1024,
283-
.has_dual_bank = true,
284-
.use_all_wrpxx = false,
293+
.flags = F_HAS_DUAL_BANK,
285294
.flash_regs_base = 0x40022000,
286295
.default_flash_regs = stm32l4_flash_regs,
287296
.fsize_addr = 0x1FFF75E0,
@@ -294,8 +303,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
294303
.num_revs = ARRAY_SIZE(stm32_435_revs),
295304
.device_str = "STM32L43/L44xx",
296305
.max_flash_size_kb = 256,
297-
.has_dual_bank = false,
298-
.use_all_wrpxx = false,
306+
.flags = F_NONE,
299307
.flash_regs_base = 0x40022000,
300308
.default_flash_regs = stm32l4_flash_regs,
301309
.fsize_addr = 0x1FFF75E0,
@@ -308,8 +316,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
308316
.num_revs = ARRAY_SIZE(stm32_460_revs),
309317
.device_str = "STM32G07/G08xx",
310318
.max_flash_size_kb = 128,
311-
.has_dual_bank = false,
312-
.use_all_wrpxx = false,
319+
.flags = F_NONE,
313320
.flash_regs_base = 0x40022000,
314321
.default_flash_regs = stm32l4_flash_regs,
315322
.fsize_addr = 0x1FFF75E0,
@@ -322,8 +329,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
322329
.num_revs = ARRAY_SIZE(stm32_461_revs),
323330
.device_str = "STM32L49/L4Axx",
324331
.max_flash_size_kb = 1024,
325-
.has_dual_bank = true,
326-
.use_all_wrpxx = false,
332+
.flags = F_HAS_DUAL_BANK,
327333
.flash_regs_base = 0x40022000,
328334
.default_flash_regs = stm32l4_flash_regs,
329335
.fsize_addr = 0x1FFF75E0,
@@ -336,8 +342,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
336342
.num_revs = ARRAY_SIZE(stm32_462_revs),
337343
.device_str = "STM32L45/L46xx",
338344
.max_flash_size_kb = 512,
339-
.has_dual_bank = false,
340-
.use_all_wrpxx = false,
345+
.flags = F_NONE,
341346
.flash_regs_base = 0x40022000,
342347
.default_flash_regs = stm32l4_flash_regs,
343348
.fsize_addr = 0x1FFF75E0,
@@ -350,8 +355,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
350355
.num_revs = ARRAY_SIZE(stm32_464_revs),
351356
.device_str = "STM32L41/L42xx",
352357
.max_flash_size_kb = 128,
353-
.has_dual_bank = false,
354-
.use_all_wrpxx = false,
358+
.flags = F_NONE,
355359
.flash_regs_base = 0x40022000,
356360
.default_flash_regs = stm32l4_flash_regs,
357361
.fsize_addr = 0x1FFF75E0,
@@ -364,8 +368,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
364368
.num_revs = ARRAY_SIZE(stm32_466_revs),
365369
.device_str = "STM32G03/G04xx",
366370
.max_flash_size_kb = 64,
367-
.has_dual_bank = false,
368-
.use_all_wrpxx = false,
371+
.flags = F_NONE,
369372
.flash_regs_base = 0x40022000,
370373
.default_flash_regs = stm32l4_flash_regs,
371374
.fsize_addr = 0x1FFF75E0,
@@ -378,8 +381,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
378381
.num_revs = ARRAY_SIZE(stm32_468_revs),
379382
.device_str = "STM32G43/G44xx",
380383
.max_flash_size_kb = 128,
381-
.has_dual_bank = false,
382-
.use_all_wrpxx = false,
384+
.flags = F_NONE,
383385
.flash_regs_base = 0x40022000,
384386
.default_flash_regs = stm32l4_flash_regs,
385387
.fsize_addr = 0x1FFF75E0,
@@ -392,8 +394,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
392394
.num_revs = ARRAY_SIZE(stm32_469_revs),
393395
.device_str = "STM32G47/G48xx",
394396
.max_flash_size_kb = 512,
395-
.has_dual_bank = true,
396-
.use_all_wrpxx = true,
397+
.flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
397398
.flash_regs_base = 0x40022000,
398399
.default_flash_regs = stm32l4_flash_regs,
399400
.fsize_addr = 0x1FFF75E0,
@@ -406,8 +407,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
406407
.num_revs = ARRAY_SIZE(stm32_470_revs),
407408
.device_str = "STM32L4R/L4Sxx",
408409
.max_flash_size_kb = 2048,
409-
.has_dual_bank = true,
410-
.use_all_wrpxx = true,
410+
.flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
411411
.flash_regs_base = 0x40022000,
412412
.default_flash_regs = stm32l4_flash_regs,
413413
.fsize_addr = 0x1FFF75E0,
@@ -420,8 +420,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
420420
.num_revs = ARRAY_SIZE(stm32_471_revs),
421421
.device_str = "STM32L4P5/L4Q5x",
422422
.max_flash_size_kb = 1024,
423-
.has_dual_bank = true,
424-
.use_all_wrpxx = true,
423+
.flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
425424
.flash_regs_base = 0x40022000,
426425
.default_flash_regs = stm32l4_flash_regs,
427426
.fsize_addr = 0x1FFF75E0,
@@ -434,8 +433,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
434433
.num_revs = ARRAY_SIZE(stm32_472_revs),
435434
.device_str = "STM32L55/L56xx",
436435
.max_flash_size_kb = 512,
437-
.has_dual_bank = true,
438-
.use_all_wrpxx = true,
436+
.flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX | F_HAS_TZ,
439437
.flash_regs_base = 0x40022000,
440438
.default_flash_regs = stm32l5_ns_flash_regs,
441439
.fsize_addr = 0x0BFA05E0,
@@ -448,8 +446,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
448446
.num_revs = ARRAY_SIZE(stm32_479_revs),
449447
.device_str = "STM32G49/G4Axx",
450448
.max_flash_size_kb = 512,
451-
.has_dual_bank = false,
452-
.use_all_wrpxx = false,
449+
.flags = F_NONE,
453450
.flash_regs_base = 0x40022000,
454451
.default_flash_regs = stm32l4_flash_regs,
455452
.fsize_addr = 0x1FFF75E0,
@@ -462,8 +459,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
462459
.num_revs = ARRAY_SIZE(stm32_495_revs),
463460
.device_str = "STM32WB5x",
464461
.max_flash_size_kb = 1024,
465-
.has_dual_bank = false,
466-
.use_all_wrpxx = false,
462+
.flags = F_NONE,
467463
.flash_regs_base = 0x58004000,
468464
.default_flash_regs = stm32l4_flash_regs,
469465
.fsize_addr = 0x1FFF75E0,
@@ -476,8 +472,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
476472
.num_revs = ARRAY_SIZE(stm32_496_revs),
477473
.device_str = "STM32WB3x",
478474
.max_flash_size_kb = 512,
479-
.has_dual_bank = false,
480-
.use_all_wrpxx = false,
475+
.flags = F_NONE,
481476
.flash_regs_base = 0x58004000,
482477
.default_flash_regs = stm32l4_flash_regs,
483478
.fsize_addr = 0x1FFF75E0,
@@ -490,8 +485,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
490485
.num_revs = ARRAY_SIZE(stm32_497_revs),
491486
.device_str = "STM32WLEx",
492487
.max_flash_size_kb = 256,
493-
.has_dual_bank = false,
494-
.use_all_wrpxx = false,
488+
.flags = F_NONE,
495489
.flash_regs_base = 0x58004000,
496490
.default_flash_regs = stm32l4_flash_regs,
497491
.fsize_addr = 0x1FFF75E0,
@@ -847,7 +841,7 @@ static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev
847841
return ret;
848842

849843
/* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */
850-
if (stm32l4_info->part_info->use_all_wrpxx && !stm32l4_info->dual_bank_mode)
844+
if ((stm32l4_info->part_info->flags & F_USE_ALL_WRPXX) && !stm32l4_info->dual_bank_mode)
851845
wrp2y_sectors_offset = 0;
852846
}
853847

@@ -1611,7 +1605,7 @@ static int stm32l4_mass_erase(struct flash_bank *bank)
16111605

16121606
uint32_t action = FLASH_MER1;
16131607

1614-
if (stm32l4_info->part_info->has_dual_bank)
1608+
if (stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)
16151609
action |= FLASH_MER2;
16161610

16171611
if (target->state != TARGET_HALTED) {
@@ -1858,7 +1852,7 @@ COMMAND_HANDLER(stm32l4_handle_wrp_info_command)
18581852
}
18591853

18601854
if (dev_bank_id == STM32_BANK2) {
1861-
if (!stm32l4_info->part_info->has_dual_bank) {
1855+
if (!(stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)) {
18621856
LOG_ERROR("this device has no second bank");
18631857
return ERROR_FAIL;
18641858
} else if (!stm32l4_info->dual_bank_mode) {

0 commit comments

Comments
 (0)