SoC: Fix fespi not rerouted to nuspi in openocd 2023.10

see #8

Signed-off-by: Huaqi Fang <[email protected]>

Author: fanghuaqi

SoC/hbird/Board/hbird_eval/openocd_hbird.cfg

@@ -22,14 +22,14 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
 
 set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME nuspi 0x20000000 0 0 0 $_TARGETNAME
 # Set the ILM space also as flash, to make sure it can be add breakpoint with hardware trigger
-#flash bank onboard_ilm fespi 0x80000000 0 0 0 $_TARGETNAME
+#flash bank onboard_ilm nuspi 0x80000000 0 0 0 $_TARGETNAME
 
 # Expose Nuclei self-defined CSRS range 770-800,835-850,1984-2032,2064-2070
 # See https://github.com/riscv/riscv-gnu-toolchain/issues/319#issuecomment-358397306
 # Then user can view the csr register value in gdb using: info reg csr775 for CSR MTVT(0x307)
-riscv expose_csrs 770-800,835-850,1984-2032,2064-2070
+#riscv expose_csrs 770-800,835-850,1984-2032,2064-2070
 
 init
 #reset

SoC/hbirdv2/Board/ddr200t/openocd_hbirdv2.cfg

@@ -22,14 +22,14 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
 
 set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME nuspi 0x20000000 0 0 0 $_TARGETNAME
 # Set the ILM space also as flash, to make sure it can be add breakpoint with hardware trigger
-#flash bank onboard_ilm fespi 0x80000000 0 0 0 $_TARGETNAME
+#flash bank onboard_ilm nuspi 0x80000000 0 0 0 $_TARGETNAME
 
 # Expose Nuclei self-defined CSRS range 770-800,835-850,1984-2032,2064-2070
 # See https://github.com/riscv/riscv-gnu-toolchain/issues/319#issuecomment-358397306
 # Then user can view the csr register value in gdb using: info reg csr775 for CSR MTVT(0x307)
-riscv expose_csrs 770-800,835-850,1984-2032,2064-2070
+#riscv expose_csrs 770-800,835-850,1984-2032,2064-2070
 
 init
 #reset

SoC/hbirdv2/Board/mcu200t/openocd_hbirdv2.cfg

@@ -22,14 +22,14 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
 
 set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME nuspi 0x20000000 0 0 0 $_TARGETNAME
 # Set the ILM space also as flash, to make sure it can be add breakpoint with hardware trigger
-#flash bank onboard_ilm fespi 0x80000000 0 0 0 $_TARGETNAME
+#flash bank onboard_ilm nuspi 0x80000000 0 0 0 $_TARGETNAME
 
 # Expose Nuclei self-defined CSRS range 770-800,835-850,1984-2032,2064-2070
 # See https://github.com/riscv/riscv-gnu-toolchain/issues/319#issuecomment-358397306
 # Then user can view the csr register value in gdb using: info reg csr775 for CSR MTVT(0x307)
-riscv expose_csrs 770-800,835-850,1984-2032,2064-2070
+#riscv expose_csrs 770-800,835-850,1984-2032,2064-2070
 
 init
 #reset