CCxCfg.h

//
// HoneyComm - Alternative RFBee firmware to communicate with
//             HR80 radiator controllers.
//
// Copyright (C) 2011 Wladimir Komarow
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
//

#ifndef CCXCFG_H
#define CCXCFG_H

#include "CCx.h"
#include <avr/pgmspace.h>

#define MAX_PACKET_LENGTH 0x40
#define CCX_NR_OF_REGISTERS 31

// list the registers in the same order as CCxRegisterSettings
// stored in progmem to save on RAM
static const byte CCx_registers[CCX_NR_OF_REGISTERS] PROGMEM = {

      CCx_IOCFG2,
      CCx_IOCFG0,
      CCx_FIFOTHR,
      CCx_SYNC1,
      CCx_SYNC0,
      CCx_PKTLEN,
      CCx_PKTCTRL1,
      CCx_PKTCTRL0,
      CCx_FSCTRL1,
      CCx_FSCTRL0,
      CCx_FREQ2,
      CCx_FREQ1,
      CCx_FREQ0,
      CCx_MDMCFG4,
      CCx_MDMCFG3,
      CCx_MDMCFG2,
      CCx_MDMCFG1,
      CCx_MDMCFG0,
      CCx_DEVIATN,
      CCx_MCSM0,
      CCx_FOCCFG,
      CCx_AGCCTRL2,
      CCx_AGCCTRL1,
      CCx_AGCCTRL0,
      CCx_FSCAL3,
      CCx_FSCAL2,
      CCx_FSCAL1,
      CCx_FSCAL0,
      CCx_TEST2,
      CCx_TEST1,
      CCx_TEST0,
};

#define CCX_NR_OF_CONFIGS 1

// configuration for CC1101 generated by TI's SmartRf studio
// stored in progmem to save on RAM
static const byte CCx_registerSettings[CCX_NR_OF_CONFIGS][CCX_NR_OF_REGISTERS] PROGMEM = {

      {
            0x2E,   // IOCFG2: GDO2 - High impedance (3-state).
            0x06,   // IOCFG0: GDO0 - Asserts when sync word has been received, and de-asserts at the end of the packet. In RX, the pin will also de- assert when a packet is discarded due to address or maximum length filtering or when the radio enters RXFIFO_OVERFLOW state.
            0x00,   // FIFOTHR: RX FIFO threshold at 4 Bytes

            // Preamble of each message is as follows.
            // Note that after the 4x 01010101 there is also a start bit [0] and
            // a stop bit [1] for each byte.
            //
            // 01010101 01010101 01010101 01010101
            // [0]11111111[1] [0]00000000[1] [0]11001100[1] [0]10101010[1] [0]11001010[1]
            //
            // We instruct the CC1101 to sync on the following 16 bits,
            // starting at bit position 8x4 + 4 = 36
            // 11111[1][0]0 0000000[1]

            0xFC,   // SYNC1: Syncword 11111[1][0]0
            0x01,   // SYNC0: Syncword 0000000[1]
            MAX_PACKET_LENGTH,   // PKTLEN:
            0x00,   // PKTCTRL1: Do not append status (RSSI and LQI)
            0x00,   // PKTCTRL0: Fixed packet length (see PKTLEN)
            0x06,   // FSCTRL1   Frequency synthesizer control.
            0x00,   // FSCTRL0   Frequency synthesizer control.
            0x21,   // FREQ2     Frequency control word, high byte.
            0x65,   // FREQ1     Frequency control word, middle byte.
            0xCC,   // FREQ0     Frequency control word, low byte.
            0x6A,   // MDMCFG4: Data rate = 38,38 kBaud with 26.0 MHz crystal
            0x83,   // MDMCFG3: Data rate = 38,38 kBaud with 26.0 MHz crystal
            0x16,   // MDMCFG2: 2-FSK, 15/16 + carrier-sense above threshold
            0x02,   // MDMCFG1   Modem configuration.
            0xF8,   // MDMCFG0   Modem configuration.
            0x50,   // DEVIATN   Modem deviation setting (when FSK modulation is enabled).
            0x18,   // MCSM0     Main Radio Control State Machine configuration.
            0x16,   // FOCCFG    Frequency Offset Compensation Configuration.
            0x43,   // AGCCTRL2  AGC control.
            0x40,   // AGCCTRL1  AGC control.
            0x91,   // AGCCTRL0  AGC control.
            0xE9,   // FSCAL3    Frequency synthesizer calibration.
            0x2A,   // FSCAL2    Frequency synthesizer calibration.
            0x00,   // FSCAL1    Frequency synthesizer calibration.
            0x1F,   // FSCAL0    Frequency synthesizer calibration.
            0x81,   // TEST2     Various test settings.
            0x35,   // TEST1     Various test settings.
            0x09,   // TEST0     Various test settings.
      }


};

// PATABLE (dBm output power)

// stored in progmem to save on RAM
static const byte CCx_paTable[CCX_NR_OF_CONFIGS][CCx_PA_TABLESIZE] PROGMEM ={
      // -30  -20   -15  -10    0   5    7   10
      {
            0x03,0x0E,0x1E,0x27,0x8E,0xCD,0xC7,0xC0      }
};

#endif