Merge branch 'release/v0.2.0' into main

Author: thejpster

CHANGELOG.md

@@ -0,0 +1,13 @@
+# Changelog
+
+## Unreleased Changes
+
+## v0.2.0
+
+Uses `rp2040_boot2` crate for the bootloader.
+
+## v0.1.0
+
+As released in the twitch.tv stream.
+
+

Cargo.toml

@@ -1,8 +1,10 @@
 [package]
 name = "pico-blink-rs"
-version = "0.1.0"
+version = "0.2.0"
 authors = ["Jonathan 'theJPster' Pallant <[email protected]>"]
 edition = "2018"
+license = "CC0"
+description = "Basic blinky program for the Raspberry Pi Pico"
 
 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
 
@@ -11,6 +13,7 @@ cortex-m = "0.7"
 cortex-m-rt = "0.6.13"
 rp2040-pac = { git = "https://github.com/rp-rs/rp2040-pac", branch="main" }
 panic-halt = "0.2.0"
+rp2040-boot2 = "0.1.0"
 
 # this lets you use `cargo fix`!
 [[bin]]

README.md

@@ -4,15 +4,20 @@ Running Rust code on the Raspberry Pi Pico
 
 ## Booting
 
-The RP2040 has external QSPI flash. There is an internal mask-ROM bootloader which can read the first 256 bytes of external flash and copy it to the top of SRAM (`0x2004_1f00`). This 256 byte block is the 'second stage bootloader'. Its job is to reconfigure the XIP_SSI interface to the right values for the attached QSPI flash chip (the mask ROM has some very conservative defaults which should work with all chips), and configure the XIP so that the QSPI flash appears at address `0x1000_0000` upwards.
+The RP2040 has external QSPI flash. There is an internal mask-ROM bootloader which can read the first 256 bytes of 
+external flash and copy it to the top of SRAM (`0x2004_1f00`). This 256 byte block is the 'second stage bootloader'. 
+Its job is to reconfigure the XIP_SSI interface to the right values for the attached QSPI flash chip (the mask ROM has 
+some very conservative defaults which should work with all chips), and configure the XIP so that the QSPI flash appears 
+at address `0x1000_0000` upwards.
 
-The second stage bootloader then loads the user application once the XIP_SSI configuration is complete. It does this by jumping to `0x1000_0100`, which is 256 bytes into the QSPI flash contents (or immediately after the 256 byte second stage bootloader). We emulate this by storing the second stage bootloader in a static array at the start of our application.
+The second stage bootloader then loads the user application once the XIP_SSI configuration is complete. It does this by 
+reading a vector table at `0x1000_0100`, which is 256 bytes into the QSPI flash contents (or immediately after the 256 
+byte second stage bootloader), and jumping to the reset vector.
 
-The application needs to relocate the vector table using VTOR, then set the stack pointer
-and call the reset function manually. Rather than do that in Rust, currently we copy the first 256 bytes of the "blink" pico-sdk example, which does this for us. Yes, this is ugly. The bootloader should be trimmed back to 256 bytes and some Rust code written which sets up VTOR correctly. Or, we can ask Raspberry Pi Trading to change boot2 to expect a Vector Table at 0x100 instead of a function: see https://github.com/raspberrypi/pico-sdk/pull/10.
-
-We should also write a BSP for the pico, and a HAL for the RP2040. Basically, don't do any of what I did here. But hey, it blinks!
+We should also write a BSP for the pico, and a HAL for the RP2040. Basically, don't do any of what I did here. But hey, 
+it blinks!
 
 ## Licence
 
-This work is licenced under CC0. The bootrom binaries are Copyright Raspberry Pi Trading and build from pico-sdk v1.0.0.
+This work is licenced under CC0. Binaries may include material Copyright Raspberry Pi Trading - see other crates for 
+details.

memory.x

@@ -2,8 +2,8 @@ MEMORY
 {
   /* NOTE 1 K = 1 KiBi = 1024 bytes */
   /* To suit Raspberry Pi RP2040 SoC */
-  BOOT_LOADER : ORIGIN = 0x10000000, LENGTH = 512
-  FLASH : ORIGIN = 0x10000200, LENGTH = 2048K - 512
+  BOOT_LOADER : ORIGIN = 0x10000000, LENGTH = 0x100
+  FLASH : ORIGIN = 0x10000100, LENGTH = 2048K - 0x100
   RAM : ORIGIN = 0x20000000, LENGTH = 256K
 }
 

src/boot2.bin

@@ -1,29 +1,17 @@
 #![no_std]
 #![no_main]
 
-use cortex_m_rt::{entry, pre_init};
+use cortex_m_rt::entry;
 use panic_halt as _;
 
 #[link_section = ".boot_loader"]
-#[no_mangle]
-pub static BOOT_LOADER: [u8; 512] = *include_bytes!("boot2_and_reset.bin");
-
-#[pre_init]
-unsafe fn pre_init() {
-    let sio = &*rp2040_pac::SIO::ptr();
-
-    // If we are core 1, then stop dead and let core 0 do all the work.
-    if sio.cpuid.read().bits() != 0u32 {
-        loop {
-            cortex_m::asm::nop();
-        }
-    }
-}
+#[used]
+pub static BOOT_LOADER: [u8; 256] = rp2040_boot2::BOOT_LOADER;
 
+/// Handle peripheral resets so the chip is usable.
 unsafe fn setup_chip(p: &mut rp2040_pac::Peripherals) {
     // Now reset all the peripherals, except QSPI and XIP (we're using those
     // to execute from external flash!)
-
     p.RESETS.reset.write(|w| {
         w.adc().set_bit();
         w.busctrl().set_bit();
@@ -53,16 +41,6 @@ unsafe fn setup_chip(p: &mut rp2040_pac::Peripherals) {
         w
     });
 
-    // unreset_block_wait(RESETS_RESET_BITS /* 01ff_ffff */ & ~(
-    //         RESETS_RESET_ADC_BITS |
-    //         RESETS_RESET_RTC_BITS |
-    //         RESETS_RESET_SPI0_BITS |
-    //         RESETS_RESET_SPI1_BITS |
-    //         RESETS_RESET_UART0_BITS |
-    //         RESETS_RESET_UART1_BITS |
-    //         RESETS_RESET_USBCTRL_BITS
-    // ));
-
     const RESETS_RESET_BITS: u32 = 0x01ffffff;
     const RESETS_RESET_USBCTRL_BITS: u32 = 0x01000000;
     const RESETS_RESET_UART1_BITS: u32 = 0x00800000;
@@ -72,6 +50,17 @@ unsafe fn setup_chip(p: &mut rp2040_pac::Peripherals) {
     const RESETS_RESET_RTC_BITS: u32 = 0x00008000;
     const RESETS_RESET_ADC_BITS: u32 = 0x00000001;
 
+    // We want to take everything out of reset, except these peripherals:
+    //
+    // * ADC
+    // * RTC
+    // * SPI0
+    // * SPI1
+    // * UART0
+    // * UART1
+    // * USBCTRL
+    //
+    // These must stay in reset until the clocks are sorted out.
     const PERIPHERALS_TO_UNRESET: u32 = RESETS_RESET_BITS
         & !(RESETS_RESET_ADC_BITS
             | RESETS_RESET_RTC_BITS
@@ -81,8 +70,8 @@ unsafe fn setup_chip(p: &mut rp2040_pac::Peripherals) {
             | RESETS_RESET_UART1_BITS
             | RESETS_RESET_USBCTRL_BITS);
 
+    // Write 0 to the reset field to take it out of reset
     p.RESETS.reset.modify(|_r, w| {
-        // w.adc().clear_bit();
         w.busctrl().clear_bit();
         w.dma().clear_bit();
         w.i2c0().clear_bit();
@@ -97,16 +86,10 @@ unsafe fn setup_chip(p: &mut rp2040_pac::Peripherals) {
         w.pll_sys().clear_bit();
         w.pll_usb().clear_bit();
         w.pwm().clear_bit();
-        // w.rtc().clear_bit();
-        // w.spi0().clear_bit();
-        // w.spi1().clear_bit();
         w.syscfg().clear_bit();
         w.sysinfo().clear_bit();
         w.tbman().clear_bit();
         w.timer().clear_bit();
-        // w.uart0().clear_bit();
-        // w.uart1().clear_bit();
-        // w.usbctrl().clear_bit();
         w
     });
 
@@ -156,7 +139,7 @@ fn main() -> ! {
     });
 
     loop {
-        for _i in 0..1000000 {
+        for _i in 0..500000 {
             cortex_m::asm::nop();
         }
 
@@ -166,7 +149,7 @@ fn main() -> ! {
             w
         });
 
-        for _i in 0..1000000 {
+        for _i in 0..500000 {
             cortex_m::asm::nop();
         }