First version. It blinks!

Author: thejpster

.cargo/config

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+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+# uncomment ONE of these three option to make `cargo run` start a GDB session
+# which option to pick depends on your system
+# runner = "arm-none-eabi-gdb -q -x openocd.gdb"
+# runner = "gdb-multiarch -q -x openocd.gdb"
+# runner = "gdb -q -x openocd.gdb"
+
+rustflags = [
+  # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x
+  # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95
+  "-C", "link-arg=--nmagic",
+
+  # LLD (shipped with the Rust toolchain) is used as the default linker
+  "-C", "link-arg=-Tlink.x",
+
+  # if you run into problems with LLD switch to the GNU linker by commenting out
+  # this line
+  # "-C", "linker=arm-none-eabi-ld",
+
+  # if you need to link to pre-compiled C libraries provided by a C toolchain
+  # use GCC as the linker by commenting out both lines above and then
+  # uncommenting the three lines below
+  # "-C", "linker=arm-none-eabi-gcc",
+  # "-C", "link-arg=-Wl,-Tlink.x",
+  # "-C", "link-arg=-nostartfiles",
+]
+
+[build]
+# Pick ONE of these compilation targets
+target = "thumbv6m-none-eabi"        # Cortex-M0 and Cortex-M0+
+# target = "thumbv7m-none-eabi"        # Cortex-M3
+# target = "thumbv7em-none-eabi"       # Cortex-M4 and Cortex-M7 (no FPU)
+# target = "thumbv7em-none-eabihf"     # Cortex-M4F and Cortex-M7F (with FPU)
+# target = "thumbv8m.base-none-eabi"   # Cortex-M23
+# target = "thumbv8m.main-none-eabi"   # Cortex-M33 (no FPU)
+# target = "thumbv8m.main-none-eabihf" # Cortex-M33 (with FPU)

.gitignore

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+/target

Cargo.toml

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+[package]
+name = "pico-blink-rs"
+version = "0.1.0"
+authors = ["Jonathan 'theJPster' Pallant <[email protected]>"]
+edition = "2018"
+
+# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
+
+[dependencies]
+cortex-m = "0.7"
+cortex-m-rt = "0.6.13"
+rp2040-pac = { path = "../rp2040-pac" }
+panic-halt = "0.2.0"
+
+# this lets you use `cargo fix`!
+[[bin]]
+name = "pico-blink-rs"
+test = false
+bench = false
+
+[profile.release]
+codegen-units = 1 # better optimizations
+debug = true # symbols are nice and they don't increase the size on Flash
+lto = true # better optimizations

README.md

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+# pico-blink-rs
+
+Running Rust code on the Raspberry Pi Pico
+
+## Booting
+
+The RP2040 has external QSPI flash. There is an internal mask-ROM bootloader which can read the first 256 bytes of external flash and copy it to the top of SRAM (`0x2004_1f00`). This 256 byte block is the 'second stage bootloader'. Its job is to reconfigure the XIP_SSI interface to the right values for the attached QSPI flash chip (the mask ROM has some very conservative defaults which should work with all chips), and configure the XIP so that the QSPI flash appears at address `0x1000_0000` upwards.
+
+The second stage bootloader then loads the user application once the XIP_SSI configuration is complete. It does this by jumping to `0x1000_0100`, which is 256 bytes into the QSPI flash contents (or immediately after the 256 byte second stage bootloader).
+
+## Licence
+
+This work is licenced under CC0.

build.rs

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+//! This build script copies the `memory.x` file from the crate root into
+//! a directory where the linker can always find it at build time.
+//! For many projects this is optional, as the linker always searches the
+//! project root directory -- wherever `Cargo.toml` is. However, if you
+//! are using a workspace or have a more complicated build setup, this
+//! build script becomes required. Additionally, by requesting that
+//! Cargo re-run the build script whenever `memory.x` is changed,
+//! updating `memory.x` ensures a rebuild of the application with the
+//! new memory settings.
+
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+
+fn main() {
+    // Put `memory.x` in our output directory and ensure it's
+    // on the linker search path.
+    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    File::create(out.join("memory.x"))
+        .unwrap()
+        .write_all(include_bytes!("memory.x"))
+        .unwrap();
+    println!("cargo:rustc-link-search={}", out.display());
+
+    // By default, Cargo will re-run a build script whenever
+    // any file in the project changes. By specifying `memory.x`
+    // here, we ensure the build script is only re-run when
+    // `memory.x` is changed.
+    println!("cargo:rerun-if-changed=memory.x");
+}

memory.x

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+MEMORY
+{
+  /* NOTE 1 K = 1 KiBi = 1024 bytes */
+  /* To suit Raspberry Pi RP2040 SoC */
+  BOOT_LOADER : ORIGIN = 0x10000000, LENGTH = 512
+  FLASH : ORIGIN = 0x10000200, LENGTH = 2048K - 512
+  RAM : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+SECTIONS {
+
+  /* ### Boot loader */
+  .boot_loader ORIGIN(BOOT_LOADER) :
+  {
+    KEEP(*(.boot_loader*));
+  } > BOOT_LOADER
+
+} INSERT BEFORE .text;

src/boot2.bin

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+#![no_std]
+#![no_main]
+
+use cortex_m_rt::{entry, pre_init};
+use panic_halt as _;
+
+#[link_section = ".boot_loader"]
+#[no_mangle]
+pub static BOOT_LOADER: [u8; 512] = *include_bytes!("boot2_and_reset.bin");
+
+#[pre_init]
+unsafe fn pre_init() {
+    let sio = &*rp2040_pac::SIO::ptr();
+
+    // If we are core 1, then stop dead and let core 0 do all the work.
+    if sio.cpuid.read() != 0u32 {
+        loop {
+            cortex_m::asm::nop();
+        }
+    }
+}
+
+unsafe fn setup_chip(p: &mut rp2040_pac::Peripherals) {
+    // Now reset all the peripherals, except QSPI and XIP (we're using those
+    // to execute from external flash!)
+
+    p.RESETS.reset.write(|w| {
+        w.adc().set_bit();
+        w.busctrl().set_bit();
+        w.dma().set_bit();
+        w.i2c0().set_bit();
+        w.i2c1().set_bit();
+        w.io_bank0().set_bit();
+        w.io_qspi().clear_bit();
+        w.jtag().set_bit();
+        w.pads_bank0().set_bit();
+        w.pads_qspi().clear_bit();
+        w.pio0().set_bit();
+        w.pio1().set_bit();
+        w.pll_sys().clear_bit();
+        w.pll_usb().clear_bit();
+        w.pwm().set_bit();
+        w.rtc().set_bit();
+        w.spi0().set_bit();
+        w.spi1().set_bit();
+        w.syscfg().set_bit();
+        w.sysinfo().set_bit();
+        w.tbman().set_bit();
+        w.timer().set_bit();
+        w.uart0().set_bit();
+        w.uart1().set_bit();
+        w.usbctrl().set_bit();
+        w
+    });
+
+    // unreset_block_wait(RESETS_RESET_BITS /* 01ff_ffff */ & ~(
+    //         RESETS_RESET_ADC_BITS |
+    //         RESETS_RESET_RTC_BITS |
+    //         RESETS_RESET_SPI0_BITS |
+    //         RESETS_RESET_SPI1_BITS |
+    //         RESETS_RESET_UART0_BITS |
+    //         RESETS_RESET_UART1_BITS |
+    //         RESETS_RESET_USBCTRL_BITS
+    // ));
+
+    const RESETS_RESET_BITS: u32 = 0x01ffffff;
+    const RESETS_RESET_USBCTRL_BITS: u32 = 0x01000000;
+    const RESETS_RESET_UART1_BITS: u32 = 0x00800000;
+    const RESETS_RESET_UART0_BITS: u32 = 0x00400000;
+    const RESETS_RESET_SPI1_BITS: u32 = 0x00020000;
+    const RESETS_RESET_SPI0_BITS: u32 = 0x00010000;
+    const RESETS_RESET_RTC_BITS: u32 = 0x00008000;
+    const RESETS_RESET_ADC_BITS: u32 = 0x00000001;
+
+    const PERIPHERALS_TO_UNRESET: u32 = RESETS_RESET_BITS
+        & !(RESETS_RESET_ADC_BITS
+            | RESETS_RESET_RTC_BITS
+            | RESETS_RESET_SPI0_BITS
+            | RESETS_RESET_SPI1_BITS
+            | RESETS_RESET_UART0_BITS
+            | RESETS_RESET_UART1_BITS
+            | RESETS_RESET_USBCTRL_BITS);
+
+    p.RESETS.reset.modify(|_r, w| {
+        // w.adc().clear_bit();
+        w.busctrl().clear_bit();
+        w.dma().clear_bit();
+        w.i2c0().clear_bit();
+        w.i2c1().clear_bit();
+        w.io_bank0().clear_bit();
+        w.io_qspi().clear_bit();
+        w.jtag().clear_bit();
+        w.pads_bank0().clear_bit();
+        w.pads_qspi().clear_bit();
+        w.pio0().clear_bit();
+        w.pio1().clear_bit();
+        w.pll_sys().clear_bit();
+        w.pll_usb().clear_bit();
+        w.pwm().clear_bit();
+        // w.rtc().clear_bit();
+        // w.spi0().clear_bit();
+        // w.spi1().clear_bit();
+        w.syscfg().clear_bit();
+        w.sysinfo().clear_bit();
+        w.tbman().clear_bit();
+        w.timer().clear_bit();
+        // w.uart0().clear_bit();
+        // w.uart1().clear_bit();
+        // w.usbctrl().clear_bit();
+        w
+    });
+
+    while (!p.RESETS.reset_done.read().bits() & PERIPHERALS_TO_UNRESET) != 0 {
+        cortex_m::asm::nop();
+    }
+}
+
+#[entry]
+fn main() -> ! {
+    let mut p = rp2040_pac::Peripherals::take().unwrap();
+
+    unsafe {
+        setup_chip(&mut p);
+    }
+
+    // Set GPIO25 to be an input (output enable is cleared)
+    p.SIO.gpio_oe_clr.write(|w| unsafe {
+        w.bits(1 << 25);
+        w
+    });
+
+    // Set GPIO25 to be an output low (output is cleared)
+    p.SIO.gpio_out_clr.write(|w| unsafe {
+        w.bits(1 << 25);
+        w
+    });
+
+    // Configure pin 25 for GPIO
+    p.PADS_BANK0.gpio25.write(|w| {
+        // Output Disable off
+        w.od().clear_bit();
+        // Input Enable on
+        w.ie().set_bit();
+        w
+    });
+    p.IO_BANK0.gpio25_ctrl.write(|w| {
+        // Map pin 25 to SIO
+        w.funcsel().sio_25();
+        w
+    });
+
+    // Set GPIO25 to be an output (output enable is set)
+    p.SIO.gpio_oe_set.write(|w| unsafe {
+        w.bits(1 << 25);
+        w
+    });
+
+    loop {
+        for _i in 0..1000000 {
+            cortex_m::asm::nop();
+        }
+
+        // Set GPIO25 to be low
+        p.SIO.gpio_out_clr.write(|w| unsafe {
+            w.bits(1 << 25);
+            w
+        });
+
+        for _i in 0..1000000 {
+            cortex_m::asm::nop();
+        }
+
+        // Set GPIO25 to be high
+        p.SIO.gpio_out_set.write(|w| unsafe {
+            w.bits(1 << 25);
+            w
+        });
+    }
+}