Fix expected outputs, and prefer hex to decimal.

Author: thejpster

examples/mps3-an536/reference/registers-armv8r-none-eabihf.out

@@ -1,7 +1,7 @@
 MIDR { implementer=0x41 variant=0x1 arch=0xf part_no=0xd13 rev=0x3 }
 CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
 IMP_CBAR { 0xf0000000 }
-VBAR { 0x08000000 }
+Vbar(8000000)
 PMSA-v8 MPUIR: Mpuir { iregions: 0, dregions: 16, non_unified: false }
 Region 0: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
 Region 1: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }

examples/mps3-an536/src/bin/registers.rs

@@ -22,12 +22,12 @@ fn main() -> ! {
 }
 
 fn chip_info() {
-    println!("{:?}", aarch32_cpu::register::Midr::read());
-    println!("{:?}", aarch32_cpu::register::Cpsr::read());
+    println!("{:x?}", aarch32_cpu::register::Midr::read());
+    println!("{:x?}", aarch32_cpu::register::Cpsr::read());
     #[cfg(arm_architecture = "v8-r")]
     {
-        println!("{:?}", aarch32_cpu::register::ImpCbar::read());
-        println!("{:?}", aarch32_cpu::register::Vbar::read());
+        println!("{:x?}", aarch32_cpu::register::ImpCbar::read());
+        println!("{:x?}", aarch32_cpu::register::Vbar::read());
         // This only works in EL2 and start-up put us in EL1
         // println!("{:?}", aarch32_cpu::register::Hvbar::read());
     }

examples/versatileab/reference/registers-armv4t-none-eabi.out

@@ -1,5 +1,5 @@
 MIDR { implementer=0x69 variant=0x0 arch=0x5 part_no=0x210 rev=0x0 }
 CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
-Mpidr(1761943808)
+Mpidr(69052100)
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after

examples/versatileab/reference/registers-armv5te-none-eabi.out

@@ -1,5 +1,5 @@
 MIDR { implementer=0x41 variant=0x0 arch=0x6 part_no=0x926 rev=0x5 }
 CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
-Mpidr(1090949733)
+Mpidr(41069265)
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after

examples/versatileab/reference/registers-armv7r-none-eabi.out

@@ -1,6 +1,6 @@
 MIDR { implementer=0x41 variant=0x1 arch=0xf part_no=0xc15 rev=0x3 }
 CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
-Mpidr(3221225472)
+Mpidr(c0000000)
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
 PMSA-v7 MPUIR: Mpuir { iregions: 0, dregions: 16, non_unified: false }

examples/versatileab/reference/registers-armv7r-none-eabihf.out

@@ -1,6 +1,6 @@
 MIDR { implementer=0x41 variant=0x1 arch=0xf part_no=0xc15 rev=0x3 }
 CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
-Mpidr(3221225472)
+Mpidr(c0000000)
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
 PMSA-v7 MPUIR: Mpuir { iregions: 0, dregions: 16, non_unified: false }

examples/versatileab/src/bin/registers.rs

@@ -20,9 +20,9 @@ fn main() -> ! {
 }
 
 fn chip_info() {
-    println!("{:?}", aarch32_cpu::register::Midr::read());
-    println!("{:?}", aarch32_cpu::register::Cpsr::read());
-    println!("{:?}", aarch32_cpu::register::Mpidr::read());
+    println!("{:x?}", aarch32_cpu::register::Midr::read());
+    println!("{:x?}", aarch32_cpu::register::Cpsr::read());
+    println!("{:x?}", aarch32_cpu::register::Mpidr::read());
 }
 
 #[cfg(arm_architecture = "v7-r")]