|
1 |
| -[](https://crates.io/crates/cortex-a) |
2 |
| -[](https://crates.io/crates/cortex-a) |
| 1 | +# Deprecation Notice |
3 | 2 |
|
4 |
| -# cortex-a |
| 3 | +This crate has been renamed to `aarch64-cpu`. Please find it at |
| 4 | +- https://github.com/rust-embedded/aarch64-cpu |
| 5 | +- https://crates.io/crates/aarch64-cpu |
5 | 6 |
|
6 |
| -Low level access to Cortex-A processors. |
| 7 | +Version `8.1.1` will be the last version of this crate and has been added to get this message out. |
| 8 | +To keep the version history sane, the first version of `aarch64-cpu` starts at `9.0.0`. |
7 | 9 |
|
8 |
| -## Currently Supported Execution States |
9 |
| - |
10 |
| -- [x] AArch64 |
11 |
| -- [ ] AArch32 |
12 |
| - |
13 |
| -## Minimum Supported Rust Version |
14 |
| - |
15 |
| -Requires a recent nightly of Rust if the (default) `nightly` feature is enabled. Without this the |
16 |
| -register access module is not available. |
17 |
| - |
18 |
| -## Usage |
19 |
| - |
20 |
| -Please note that for using this crate's [register definitions](src/registers) (as provided by |
21 |
| -`cortex_a::registers::*`), you need to also include |
22 |
| -[`tock-registers`](https://crates.io/crates/tock-registers) in your project. This is because the |
23 |
| -`interface` traits provided by `tock-registers` are implemented by this crate. You should include |
24 |
| -the same version of `tock-registers` as is being used by this crate to ensure sane |
25 |
| -interoperatbility. |
26 |
| - |
27 |
| -For example, in the following snippet, `X.Y.Z` should be the same version of `tock-registers` that |
28 |
| -is mentioned in `cortex-a`'s [`Cargo.toml`](Cargo.toml#L27). |
29 |
| - |
30 |
| -```toml |
31 |
| -[package] |
32 |
| -name = "Your embedded project" |
33 |
| - |
34 |
| -# Some parts omitted for brevity. |
35 |
| - |
36 |
| -[dependencies] |
37 |
| -tock-registers = "X.Y.Z" |
38 |
| -cortex-a = "A.B.C" # <-- Includes tock-registers itself. |
39 |
| -``` |
40 |
| - |
41 |
| -### Example |
42 |
| - |
43 |
| -Check out https://github.com/rust-embedded/rust-raspberrypi-OS-tutorials for usage examples. Listed |
44 |
| -below is a snippet of `rust-raspberrypi-OS-tutorials`'s early boot code. |
45 |
| - |
46 |
| -```rust |
47 |
| -use cortex_a::{asm, registers::*}; |
48 |
| -use tock_registers::interfaces::Writeable; // <-- Trait needed to use `write()` and `set()`. |
49 |
| - |
50 |
| -// Some parts omitted for brevity. |
51 |
| - |
52 |
| -unsafe fn prepare_el2_to_el1_transition( |
53 |
| - virt_boot_core_stack_end_exclusive_addr: u64, |
54 |
| - virt_kernel_init_addr: u64, |
55 |
| -) { |
56 |
| - // Enable timer counter registers for EL1. |
57 |
| - CNTHCTL_EL2.write(CNTHCTL_EL2::EL1PCEN::SET + CNTHCTL_EL2::EL1PCTEN::SET); |
58 |
| - |
59 |
| - // No offset for reading the counters. |
60 |
| - CNTVOFF_EL2.set(0); |
61 |
| - |
62 |
| - // Set EL1 execution state to AArch64. |
63 |
| - HCR_EL2.write(HCR_EL2::RW::EL1IsAarch64); |
64 |
| - |
65 |
| - // Set up a simulated exception return. |
66 |
| - SPSR_EL2.write( |
67 |
| - SPSR_EL2::D::Masked |
68 |
| - + SPSR_EL2::A::Masked |
69 |
| - + SPSR_EL2::I::Masked |
70 |
| - + SPSR_EL2::F::Masked |
71 |
| - + SPSR_EL2::M::EL1h, |
72 |
| - ); |
73 |
| -``` |
74 |
| - |
75 |
| -## Disclaimer |
76 |
| - |
77 |
| -Descriptive comments in the source files are taken from the |
78 |
| -[ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile](https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf?_ga=2.266626254.1122218691.1534883460-1326731866.1530967873). |
79 |
| - |
80 |
| -## License |
81 |
| - |
82 |
| -Licensed under either of |
83 |
| - |
84 |
| -- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or |
85 |
| - http://www.apache.org/licenses/LICENSE-2.0) |
86 |
| -- MIT License ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT) |
87 |
| - |
88 |
| -at your option. |
89 |
| - |
90 |
| -### Contribution |
91 |
| - |
92 |
| -Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the |
93 |
| -work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any |
94 |
| -additional terms or conditions. |
| 10 | +Thanks! |
0 commit comments