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Merge branch 'master' into fix/pwm-channel-by-ref
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CHANGELOG.md

+7-1
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@@ -12,6 +12,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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### Changed
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- Swap PWM channel arguments to references
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## [v1.0.0-alpha.4] - 2020-11-11
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### Fixed
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- Support for I2C addressing modes in `Transactional` I2C traits.
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## [v1.0.0-alpha.3] - 2020-11-04
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### Added
@@ -146,7 +151,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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Initial release
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[Unreleased]: https://github.com/rust-embedded/embedded-hal/compare/v1.0.0-alpha.3...HEAD
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[Unreleased]: https://github.com/rust-embedded/embedded-hal/compare/v1.0.0-alpha.4...HEAD
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[v1.0.0-alpha.4]: https://github.com/rust-embedded/embedded-hal/compare/v1.0.0-alpha.3...v1.0.0-alpha.4
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[v1.0.0-alpha.3]: https://github.com/rust-embedded/embedded-hal/compare/v1.0.0-alpha.2...v1.0.0-alpha.3
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[v1.0.0-alpha.2]: https://github.com/rust-embedded/embedded-hal/compare/v1.0.0-alpha.1...v1.0.0-alpha.2
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[v1.0.0-alpha.1]: https://github.com/rust-embedded/embedded-hal/compare/v0.2.3...v1.0.0-alpha.1

Cargo.toml

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@@ -13,7 +13,7 @@ license = "MIT OR Apache-2.0"
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name = "embedded-hal"
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readme = "README.md"
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repository = "https://github.com/rust-embedded/embedded-hal"
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version = "1.0.0-alpha.3"
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version = "1.0.0-alpha.4" # remember to update html_root_url
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[dependencies]
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nb = "1"

src/blocking/i2c.rs

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@@ -247,7 +247,7 @@ pub enum Operation<'a> {
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/// Transactional I2C interface.
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///
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/// This allows combining operations within an I2C transaction.
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pub trait Transactional {
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pub trait Transactional<A: AddressMode = SevenBitAddress> {
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/// Error type
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type Error;
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@@ -266,15 +266,15 @@ pub trait Transactional {
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/// - `SP` = stop condition
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fn try_exec<'a>(
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&mut self,
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address: u8,
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address: A,
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operations: &mut [Operation<'a>],
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) -> Result<(), Self::Error>;
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}
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/// Transactional I2C interface (iterator version).
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///
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/// This allows combining operation within an I2C transaction.
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pub trait TransactionalIter {
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pub trait TransactionalIter<A: AddressMode = SevenBitAddress> {
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/// Error type
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type Error;
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@@ -291,51 +291,85 @@ pub trait TransactionalIter {
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/// - `SAD+R/W` = slave address followed by bit 1 to indicate reading or 0 to indicate writing
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/// - `SR` = repeated start condition
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/// - `SP` = stop condition
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fn try_exec_iter<'a, O>(&mut self, address: u8, operations: O) -> Result<(), Self::Error>
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fn try_exec_iter<'a, O>(&mut self, address: A, operations: O) -> Result<(), Self::Error>
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where
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O: IntoIterator<Item = Operation<'a>>;
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}
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/// Default implementation of `blocking::i2c::Write`, `blocking::i2c::Read` and
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/// `blocking::i2c::WriteRead` traits for `blocking::i2c::Transactional` implementers.
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///
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/// If you implement `blocking::i2c::Transactional` for your I2C peripheral,
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/// you can use this default implementation so that you do not need to implement
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/// the `blocking::i2c::Write`, `blocking::i2c::Read` and `blocking::i2c::WriteRead`
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/// traits as well.
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/// ```
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/// use embedded_hal::blocking::i2c;
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///
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/// struct I2c1;
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///
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/// impl i2c::Transactional<i2c::SevenBitAddress> for I2c1 {
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/// # type Error = ();
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/// fn try_exec<'a>(
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/// &mut self,
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/// address: i2c::SevenBitAddress,
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/// operations: &mut [i2c::Operation<'a>],
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/// ) -> Result<(), Self::Error> {
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/// // ...
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/// # Ok(())
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/// }
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/// }
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///
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/// // This is all you need to do:
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/// impl i2c::transactional::Default<i2c::SevenBitAddress> for I2c1 {};
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///
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/// // Then you can use `Write` and so on:
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/// use i2c::Write;
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///
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/// let mut i2c1 = I2c1{};
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/// i2c1.try_write(0x01, &[0xAB, 0xCD]).unwrap();
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/// ```
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pub mod transactional {
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use super::{Operation, Read, Transactional, Write, WriteRead};
333+
use super::{AddressMode, Operation, Read, Transactional, Write, WriteRead};
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/// Default implementation of `blocking::i2c::Write`, `blocking::i2c::Read` and
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/// `blocking::i2c::WriteRead` traits for `blocking::i2c::Transactional` implementers.
306-
pub trait Default<E> {}
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pub trait Default<A: AddressMode>: Transactional<A> {}
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308-
impl<E, S> Write for S
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impl<A, E, S> Write<A> for S
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where
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S: self::Default<E> + Transactional<Error = E>,
341+
A: AddressMode,
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S: self::Default<A> + Transactional<A, Error = E>,
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{
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type Error = E;
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314-
fn try_write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Self::Error> {
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fn try_write(&mut self, address: A, bytes: &[u8]) -> Result<(), Self::Error> {
315347
self.try_exec(address, &mut [Operation::Write(bytes)])
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}
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}
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319-
impl<E, S> Read for S
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impl<A, E, S> Read<A> for S
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where
321-
S: self::Default<E> + Transactional<Error = E>,
353+
A: AddressMode,
354+
S: self::Default<A> + Transactional<A, Error = E>,
322355
{
323356
type Error = E;
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325-
fn try_read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
358+
fn try_read(&mut self, address: A, buffer: &mut [u8]) -> Result<(), Self::Error> {
326359
self.try_exec(address, &mut [Operation::Read(buffer)])
327360
}
328361
}
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330-
impl<E, S> WriteRead for S
363+
impl<A, E, S> WriteRead<A> for S
331364
where
332-
S: self::Default<E> + Transactional<Error = E>,
365+
A: AddressMode,
366+
S: self::Default<A> + Transactional<A, Error = E>,
333367
{
334368
type Error = E;
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336370
fn try_write_read(
337371
&mut self,
338-
address: u8,
372+
address: A,
339373
bytes: &[u8],
340374
buffer: &mut [u8],
341375
) -> Result<(), Self::Error> {

src/fmt.rs

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@@ -3,7 +3,7 @@
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//! TODO write example of usage
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use core::fmt::{Result, Write};
55

6-
impl<Word, Error> Write for dyn (crate::serial::Write<Word, Error = Error>)
6+
impl<Word, Error> Write for dyn crate::serial::Write<Word, Error = Error> + '_
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where
88
Word: From<u8>,
99
{

src/lib.rs

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@@ -404,6 +404,7 @@
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//! # fn main() {}
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//! ```
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#![doc(html_root_url = "https://docs.rs/embedded-hal/1.0.0-alpha.4")]
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#![deny(missing_docs)]
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#![no_std]
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