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test/CodeGen/AArch64/GlobalISel
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lines changed Original file line number Diff line number Diff line change @@ -1791,7 +1791,7 @@ bool AArch64InstructionSelector::selectVectorAshrLshr(
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NegOpc = AArch64::NEGv8i16;
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} else if (Ty == LLT::vector (16 , 8 )) {
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Opc = IsASHR ? AArch64::SSHLv16i8 : AArch64::USHLv16i8;
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- NegOpc = AArch64::NEGv8i16 ;
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+ NegOpc = AArch64::NEGv16i8 ;
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} else if (Ty == LLT::vector (8 , 8 )) {
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Opc = IsASHR ? AArch64::SSHLv8i8 : AArch64::USHLv8i8;
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NegOpc = AArch64::NEGv8i8;
Original file line number Diff line number Diff line change @@ -562,8 +562,8 @@ body: |
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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- ; CHECK: [[NEGv8i16_ :%[0-9]+]]:fpr128 = NEGv8i16 [[COPY1]]
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- ; CHECK: [[USHLv16i8_:%[0-9]+]]:fpr128 = USHLv16i8 [[COPY]], [[NEGv8i16_ ]]
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+ ; CHECK: [[NEGv16i8_ :%[0-9]+]]:fpr128 = NEGv16i8 [[COPY1]]
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+ ; CHECK: [[USHLv16i8_:%[0-9]+]]:fpr128 = USHLv16i8 [[COPY]], [[NEGv16i8_ ]]
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; CHECK: $q0 = COPY [[USHLv16i8_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<16 x s8>) = COPY $q0
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