From 450fbb580fb06988dab3d081a9e38fe7d793fd86 Mon Sep 17 00:00:00 2001
From: Geoffry Song <goffrie@dropbox.com>
Date: Fri, 11 Jan 2019 11:55:21 -0800
Subject: [PATCH] Avoid clobbering ESP/RSP in the epilogue.

In r345197 ESP and RSP were added to GR32_TC/GR64_TC, allowing them to
be used for tail calls, but this also caused `findDeadCallerSavedReg` to
think they were acceptable targets for clobbering. Filter them out.

Fixes PR40289.
---
 lib/Target/X86/X86FrameLowering.cpp | 3 ++-
 test/CodeGen/X86/pr40289-64bit.ll   | 9 +++++++++
 test/CodeGen/X86/pr40289.ll         | 9 +++++++++
 3 files changed, 20 insertions(+), 1 deletion(-)
 create mode 100644 test/CodeGen/X86/pr40289-64bit.ll
 create mode 100644 test/CodeGen/X86/pr40289.ll

diff --git a/lib/Target/X86/X86FrameLowering.cpp b/lib/Target/X86/X86FrameLowering.cpp
index e40b0f81e330..0cdec053b810 100644
--- a/lib/Target/X86/X86FrameLowering.cpp
+++ b/lib/Target/X86/X86FrameLowering.cpp
@@ -185,7 +185,8 @@ static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
     }
 
     for (auto CS : AvailableRegs)
-      if (!Uses.count(CS) && CS != X86::RIP)
+      if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP &&
+          CS != X86::ESP)
         return CS;
   }
   }
diff --git a/test/CodeGen/X86/pr40289-64bit.ll b/test/CodeGen/X86/pr40289-64bit.ll
new file mode 100644
index 000000000000..43fde78c68f9
--- /dev/null
+++ b/test/CodeGen/X86/pr40289-64bit.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=x86_64-pc-windows-msvc | FileCheck %s
+
+define cc 92 < 9 x i64 > @clobber() {
+  %1 = alloca i64
+  %2 = load volatile i64, i64* %1
+  ; CHECK-NOT: popq %rsp
+  ; CHECK: addq $8, %rsp
+  ret < 9 x i64 > undef
+}
diff --git a/test/CodeGen/X86/pr40289.ll b/test/CodeGen/X86/pr40289.ll
new file mode 100644
index 000000000000..8bf0517a9a3b
--- /dev/null
+++ b/test/CodeGen/X86/pr40289.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=i686-pc-windows-msvc | FileCheck %s
+
+define < 3 x i32 > @clobber() {
+  %1 = alloca i32
+  %2 = load volatile i32, i32* %1
+  ; CHECK-NOT: popl %esp
+  ; CHECK: addl $4, %esp
+  ret < 3 x i32 > undef
+}