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SergioGasquezMabezDev
SergioGasquez
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MabezDev
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Add no_std Xtensa targets support
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11 files changed

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‎compiler/rustc_target/src/spec/base/mod.rs

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@@ -35,3 +35,4 @@ pub(crate) mod windows_gnullvm;
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pub(crate) mod windows_msvc;
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pub(crate) mod windows_uwp_gnu;
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pub(crate) mod windows_uwp_msvc;
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pub(crate) mod xtensa;

‎compiler/rustc_target/src/spec/base/xtensa.rs

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@@ -0,0 +1,17 @@
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use crate::abi::Endian;
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use crate::spec::{Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, TargetOptions};
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pub fn opts() -> TargetOptions {
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TargetOptions {
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os: "none".into(),
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endian: Endian::Little,
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c_int_width: "32".into(),
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linker_flavor: LinkerFlavor::Gnu(Cc::Yes, Lld::No),
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executables: true,
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panic_strategy: PanicStrategy::Abort,
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relocation_model: RelocModel::Static,
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emit_debug_gdb_scripts: false,
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atomic_cas: false,
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..Default::default()
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}
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}

‎compiler/rustc_target/src/spec/mod.rs

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@@ -1766,6 +1766,10 @@ supported_targets! {
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("nvptx64-nvidia-cuda", nvptx64_nvidia_cuda),
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("xtensa-esp32-none-elf", xtensa_esp32_none_elf),
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("xtensa-esp32s2-none-elf", xtensa_esp32s2_none_elf),
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("xtensa-esp32s3-none-elf", xtensa_esp32s3_none_elf),
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("i686-wrs-vxworks", i686_wrs_vxworks),
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("x86_64-wrs-vxworks", x86_64_wrs_vxworks),
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("armv7-wrs-vxworks-eabihf", armv7_wrs_vxworks_eabihf),

‎compiler/rustc_target/src/spec/targets/xtensa_esp32_none_elf.rs

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@@ -0,0 +1,24 @@
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use crate::spec::{base::xtensa, Target, TargetOptions};
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pub fn target() -> Target {
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Target {
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llvm_target: "xtensa-none-elf".into(),
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pointer_width: 32,
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data_layout: "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32".into(),
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arch: "xtensa".into(),
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metadata: crate::spec::TargetMetadata {
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description: Some("Xtensa ESP32".into()),
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tier: Some(3),
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host_tools: Some(false),
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std: Some(false),
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},
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options: TargetOptions {
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cpu: "esp32".into(),
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linker: Some("xtensa-esp32-elf-gcc".into()),
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max_atomic_width: Some(32),
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atomic_cas: true,
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..xtensa::opts()
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},
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}
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}

‎compiler/rustc_target/src/spec/targets/xtensa_esp32s2_none_elf.rs

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@@ -0,0 +1,23 @@
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use crate::spec::{base::xtensa, Target, TargetOptions};
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pub fn target() -> Target {
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Target {
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llvm_target: "xtensa-none-elf".into(),
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pointer_width: 32,
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data_layout: "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32".into(),
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arch: "xtensa".into(),
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metadata: crate::spec::TargetMetadata {
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description: Some("Xtensa ESP32-S2".into()),
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tier: Some(3),
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host_tools: Some(false),
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std: Some(false),
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},
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options: TargetOptions {
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cpu: "esp32-s2".into(),
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linker: Some("xtensa-esp32s2-elf-gcc".into()),
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max_atomic_width: Some(32),
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..xtensa::opts()
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},
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}
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}

‎compiler/rustc_target/src/spec/targets/xtensa_esp32s3_none_elf.rs

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@@ -0,0 +1,24 @@
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use crate::spec::{base::xtensa, Target, TargetOptions};
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pub fn target() -> Target {
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Target {
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llvm_target: "xtensa-none-elf".into(),
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pointer_width: 32,
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data_layout: "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32".into(),
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arch: "xtensa".into(),
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metadata: crate::spec::TargetMetadata {
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description: Some("Xtensa ESP32-S3".into()),
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tier: Some(3),
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host_tools: Some(false),
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std: Some(false),
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},
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options: TargetOptions {
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cpu: "esp32-s3".into(),
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linker: Some("xtensa-esp32s3-elf-gcc".into()),
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max_atomic_width: Some(32),
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atomic_cas: true,
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..xtensa::opts()
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},
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}
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}

‎src/doc/rustc/src/platform-support.md

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@@ -383,5 +383,8 @@ target | std | host | notes
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`x86_64-wrs-vxworks` | ? | |
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[`x86_64h-apple-darwin`](platform-support/x86_64h-apple-darwin.md) | ✓ | ✓ | macOS with late-gen Intel (at least Haswell)
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[`x86_64-unknown-linux-none`](platform-support/x86_64-unknown-linux-none.md) | * | | 64-bit Linux with no libc
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`xtensa-esp32-none-elf` | | | Xtensa ESP32
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`xtensa-esp32s2-none-elf` | | | Xtensa ESP32-S2
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`xtensa-esp32s3-none-elf` | | | Xtensa ESP32-S3
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[runs on NVIDIA GPUs]: https://github.com/japaric-archived/nvptx#targets

‎src/doc/rustc/src/platform-support/xtensa.md

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# `xtensa-*`
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**Tier: 3**
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Targets for Xtensa CPUs.
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## Target maintainers
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- Scott Mabin [@MabezDev](https://github.com/MabezDev)
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- Sergio Gasquez [@SergioGasquez](https://github.com/SergioGasquez)
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## Requirements
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The target names follow this format: `xtensa-$CPU`, where `$CPU` specifies the target chip. The following targets are currently defined:
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| Target name | Target CPU(s) |
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| ------------------------- | --------------------------------------------------------------- |
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| `xtensa-esp32-none-elf` | [ESP32](https://www.espressif.com/en/products/socs/esp32) |
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| `xtensa-esp32s2-none-elf` | [ESP32-S2](https://www.espressif.com/en/products/socs/esp32-s2) |
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| `xtensa-esp32s3-none-elf` | [ESP32-S3](https://www.espressif.com/en/products/socs/esp32-s3) |
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## Building the target
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The targets can be built by installing the [Xtensa enabled Rust channel](https://github.com/esp-rs/rust/). See instructions in the [RISC-V and Xtensa Targets section of the The Rust on ESP Book](https://docs.esp-rs.org/book/installation/riscv-and-xtensa.html).

‎src/tools/tidy/src/target_policy.rs

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@@ -12,6 +12,10 @@ const EXCEPTIONS: &[&str] = &[
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// FIXME: disabled since it fails on CI saying the csky component is missing
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"csky_unknown_linux_gnuabiv2",
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"csky_unknown_linux_gnuabiv2hf",
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// FIXME: disabled since it requires a custom LLVM until the upstream LLVM adds support for the target (https://github.com/espressif/llvm-project/issues/4)
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"xtensa_esp32_none_elf",
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"xtensa_esp32s2_none_elf",
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"xtensa_esp32s3_none_elf",
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];
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pub fn check(root_path: &Path, bad: &mut bool) {

‎tests/assembly/targets/targets-elf.rs

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@@ -573,7 +573,18 @@
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//@ revisions: x86_64_wrs_vxworks
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//@ [x86_64_wrs_vxworks] compile-flags: --target x86_64-wrs-vxworks
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//@ [x86_64_wrs_vxworks] needs-llvm-components: x86
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// FIXME: disabled since it requires a custom LLVM until the upstream LLVM adds support for the target (https://github.com/espressif/llvm-project/issues/4)
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/*
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revisions: xtensa_esp32_none_elf
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[xtensa_esp32_none_elf] compile-flags: --target xtensa-esp32-none-elf
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[xtensa_esp32_none_elf] needs-llvm-components: xtensa
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revisions: xtensa_esp32s2_none_elf
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[xtensa_esp32s2_none_elf] compile-flags: --target xtensa-esp32s2-none-elf
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[xtensa_esp32s2_none_elf] needs-llvm-components: xtensa
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revisions: xtensa_esp32s3_none_elf
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[xtensa_esp32s3_none_elf] compile-flags: --target xtensa-esp32s3-none-elf
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[xtensa_esp32s3_none_elf] needs-llvm-components: xtensa
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*/
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// Sanity-check that each target can produce assembly code.
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#![feature(no_core, lang_items)]

‎tests/ui/check-cfg/well-known-values.stderr

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@@ -129,7 +129,7 @@ warning: unexpected `cfg` condition value: `_UNEXPECTED_VALUE`
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LL | target_arch = "_UNEXPECTED_VALUE",
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| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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|
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= note: expected values for `target_arch` are: `aarch64`, `arm`, `arm64ec`, `avr`, `bpf`, `csky`, `hexagon`, `loongarch64`, `m68k`, `mips`, `mips32r6`, `mips64`, `mips64r6`, `msp430`, `nvptx64`, `powerpc`, `powerpc64`, `riscv32`, `riscv64`, `s390x`, `sparc`, `sparc64`, `wasm32`, `wasm64`, `x86`, and `x86_64`
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= note: expected values for `target_arch` are: `aarch64`, `arm`, `arm64ec`, `avr`, `bpf`, `csky`, `hexagon`, `loongarch64`, `m68k`, `mips`, `mips32r6`, `mips64`, `mips64r6`, `msp430`, `nvptx64`, `powerpc`, `powerpc64`, `riscv32`, `riscv64`, `s390x`, `sparc`, `sparc64`, `wasm32`, `wasm64`, `x86`, `x86_64`, and `xtensa`
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= note: see <https://doc.rust-lang.org/nightly/rustc/check-cfg.html> for more information about checking conditional configuration
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warning: unexpected `cfg` condition value: `_UNEXPECTED_VALUE`

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