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Auto merge of #77527 - jonas-schievink:rollup-szgq5he, r=jonas-schievink
Rollup of 8 pull requests Successful merges: - #77072 (Minor `hash_map` doc adjustments + item attribute orderings) - #77368 (Backport LLVM apfloat commit to rustc_apfloat) - #77445 (BTreeMap: complete the compile-time test_variance test case) - #77504 (Support vectors with fewer than 8 elements for simd_select_bitmask) - #77513 (Change DocFragments from enum variant fields to structs with a nested enum) - #77518 (Only use Fira Sans for the first `td` in item lists) - #77521 (Move target feature whitelist from cg_llvm to cg_ssa) - #77525 (Enable RenameReturnPlace MIR optimization on mir-opt-level >= 2) Failed merges: r? `@ghost`
2 parents 0644cc1 + fa200ce commit a835b48

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21 files changed

+438
-318
lines changed

21 files changed

+438
-318
lines changed

‎compiler/rustc_apfloat/src/ieee.rs

+10-5
Original file line numberDiff line numberDiff line change
@@ -1511,11 +1511,16 @@ impl<S: Semantics, T: Semantics> FloatConvert<IeeeFloat<T>> for IeeeFloat<S> {
15111511
sig::set_bit(&mut r.sig, T::PRECISION - 1);
15121512
}
15131513

1514-
// gcc forces the Quiet bit on, which means (float)(double)(float_sNan)
1515-
// does not give you back the same bits. This is dubious, and we
1516-
// don't currently do it. You're really supposed to get
1517-
// an invalid operation signal at runtime, but nobody does that.
1518-
status = Status::OK;
1514+
// Convert of sNaN creates qNaN and raises an exception (invalid op).
1515+
// This also guarantees that a sNaN does not become Inf on a truncation
1516+
// that loses all payload bits.
1517+
if self.is_signaling() {
1518+
// Quiet signaling NaN.
1519+
sig::set_bit(&mut r.sig, T::QNAN_BIT);
1520+
status = Status::INVALID_OP;
1521+
} else {
1522+
status = Status::OK;
1523+
}
15191524
} else {
15201525
*loses_info = false;
15211526
status = Status::OK;

‎compiler/rustc_apfloat/tests/ieee.rs

+25-9
Original file line numberDiff line numberDiff line change
@@ -566,6 +566,17 @@ fn fma() {
566566
}
567567
}
568568

569+
#[test]
570+
fn issue_69532() {
571+
let f = Double::from_bits(0x7FF0_0000_0000_0001u64 as u128);
572+
let mut loses_info = false;
573+
let sta = f.convert(&mut loses_info);
574+
let r: Single = sta.value;
575+
assert!(loses_info);
576+
assert!(r.is_nan());
577+
assert_eq!(sta.status, Status::INVALID_OP);
578+
}
579+
569580
#[test]
570581
fn min_num() {
571582
let f1 = Double::from_f64(1.0);
@@ -1492,27 +1503,32 @@ fn convert() {
14921503
assert_eq!(4294967295.0, test.to_f64());
14931504
assert!(!loses_info);
14941505

1495-
let test = Single::snan(None);
1496-
let x87_snan = X87DoubleExtended::snan(None);
1497-
let test: X87DoubleExtended = test.convert(&mut loses_info).value;
1498-
assert!(test.bitwise_eq(x87_snan));
1499-
assert!(!loses_info);
1500-
15011506
let test = Single::qnan(None);
15021507
let x87_qnan = X87DoubleExtended::qnan(None);
15031508
let test: X87DoubleExtended = test.convert(&mut loses_info).value;
15041509
assert!(test.bitwise_eq(x87_qnan));
15051510
assert!(!loses_info);
15061511

1507-
let test = X87DoubleExtended::snan(None);
1508-
let test: X87DoubleExtended = test.convert(&mut loses_info).value;
1509-
assert!(test.bitwise_eq(x87_snan));
1512+
let test = Single::snan(None);
1513+
let sta = test.convert(&mut loses_info);
1514+
let test: X87DoubleExtended = sta.value;
1515+
assert!(test.is_nan());
1516+
assert!(!test.is_signaling());
15101517
assert!(!loses_info);
1518+
assert_eq!(sta.status, Status::INVALID_OP);
15111519

15121520
let test = X87DoubleExtended::qnan(None);
15131521
let test: X87DoubleExtended = test.convert(&mut loses_info).value;
15141522
assert!(test.bitwise_eq(x87_qnan));
15151523
assert!(!loses_info);
1524+
1525+
let test = X87DoubleExtended::snan(None);
1526+
let sta = test.convert(&mut loses_info);
1527+
let test: X87DoubleExtended = sta.value;
1528+
assert!(test.is_nan());
1529+
assert!(!test.is_signaling());
1530+
assert!(!loses_info);
1531+
assert_eq!(sta.status, Status::INVALID_OP);
15161532
}
15171533

15181534
#[test]

‎compiler/rustc_codegen_llvm/src/attributes.rs

+3-5
Original file line numberDiff line numberDiff line change
@@ -349,17 +349,15 @@ pub fn from_fn_attrs(cx: &CodegenCx<'ll, 'tcx>, llfn: &'ll Value, instance: ty::
349349
}
350350

351351
pub fn provide(providers: &mut Providers) {
352+
use rustc_codegen_ssa::target_features::{all_known_features, supported_target_features};
352353
providers.supported_target_features = |tcx, cnum| {
353354
assert_eq!(cnum, LOCAL_CRATE);
354355
if tcx.sess.opts.actually_rustdoc {
355356
// rustdoc needs to be able to document functions that use all the features, so
356357
// provide them all.
357-
llvm_util::all_known_features().map(|(a, b)| (a.to_string(), b)).collect()
358+
all_known_features().map(|(a, b)| (a.to_string(), b)).collect()
358359
} else {
359-
llvm_util::supported_target_features(tcx.sess)
360-
.iter()
361-
.map(|&(a, b)| (a.to_string(), b))
362-
.collect()
360+
supported_target_features(tcx.sess).iter().map(|&(a, b)| (a.to_string(), b)).collect()
363361
}
364362
};
365363

‎compiler/rustc_codegen_llvm/src/intrinsic.rs

+7-3
Original file line numberDiff line numberDiff line change
@@ -793,14 +793,18 @@ fn generic_simd_intrinsic(
793793
require_simd!(arg_tys[1], "argument");
794794
let v_len = arg_tys[1].simd_size(tcx);
795795
require!(
796-
m_len == v_len,
796+
// Allow masks for vectors with fewer than 8 elements to be
797+
// represented with a u8 or i8.
798+
m_len == v_len || (m_len == 8 && v_len < 8),
797799
"mismatched lengths: mask length `{}` != other vector length `{}`",
798800
m_len,
799801
v_len
800802
);
801803
let i1 = bx.type_i1();
802-
let i1xn = bx.type_vector(i1, m_len);
803-
let m_i1s = bx.bitcast(args[0].immediate(), i1xn);
804+
let im = bx.type_ix(v_len);
805+
let i1xn = bx.type_vector(i1, v_len);
806+
let m_im = bx.trunc(args[0].immediate(), im);
807+
let m_i1s = bx.bitcast(m_im, i1xn);
804808
return Ok(bx.select(m_i1s, args[1].immediate(), args[2].immediate()));
805809
}
806810

‎compiler/rustc_codegen_llvm/src/llvm_util.rs

+1-149
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
11
use crate::back::write::create_informational_target_machine;
22
use crate::llvm;
33
use libc::c_int;
4+
use rustc_codegen_ssa::target_features::supported_target_features;
45
use rustc_data_structures::fx::FxHashSet;
56
use rustc_feature::UnstableFeatures;
67
use rustc_middle::bug;
78
use rustc_session::config::PrintRequest;
89
use rustc_session::Session;
9-
use rustc_span::symbol::sym;
1010
use rustc_span::symbol::Symbol;
1111
use rustc_target::spec::{MergeFunctions, PanicStrategy};
1212
use std::ffi::CString;
@@ -139,140 +139,6 @@ pub fn time_trace_profiler_finish(file_name: &str) {
139139
// WARNING: the features after applying `to_llvm_feature` must be known
140140
// to LLVM or the feature detection code will walk past the end of the feature
141141
// array, leading to crashes.
142-
143-
const ARM_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
144-
("aclass", Some(sym::arm_target_feature)),
145-
("mclass", Some(sym::arm_target_feature)),
146-
("rclass", Some(sym::arm_target_feature)),
147-
("dsp", Some(sym::arm_target_feature)),
148-
("neon", Some(sym::arm_target_feature)),
149-
("crc", Some(sym::arm_target_feature)),
150-
("crypto", Some(sym::arm_target_feature)),
151-
("v5te", Some(sym::arm_target_feature)),
152-
("v6", Some(sym::arm_target_feature)),
153-
("v6k", Some(sym::arm_target_feature)),
154-
("v6t2", Some(sym::arm_target_feature)),
155-
("v7", Some(sym::arm_target_feature)),
156-
("v8", Some(sym::arm_target_feature)),
157-
("vfp2", Some(sym::arm_target_feature)),
158-
("vfp3", Some(sym::arm_target_feature)),
159-
("vfp4", Some(sym::arm_target_feature)),
160-
// This is needed for inline assembly, but shouldn't be stabilized as-is
161-
// since it should be enabled per-function using #[instruction_set], not
162-
// #[target_feature].
163-
("thumb-mode", Some(sym::arm_target_feature)),
164-
];
165-
166-
const AARCH64_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
167-
("fp", Some(sym::aarch64_target_feature)),
168-
("neon", Some(sym::aarch64_target_feature)),
169-
("sve", Some(sym::aarch64_target_feature)),
170-
("crc", Some(sym::aarch64_target_feature)),
171-
("crypto", Some(sym::aarch64_target_feature)),
172-
("ras", Some(sym::aarch64_target_feature)),
173-
("lse", Some(sym::aarch64_target_feature)),
174-
("rdm", Some(sym::aarch64_target_feature)),
175-
("fp16", Some(sym::aarch64_target_feature)),
176-
("rcpc", Some(sym::aarch64_target_feature)),
177-
("dotprod", Some(sym::aarch64_target_feature)),
178-
("tme", Some(sym::aarch64_target_feature)),
179-
("v8.1a", Some(sym::aarch64_target_feature)),
180-
("v8.2a", Some(sym::aarch64_target_feature)),
181-
("v8.3a", Some(sym::aarch64_target_feature)),
182-
];
183-
184-
const X86_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
185-
("adx", Some(sym::adx_target_feature)),
186-
("aes", None),
187-
("avx", None),
188-
("avx2", None),
189-
("avx512bw", Some(sym::avx512_target_feature)),
190-
("avx512cd", Some(sym::avx512_target_feature)),
191-
("avx512dq", Some(sym::avx512_target_feature)),
192-
("avx512er", Some(sym::avx512_target_feature)),
193-
("avx512f", Some(sym::avx512_target_feature)),
194-
("avx512ifma", Some(sym::avx512_target_feature)),
195-
("avx512pf", Some(sym::avx512_target_feature)),
196-
("avx512vbmi", Some(sym::avx512_target_feature)),
197-
("avx512vl", Some(sym::avx512_target_feature)),
198-
("avx512vpopcntdq", Some(sym::avx512_target_feature)),
199-
("bmi1", None),
200-
("bmi2", None),
201-
("cmpxchg16b", Some(sym::cmpxchg16b_target_feature)),
202-
("f16c", Some(sym::f16c_target_feature)),
203-
("fma", None),
204-
("fxsr", None),
205-
("lzcnt", None),
206-
("movbe", Some(sym::movbe_target_feature)),
207-
("pclmulqdq", None),
208-
("popcnt", None),
209-
("rdrand", None),
210-
("rdseed", None),
211-
("rtm", Some(sym::rtm_target_feature)),
212-
("sha", None),
213-
("sse", None),
214-
("sse2", None),
215-
("sse3", None),
216-
("sse4.1", None),
217-
("sse4.2", None),
218-
("sse4a", Some(sym::sse4a_target_feature)),
219-
("ssse3", None),
220-
("tbm", Some(sym::tbm_target_feature)),
221-
("xsave", None),
222-
("xsavec", None),
223-
("xsaveopt", None),
224-
("xsaves", None),
225-
];
226-
227-
const HEXAGON_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
228-
("hvx", Some(sym::hexagon_target_feature)),
229-
("hvx-length128b", Some(sym::hexagon_target_feature)),
230-
];
231-
232-
const POWERPC_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
233-
("altivec", Some(sym::powerpc_target_feature)),
234-
("power8-altivec", Some(sym::powerpc_target_feature)),
235-
("power9-altivec", Some(sym::powerpc_target_feature)),
236-
("power8-vector", Some(sym::powerpc_target_feature)),
237-
("power9-vector", Some(sym::powerpc_target_feature)),
238-
("vsx", Some(sym::powerpc_target_feature)),
239-
];
240-
241-
const MIPS_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] =
242-
&[("fp64", Some(sym::mips_target_feature)), ("msa", Some(sym::mips_target_feature))];
243-
244-
const RISCV_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
245-
("m", Some(sym::riscv_target_feature)),
246-
("a", Some(sym::riscv_target_feature)),
247-
("c", Some(sym::riscv_target_feature)),
248-
("f", Some(sym::riscv_target_feature)),
249-
("d", Some(sym::riscv_target_feature)),
250-
("e", Some(sym::riscv_target_feature)),
251-
];
252-
253-
const WASM_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
254-
("simd128", Some(sym::wasm_target_feature)),
255-
("atomics", Some(sym::wasm_target_feature)),
256-
("nontrapping-fptoint", Some(sym::wasm_target_feature)),
257-
];
258-
259-
/// When rustdoc is running, provide a list of all known features so that all their respective
260-
/// primitives may be documented.
261-
///
262-
/// IMPORTANT: If you're adding another feature list above, make sure to add it to this iterator!
263-
pub fn all_known_features() -> impl Iterator<Item = (&'static str, Option<Symbol>)> {
264-
std::iter::empty()
265-
.chain(ARM_ALLOWED_FEATURES.iter())
266-
.chain(AARCH64_ALLOWED_FEATURES.iter())
267-
.chain(X86_ALLOWED_FEATURES.iter())
268-
.chain(HEXAGON_ALLOWED_FEATURES.iter())
269-
.chain(POWERPC_ALLOWED_FEATURES.iter())
270-
.chain(MIPS_ALLOWED_FEATURES.iter())
271-
.chain(RISCV_ALLOWED_FEATURES.iter())
272-
.chain(WASM_ALLOWED_FEATURES.iter())
273-
.cloned()
274-
}
275-
276142
pub fn to_llvm_feature<'a>(sess: &Session, s: &'a str) -> &'a str {
277143
let arch = if sess.target.target.arch == "x86_64" { "x86" } else { &*sess.target.target.arch };
278144
match (arch, s) {
@@ -306,20 +172,6 @@ pub fn target_features(sess: &Session) -> Vec<Symbol> {
306172
.collect()
307173
}
308174

309-
pub fn supported_target_features(sess: &Session) -> &'static [(&'static str, Option<Symbol>)] {
310-
match &*sess.target.target.arch {
311-
"arm" => ARM_ALLOWED_FEATURES,
312-
"aarch64" => AARCH64_ALLOWED_FEATURES,
313-
"x86" | "x86_64" => X86_ALLOWED_FEATURES,
314-
"hexagon" => HEXAGON_ALLOWED_FEATURES,
315-
"mips" | "mips64" => MIPS_ALLOWED_FEATURES,
316-
"powerpc" | "powerpc64" => POWERPC_ALLOWED_FEATURES,
317-
"riscv32" | "riscv64" => RISCV_ALLOWED_FEATURES,
318-
"wasm32" => WASM_ALLOWED_FEATURES,
319-
_ => &[],
320-
}
321-
}
322-
323175
pub fn print_version() {
324176
// Can be called without initializing LLVM
325177
unsafe {

‎compiler/rustc_codegen_ssa/src/lib.rs

+1
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,7 @@ pub mod glue;
4242
pub mod meth;
4343
pub mod mir;
4444
pub mod mono_item;
45+
pub mod target_features;
4546
pub mod traits;
4647

4748
pub struct ModuleCodegen<M> {

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