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Fix simd_reduce_* intrinsics
1 parent a7b06e8 commit 344cbac

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2 files changed

+8
-6
lines changed

2 files changed

+8
-6
lines changed

src/intrinsics/mod.rs

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -218,15 +218,17 @@ fn simd_pair_for_each_lane<'tcx>(
218218
fn simd_reduce<'tcx>(
219219
fx: &mut FunctionCx<'_, '_, 'tcx>,
220220
val: CValue<'tcx>,
221+
acc: Option<Value>,
221222
ret: CPlace<'tcx>,
222223
f: impl Fn(&mut FunctionCx<'_, '_, 'tcx>, TyAndLayout<'tcx>, Value, Value) -> Value,
223224
) {
224225
let (lane_count, lane_ty) = val.layout().ty.simd_size_and_type(fx.tcx);
225226
let lane_layout = fx.layout_of(lane_ty);
226227
assert_eq!(lane_layout, ret.layout());
227228

228-
let mut res_val = val.value_lane(fx, 0).load_scalar(fx);
229-
for lane_idx in 1..lane_count {
229+
let (mut res_val, start_lane) =
230+
if let Some(acc) = acc { (acc, 0) } else { (val.value_lane(fx, 0).load_scalar(fx), 1) };
231+
for lane_idx in start_lane..lane_count {
230232
let lane = val.value_lane(fx, lane_idx).load_scalar(fx);
231233
res_val = f(fx, lane_layout, res_val, lane);
232234
}

src/intrinsics/simd.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -236,9 +236,9 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
236236
simd_flt_binop!(fx, fmax(x, y) -> ret);
237237
};
238238

239-
simd_reduce_add_ordered | simd_reduce_add_unordered, (c v) {
239+
simd_reduce_add_ordered | simd_reduce_add_unordered, (c v, v acc) {
240240
validate_simd_type!(fx, intrinsic, span, v.layout().ty);
241-
simd_reduce(fx, v, ret, |fx, lane_layout, a, b| {
241+
simd_reduce(fx, v, Some(acc), ret, |fx, lane_layout, a, b| {
242242
if lane_layout.ty.is_floating_point() {
243243
fx.bcx.ins().fadd(a, b)
244244
} else {
@@ -247,9 +247,9 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
247247
});
248248
};
249249

250-
simd_reduce_mul_ordered | simd_reduce_mul_unordered, (c v) {
250+
simd_reduce_mul_ordered | simd_reduce_mul_unordered, (c v, v acc) {
251251
validate_simd_type!(fx, intrinsic, span, v.layout().ty);
252-
simd_reduce(fx, v, ret, |fx, lane_layout, a, b| {
252+
simd_reduce(fx, v, Some(acc), ret, |fx, lane_layout, a, b| {
253253
if lane_layout.ty.is_floating_point() {
254254
fx.bcx.ins().fmul(a, b)
255255
} else {

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