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nikicAmanieu
nikic
authored and
Amanieu
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Update test expectations for aarch64
1 parent 1ee5288 commit 44dbe95

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+33
-40
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+33
-40
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‎crates/core_arch/src/aarch64/neon/generated.rs

+24-24
Original file line numberDiff line numberDiff line change
@@ -1357,7 +1357,7 @@ pub unsafe fn vcgeq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
13571357
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s8)
13581358
#[inline]
13591359
#[target_feature(enable = "neon")]
1360-
#[cfg_attr(test, assert_instr(cmgt))]
1360+
#[cfg_attr(test, assert_instr(cmge))]
13611361
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13621362
pub unsafe fn vcgez_s8(a: int8x8_t) -> uint8x8_t {
13631363
let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
@@ -1369,7 +1369,7 @@ pub unsafe fn vcgez_s8(a: int8x8_t) -> uint8x8_t {
13691369
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s8)
13701370
#[inline]
13711371
#[target_feature(enable = "neon")]
1372-
#[cfg_attr(test, assert_instr(cmgt))]
1372+
#[cfg_attr(test, assert_instr(cmge))]
13731373
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13741374
pub unsafe fn vcgezq_s8(a: int8x16_t) -> uint8x16_t {
13751375
let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@@ -1381,7 +1381,7 @@ pub unsafe fn vcgezq_s8(a: int8x16_t) -> uint8x16_t {
13811381
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s16)
13821382
#[inline]
13831383
#[target_feature(enable = "neon")]
1384-
#[cfg_attr(test, assert_instr(cmgt))]
1384+
#[cfg_attr(test, assert_instr(cmge))]
13851385
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13861386
pub unsafe fn vcgez_s16(a: int16x4_t) -> uint16x4_t {
13871387
let b: i16x4 = i16x4::new(0, 0, 0, 0);
@@ -1393,7 +1393,7 @@ pub unsafe fn vcgez_s16(a: int16x4_t) -> uint16x4_t {
13931393
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s16)
13941394
#[inline]
13951395
#[target_feature(enable = "neon")]
1396-
#[cfg_attr(test, assert_instr(cmgt))]
1396+
#[cfg_attr(test, assert_instr(cmge))]
13971397
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
13981398
pub unsafe fn vcgezq_s16(a: int16x8_t) -> uint16x8_t {
13991399
let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
@@ -1405,7 +1405,7 @@ pub unsafe fn vcgezq_s16(a: int16x8_t) -> uint16x8_t {
14051405
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s32)
14061406
#[inline]
14071407
#[target_feature(enable = "neon")]
1408-
#[cfg_attr(test, assert_instr(cmgt))]
1408+
#[cfg_attr(test, assert_instr(cmge))]
14091409
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14101410
pub unsafe fn vcgez_s32(a: int32x2_t) -> uint32x2_t {
14111411
let b: i32x2 = i32x2::new(0, 0);
@@ -1417,7 +1417,7 @@ pub unsafe fn vcgez_s32(a: int32x2_t) -> uint32x2_t {
14171417
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s32)
14181418
#[inline]
14191419
#[target_feature(enable = "neon")]
1420-
#[cfg_attr(test, assert_instr(cmgt))]
1420+
#[cfg_attr(test, assert_instr(cmge))]
14211421
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14221422
pub unsafe fn vcgezq_s32(a: int32x4_t) -> uint32x4_t {
14231423
let b: i32x4 = i32x4::new(0, 0, 0, 0);
@@ -1429,7 +1429,7 @@ pub unsafe fn vcgezq_s32(a: int32x4_t) -> uint32x4_t {
14291429
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s64)
14301430
#[inline]
14311431
#[target_feature(enable = "neon")]
1432-
#[cfg_attr(test, assert_instr(cmgt))]
1432+
#[cfg_attr(test, assert_instr(cmge))]
14331433
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14341434
pub unsafe fn vcgez_s64(a: int64x1_t) -> uint64x1_t {
14351435
let b: i64x1 = i64x1::new(0);
@@ -1441,7 +1441,7 @@ pub unsafe fn vcgez_s64(a: int64x1_t) -> uint64x1_t {
14411441
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s64)
14421442
#[inline]
14431443
#[target_feature(enable = "neon")]
1444-
#[cfg_attr(test, assert_instr(cmgt))]
1444+
#[cfg_attr(test, assert_instr(cmge))]
14451445
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
14461446
pub unsafe fn vcgezq_s64(a: int64x2_t) -> uint64x2_t {
14471447
let b: i64x2 = i64x2::new(0, 0);
@@ -1711,7 +1711,7 @@ pub unsafe fn vcgtzd_f64(a: f64) -> u64 {
17111711
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s8)
17121712
#[inline]
17131713
#[target_feature(enable = "neon")]
1714-
#[cfg_attr(test, assert_instr(cmgt))]
1714+
#[cfg_attr(test, assert_instr(cmle))]
17151715
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17161716
pub unsafe fn vclez_s8(a: int8x8_t) -> uint8x8_t {
17171717
let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
@@ -1723,7 +1723,7 @@ pub unsafe fn vclez_s8(a: int8x8_t) -> uint8x8_t {
17231723
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s8)
17241724
#[inline]
17251725
#[target_feature(enable = "neon")]
1726-
#[cfg_attr(test, assert_instr(cmgt))]
1726+
#[cfg_attr(test, assert_instr(cmle))]
17271727
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17281728
pub unsafe fn vclezq_s8(a: int8x16_t) -> uint8x16_t {
17291729
let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@@ -1735,7 +1735,7 @@ pub unsafe fn vclezq_s8(a: int8x16_t) -> uint8x16_t {
17351735
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s16)
17361736
#[inline]
17371737
#[target_feature(enable = "neon")]
1738-
#[cfg_attr(test, assert_instr(cmgt))]
1738+
#[cfg_attr(test, assert_instr(cmle))]
17391739
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17401740
pub unsafe fn vclez_s16(a: int16x4_t) -> uint16x4_t {
17411741
let b: i16x4 = i16x4::new(0, 0, 0, 0);
@@ -1747,7 +1747,7 @@ pub unsafe fn vclez_s16(a: int16x4_t) -> uint16x4_t {
17471747
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s16)
17481748
#[inline]
17491749
#[target_feature(enable = "neon")]
1750-
#[cfg_attr(test, assert_instr(cmgt))]
1750+
#[cfg_attr(test, assert_instr(cmle))]
17511751
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17521752
pub unsafe fn vclezq_s16(a: int16x8_t) -> uint16x8_t {
17531753
let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
@@ -1759,7 +1759,7 @@ pub unsafe fn vclezq_s16(a: int16x8_t) -> uint16x8_t {
17591759
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s32)
17601760
#[inline]
17611761
#[target_feature(enable = "neon")]
1762-
#[cfg_attr(test, assert_instr(cmgt))]
1762+
#[cfg_attr(test, assert_instr(cmle))]
17631763
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17641764
pub unsafe fn vclez_s32(a: int32x2_t) -> uint32x2_t {
17651765
let b: i32x2 = i32x2::new(0, 0);
@@ -1771,7 +1771,7 @@ pub unsafe fn vclez_s32(a: int32x2_t) -> uint32x2_t {
17711771
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s32)
17721772
#[inline]
17731773
#[target_feature(enable = "neon")]
1774-
#[cfg_attr(test, assert_instr(cmgt))]
1774+
#[cfg_attr(test, assert_instr(cmle))]
17751775
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17761776
pub unsafe fn vclezq_s32(a: int32x4_t) -> uint32x4_t {
17771777
let b: i32x4 = i32x4::new(0, 0, 0, 0);
@@ -1783,7 +1783,7 @@ pub unsafe fn vclezq_s32(a: int32x4_t) -> uint32x4_t {
17831783
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s64)
17841784
#[inline]
17851785
#[target_feature(enable = "neon")]
1786-
#[cfg_attr(test, assert_instr(cmgt))]
1786+
#[cfg_attr(test, assert_instr(cmle))]
17871787
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
17881788
pub unsafe fn vclez_s64(a: int64x1_t) -> uint64x1_t {
17891789
let b: i64x1 = i64x1::new(0);
@@ -1795,7 +1795,7 @@ pub unsafe fn vclez_s64(a: int64x1_t) -> uint64x1_t {
17951795
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s64)
17961796
#[inline]
17971797
#[target_feature(enable = "neon")]
1798-
#[cfg_attr(test, assert_instr(cmgt))]
1798+
#[cfg_attr(test, assert_instr(cmle))]
17991799
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
18001800
pub unsafe fn vclezq_s64(a: int64x2_t) -> uint64x2_t {
18011801
let b: i64x2 = i64x2::new(0, 0);
@@ -9215,7 +9215,7 @@ pub unsafe fn vfma_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t, c:
92159215
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f64)
92169216
#[inline]
92179217
#[target_feature(enable = "neon")]
9218-
#[cfg_attr(test, assert_instr(fmla, LANE = 0))]
9218+
#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
92199219
#[rustc_legacy_const_generics(3)]
92209220
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
92219221
pub unsafe fn vfma_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t, c: float64x2_t) -> float64x1_t {
@@ -9254,7 +9254,7 @@ pub unsafe fn vfmaq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t, c
92549254
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_lane_f32)
92559255
#[inline]
92569256
#[target_feature(enable = "neon")]
9257-
#[cfg_attr(test, assert_instr(fmla, LANE = 0))]
9257+
#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
92589258
#[rustc_legacy_const_generics(3)]
92599259
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
92609260
pub unsafe fn vfmas_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
@@ -9273,7 +9273,7 @@ pub unsafe fn vfmas_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) ->
92739273
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_laneq_f32)
92749274
#[inline]
92759275
#[target_feature(enable = "neon")]
9276-
#[cfg_attr(test, assert_instr(fmla, LANE = 0))]
9276+
#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
92779277
#[rustc_legacy_const_generics(3)]
92789278
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
92799279
pub unsafe fn vfmas_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
@@ -9311,7 +9311,7 @@ pub unsafe fn vfmad_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) ->
93119311
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_laneq_f64)
93129312
#[inline]
93139313
#[target_feature(enable = "neon")]
9314-
#[cfg_attr(test, assert_instr(fmla, LANE = 0))]
9314+
#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
93159315
#[rustc_legacy_const_generics(3)]
93169316
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
93179317
pub unsafe fn vfmad_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
@@ -9441,7 +9441,7 @@ pub unsafe fn vfms_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t, c:
94419441
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f64)
94429442
#[inline]
94439443
#[target_feature(enable = "neon")]
9444-
#[cfg_attr(test, assert_instr(fmls, LANE = 0))]
9444+
#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
94459445
#[rustc_legacy_const_generics(3)]
94469446
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
94479447
pub unsafe fn vfms_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t, c: float64x2_t) -> float64x1_t {
@@ -9480,7 +9480,7 @@ pub unsafe fn vfmsq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t, c
94809480
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_lane_f32)
94819481
#[inline]
94829482
#[target_feature(enable = "neon")]
9483-
#[cfg_attr(test, assert_instr(fmls, LANE = 0))]
9483+
#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
94849484
#[rustc_legacy_const_generics(3)]
94859485
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
94869486
pub unsafe fn vfmss_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
@@ -9492,7 +9492,7 @@ pub unsafe fn vfmss_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) ->
94929492
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_laneq_f32)
94939493
#[inline]
94949494
#[target_feature(enable = "neon")]
9495-
#[cfg_attr(test, assert_instr(fmls, LANE = 0))]
9495+
#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
94969496
#[rustc_legacy_const_generics(3)]
94979497
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
94989498
pub unsafe fn vfmss_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
@@ -9516,7 +9516,7 @@ pub unsafe fn vfmsd_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) ->
95169516
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_laneq_f64)
95179517
#[inline]
95189518
#[target_feature(enable = "neon")]
9519-
#[cfg_attr(test, assert_instr(fmls, LANE = 0))]
9519+
#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
95209520
#[rustc_legacy_const_generics(3)]
95219521
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
95229522
pub unsafe fn vfmsd_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {

‎crates/stdarch-gen/neon.spec

+9-16
Original file line numberDiff line numberDiff line change
@@ -732,7 +732,7 @@ a = MIN, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0
732732
fixed = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
733733
validate FALSE, FALSE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE
734734

735-
aarch64 = cmgt
735+
aarch64 = cmge
736736
generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t, int64x1_t:uint64x1_t, int64x2_t:uint64x2_t
737737

738738
/// Floating-point compare greater than or equal to zero
@@ -808,7 +808,7 @@ a = MIN, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0
808808
fixed = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
809809
validate TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
810810

811-
aarch64 = cmgt
811+
aarch64 = cmle
812812
generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t, int64x1_t:uint64x1_t, int64x2_t:uint64x2_t
813813

814814
/// Floating-point compare less than or equal to zero
@@ -4032,9 +4032,9 @@ validate 14., 11., 18., 21.
40324032
aarch64 = fmla
40334033
generate float32x2_t, float32x2_t:float32x2_t:float32x4_t:float32x2_t, float32x4_t:float32x4_t:float32x2_t:float32x4_t, float32x4_t
40344034
aarch64 = fmadd
4035-
generate float64x1_t
4035+
generate float64x1_t, float64x1_t:float64x1_t:float64x2_t:float64x1_t
40364036
aarch64 = fmla
4037-
generate float64x1_t:float64x1_t:float64x2_t:float64x1_t, float64x2_t:float64x2_t:float64x1_t:float64x2_t, float64x2_t
4037+
generate float64x2_t:float64x2_t:float64x1_t:float64x2_t, float64x2_t
40384038

40394039
/// Floating-point fused multiply-add to accumulator
40404040
name = vfma
@@ -4049,14 +4049,11 @@ c = 3., 0., 0., 0.
40494049
n = 0
40504050
validate 20.
40514051

4052-
aarch64 = fmla
4052+
aarch64 = fmadd
40534053
link-aarch64 = llvm.fma._EXT_:f32:f32:f32:f32
40544054
generate f32:f32:float32x2_t:f32, f32:f32:float32x4_t:f32
40554055
link-aarch64 = llvm.fma._EXT_:f64:f64:f64:f64
4056-
aarch64 = fmadd
4057-
generate f64:f64:float64x1_t:f64
4058-
aarch64 = fmla
4059-
generate f64:f64:float64x2_t:f64
4056+
generate f64:f64:float64x1_t:f64, f64:f64:float64x2_t:f64
40604057

40614058
/// Floating-point fused multiply-subtract from accumulator
40624059
name = vfms
@@ -4109,9 +4106,9 @@ validate 2., 3., 4., 5.
41094106
aarch64 = fmls
41104107
generate float32x2_t, float32x2_t:float32x2_t:float32x4_t:float32x2_t, float32x4_t:float32x4_t:float32x2_t:float32x4_t, float32x4_t
41114108
aarch64 = fmsub
4112-
generate float64x1_t
4109+
generate float64x1_t, float64x1_t:float64x1_t:float64x2_t:float64x1_t
41134110
aarch64 = fmls
4114-
generate float64x1_t:float64x1_t:float64x2_t:float64x1_t, float64x2_t:float64x2_t:float64x1_t:float64x2_t, float64x2_t
4111+
generate float64x2_t:float64x2_t:float64x1_t:float64x2_t, float64x2_t
41154112

41164113
/// Floating-point fused multiply-subtract to accumulator
41174114
name = vfms
@@ -4124,12 +4121,8 @@ c = 2., 0., 0., 0.
41244121
n = 0
41254122
validate 2.
41264123

4127-
aarch64 = fmls
4128-
generate f32:f32:float32x2_t:f32, f32:f32:float32x4_t:f32
41294124
aarch64 = fmsub
4130-
generate f64:f64:float64x1_t:f64
4131-
aarch64 = fmls
4132-
generate f64:f64:float64x2_t:f64
4125+
generate f32:f32:float32x2_t:f32, f32:f32:float32x4_t:f32, f64:f64:float64x1_t:f64, f64:f64:float64x2_t:f64
41334126

41344127
/// Divide
41354128
name = vdiv

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