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RISC-V: riscv_hwprobe-based feature detection on Linux / Android
This commit implements `riscv_hwprobe`-based feature detection as available on newer versions of the Linux kernel. It also queries whether the vector extensions are enabled using `prctl` but this is not supported on QEMU's userland emulator (as of version 9.2.3) and use the auxiliary vector as a fallback. Currently, all extensions discoverable from the Linux kernel version 6.14 and related extension groups (except "Supm", which reports the existence of `prctl`-based pointer masking control and too OS-dependent) are implemented. Co-Authored-By: Taiki Endo <[email protected]>
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‎crates/std_detect/README.md

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@@ -56,11 +56,14 @@ crate from working on applications in which `std` is not available.
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[`cupid`](https://crates.io/crates/cupid) crate.
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* Linux/Android:
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* `arm{32, 64}`, `mips{32,64}{,el}`, `powerpc{32,64}{,le}`, `riscv{32,64}`, `loongarch64`, `s390x`:
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* `arm{32, 64}`, `mips{32,64}{,el}`, `powerpc{32,64}{,le}`, `loongarch64`, `s390x`:
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`std_detect` supports these on Linux by querying ELF auxiliary vectors (using `getauxval`
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when available), and if that fails, by querying `/proc/cpuinfo`.
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* `arm64`: partial support for doing run-time feature detection by directly
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querying `mrs` is implemented for Linux >= 4.11, but not enabled by default.
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* `riscv{32,64}`:
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`std_detect` supports these on Linux by querying `riscv_hwprobe`, and
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by querying ELF auxiliary vectors (using `getauxval` when available).
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* FreeBSD:
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* `arm32`, `powerpc64`: `std_detect` supports these on FreeBSD by querying ELF

‎crates/std_detect/src/detect/arch/riscv.rs

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@@ -37,22 +37,39 @@ features! {
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/// * Zbb: `"zbb"`
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/// * Zbs: `"zbs"`
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/// * C: `"c"`
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/// * Zca: `"zca"`
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/// * Zcd: `"zcd"` (if D is enabled)
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/// * Zcf: `"zcf"` (if F is enabled on RV32)
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/// * D: `"d"`
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/// * F: `"f"`
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/// * M: `"m"`
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/// * Q: `"q"`
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/// * V: `"v"`
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/// * Zve32x: `"zve32x"`
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/// * Zve32f: `"zve32f"`
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/// * Zve64x: `"zve64x"`
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/// * Zve64f: `"zve64f"`
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/// * Zve64d: `"zve64d"`
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/// * Zicboz: `"zicboz"`
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/// * Zicntr: `"zicntr"`
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/// * Zicond: `"zicond"`
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/// * Zicsr: `"zicsr"`
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/// * Zifencei: `"zifencei"`
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/// * Zihintntl: `"zihintntl"`
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/// * Zihintpause: `"zihintpause"`
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/// * Zihpm: `"zihpm"`
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/// * Zimop: `"zimop"`
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/// * Zacas: `"zacas"`
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/// * Zawrs: `"zawrs"`
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/// * Zfa: `"zfa"`
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/// * Zfh: `"zfh"`
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/// * Zfhmin: `"zfhmin"`
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/// * Zfinx: `"zfinx"`
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/// * Zdinx: `"zdinx"`
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/// * Zhinx: `"zhinx"`
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/// * Zhinxmin: `"zhinxmin"`
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/// * Zcb: `"zcb"`
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/// * Zcmop: `"zcmop"`
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/// * Zbc: `"zbc"`
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/// * Zbkb: `"zbkb"`
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/// * Zbkc: `"zbkc"`
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/// * Zksed: `"zksed"`
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/// * Zksh: `"zksh"`
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/// * Zkt: `"zkt"`
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/// * Zvbb: `"zvbb"`
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/// * Zvbc: `"zvbc"`
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/// * Zvfh: `"zvfh"`
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/// * Zvfhmin: `"zvfhmin"`
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/// * Zvkb: `"zvkb"`
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/// * Zvkg: `"zvkg"`
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/// * Zvkn: `"zvkn"`
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/// * Zvkned: `"zvkned"`
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/// * Zvknha: `"zvknha"`
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/// * Zvknhb: `"zvknhb"`
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/// * Zvknc: `"zvknc"`
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/// * Zvkng: `"zvkng"`
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/// * Zvks: `"zvks"`
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/// * Zvksed: `"zvksed"`
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/// * Zvksh: `"zvksh"`
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/// * Zvksc: `"zvksc"`
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/// * Zvksg: `"zvksg"`
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/// * Zvkt: `"zvkt"`
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/// * Ztso: `"ztso"`
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///
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/// There's also bases and extensions marked as standard instruction set,
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/// * Svnapot: `"svnapot"`
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/// * Svpbmt: `"svpbmt"`
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/// * Svinval: `"svinval"`
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///
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/// # Performance Hints
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///
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/// The two features below define performance hints for unaligned
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/// scalar/vector memory accesses, respectively. If enabled, it denotes that
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/// corresponding unaligned memory access is reasonably fast.
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///
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/// * `"unaligned-scalar-mem"`
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/// * `"unaligned-vector-mem"`
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#[stable(feature = "riscv_ratified", since = "1.78.0")]
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32i: "rv32i";
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without cfg check: true;
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/// RV128I Base Integer Instruction Set
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] unaligned_scalar_mem: "unaligned-scalar-mem";
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/// Has reasonably performant unaligned scalar
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] unaligned_vector_mem: "unaligned-vector-mem";
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/// Has reasonably performant unaligned vector
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicsr: "zicsr";
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without cfg check: true;
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/// "Zicsr" Extension for Control and Status Register (CSR) Instructions
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without cfg check: true;
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/// "Zifencei" Extension for Instruction-Fetch Fence
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintntl: "zihintntl";
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without cfg check: true;
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/// "Zihintntl" Extension for Non-Temporal Locality Hints
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintpause: "zihintpause";
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without cfg check: true;
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/// "Zihintpause" Extension for Pause Hint
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zimop: "zimop";
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without cfg check: true;
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/// "Zimop" Extension for May-Be-Operations
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicboz: "zicboz";
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without cfg check: true;
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/// "Zicboz" Extension for Cache-Block Zero Instruction
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicond: "zicond";
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without cfg check: true;
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/// "Zicond" Extension for Integer Conditional Operations
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] m: "m";
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/// "M" Extension for Integer Multiplication and Division
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/// "Zalrsc" Extension for Load-Reserved/Store-Conditional Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zaamo: "zaamo";
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/// "Zaamo" Extension for Atomic Memory Operations
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zawrs: "zawrs";
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/// "Zawrs" Extension for Wait-on-Reservation-Set instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zacas: "zacas";
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/// "Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam";
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without cfg check: true;
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/// "Zam" Extension for Misaligned Atomics
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/// "Zfh" Extension for Half-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfhmin: "zfhmin";
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/// "Zfhmin" Extension for Minimal Half-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfa: "zfa";
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without cfg check: true;
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/// "Zfa" Extension for Additional Floating-Point Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfinx: "zfinx";
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/// "Zfinx" Extension for Single-Precision Floating-Point in Integer Registers
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] c: "c";
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/// "C" Extension for Compressed Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zca: "zca";
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without cfg check: true;
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/// "Zca" Compressed Instructions excluding Floating-Point Loads/Stores
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcf: "zcf";
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without cfg check: true;
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/// "Zcf" Compressed Instructions for Single-Precision Floating-Point Loads/Stores on RV32
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcd: "zcd";
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without cfg check: true;
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/// "Zcd" Compressed Instructions for Double-Precision Floating-Point Loads/Stores
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcb: "zcb";
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without cfg check: true;
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/// "Zcb" Simple Code-size Saving Compressed Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcmop: "zcmop";
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without cfg check: true;
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/// "Zcmop" Extension for Compressed May-Be-Operations
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] b: "b";
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] v: "v";
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/// "V" Extension for Vector Operations
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve32x: "zve32x";
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/// "Zve32x" Vector Extension for Embedded Processors (32-bit+; Integer)
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve32f: "zve32f";
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/// "Zve32f" Vector Extension for Embedded Processors (32-bit+; with Single-Precision Floating-Point)
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64x: "zve64x";
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/// "Zve64x" Vector Extension for Embedded Processors (64-bit+; Integer)
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64f: "zve64f";
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/// "Zve64f" Vector Extension for Embedded Processors (64-bit+; with Single-Precision Floating-Point)
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64d: "zve64d";
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/// "Zve64d" Vector Extension for Embedded Processors (64-bit+; with Double-Precision Floating-Point)
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfh: "zvfh";
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/// "Zvfh" Vector Extension for Half-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfhmin: "zvfhmin";
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/// "Zvfhmin" Vector Extension for Minimal Half-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvbb: "zvbb";
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/// "Zvbb" Extension for Vector Basic Bit-Manipulation
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvbc: "zvbc";
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/// "Zvbc" Extension for Vector Carryless Multiplication
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkb: "zvkb";
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/// "Zvkb" Extension for Vector Cryptography Bit-Manipulation
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkg: "zvkg";
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/// "Zvkg" Cryptography Extension for Vector GCM/GMAC
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkned: "zvkned";
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/// "Zvkned" Cryptography Extension for NIST Suite: Vector AES Block Cipher
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknha: "zvknha";
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/// "Zvknha" Cryptography Extension for Vector SHA-2 Secure Hash (SHA-256)
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknhb: "zvknhb";
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/// "Zvknhb" Cryptography Extension for Vector SHA-2 Secure Hash (SHA-256/512)
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksed: "zvksed";
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/// "Zvksed" Cryptography Extension for ShangMi Suite: Vector SM4 Block Cipher
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksh: "zvksh";
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/// "Zvksh" Cryptography Extension for ShangMi Suite: Vector SM3 Secure Hash
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkn: "zvkn";
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/// "Zvkn" Cryptography Extension for NIST Algorithm Suite
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknc: "zvknc";
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/// "Zvknc" Cryptography Extension for NIST Algorithm Suite with Carryless Multiply
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkng: "zvkng";
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/// "Zvkng" Cryptography Extension for NIST Algorithm Suite with GCM
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvks: "zvks";
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/// "Zvks" Cryptography Extension for ShangMi Algorithm Suite
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksc: "zvksc";
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/// "Zvksc" Cryptography Extension for ShangMi Algorithm Suite with Carryless Multiply
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksg: "zvksg";
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/// "Zvksg" Cryptography Extension for ShangMi Algorithm Suite with GCM
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkt: "zvkt";
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/// "Zvkt" Extension for Vector Data-Independent Execution Latency
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svnapot: "svnapot";
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without cfg check: true;

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