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| 1 | +//! Run-time feature detection for s390x on Linux. |
| 2 | +
|
| 3 | +use super::auxvec; |
| 4 | +use crate::detect::{bit, cache, Feature}; |
| 5 | + |
| 6 | +/// Try to read the features from the auxiliary vector |
| 7 | +pub(crate) fn detect_features() -> cache::Initializer { |
| 8 | + if let Ok(auxv) = auxvec::auxv() { |
| 9 | + let hwcap: AtHwcap = auxv.into(); |
| 10 | + return hwcap.cache(); |
| 11 | + } |
| 12 | + |
| 13 | + cache::Initializer::default() |
| 14 | +} |
| 15 | + |
| 16 | +/// These values are part of the platform-specific [asm/elf.h][kernel], and are a selection of the |
| 17 | +/// fields found in the [Facility Indications]. |
| 18 | +/// |
| 19 | +/// [Facility Indications]: https://www.ibm.com/support/pages/sites/default/files/2021-05/SA22-7871-10.pdf#page=63 |
| 20 | +/// [kernel]: https://github.com/torvalds/linux/blob/b62cef9a5c673f1b8083159f5dc03c1c5daced2f/arch/s390/include/asm/elf.h#L129 |
| 21 | +#[derive(Debug, Default, PartialEq)] |
| 22 | +struct AtHwcap { |
| 23 | + esan3: bool, |
| 24 | + zarch: bool, |
| 25 | + stfle: bool, |
| 26 | + msa: bool, |
| 27 | + ldisp: bool, |
| 28 | + eimm: bool, |
| 29 | + dfp: bool, |
| 30 | + hpage: bool, |
| 31 | + etf3eh: bool, |
| 32 | + high_gprs: bool, |
| 33 | + te: bool, |
| 34 | + vxrs: bool, |
| 35 | + vxrs_bcd: bool, |
| 36 | + vxrs_ext: bool, |
| 37 | + gs: bool, |
| 38 | + vxrs_ext2: bool, |
| 39 | + vxrs_pde: bool, |
| 40 | + sort: bool, |
| 41 | + dflt: bool, |
| 42 | + vxrs_pde2: bool, |
| 43 | + nnpa: bool, |
| 44 | + pci_mio: bool, |
| 45 | + sie: bool, |
| 46 | +} |
| 47 | + |
| 48 | +impl From<auxvec::AuxVec> for AtHwcap { |
| 49 | + /// Reads AtHwcap from the auxiliary vector. |
| 50 | + fn from(auxv: auxvec::AuxVec) -> Self { |
| 51 | + AtHwcap { |
| 52 | + esan3: bit::test(auxv.hwcap, 0), |
| 53 | + zarch: bit::test(auxv.hwcap, 1), |
| 54 | + stfle: bit::test(auxv.hwcap, 2), |
| 55 | + msa: bit::test(auxv.hwcap, 3), |
| 56 | + ldisp: bit::test(auxv.hwcap, 4), |
| 57 | + eimm: bit::test(auxv.hwcap, 5), |
| 58 | + dfp: bit::test(auxv.hwcap, 6), |
| 59 | + hpage: bit::test(auxv.hwcap, 7), |
| 60 | + etf3eh: bit::test(auxv.hwcap, 8), |
| 61 | + high_gprs: bit::test(auxv.hwcap, 9), |
| 62 | + te: bit::test(auxv.hwcap, 10), |
| 63 | + vxrs: bit::test(auxv.hwcap, 11), |
| 64 | + vxrs_bcd: bit::test(auxv.hwcap, 12), |
| 65 | + vxrs_ext: bit::test(auxv.hwcap, 13), |
| 66 | + gs: bit::test(auxv.hwcap, 14), |
| 67 | + vxrs_ext2: bit::test(auxv.hwcap, 15), |
| 68 | + vxrs_pde: bit::test(auxv.hwcap, 16), |
| 69 | + sort: bit::test(auxv.hwcap, 17), |
| 70 | + dflt: bit::test(auxv.hwcap, 18), |
| 71 | + vxrs_pde2: bit::test(auxv.hwcap, 19), |
| 72 | + nnpa: bit::test(auxv.hwcap, 20), |
| 73 | + pci_mio: bit::test(auxv.hwcap, 21), |
| 74 | + sie: bit::test(auxv.hwcap, 22), |
| 75 | + } |
| 76 | + } |
| 77 | +} |
| 78 | + |
| 79 | +impl AtHwcap { |
| 80 | + /// Initializes the cache from the feature bits. |
| 81 | + fn cache(self) -> cache::Initializer { |
| 82 | + let mut value = cache::Initializer::default(); |
| 83 | + { |
| 84 | + let mut enable_feature = |f, enable| { |
| 85 | + if enable { |
| 86 | + value.set(f as u32); |
| 87 | + } |
| 88 | + }; |
| 89 | + |
| 90 | + // bit 129 of the extended facility list |
| 91 | + enable_feature(Feature::vector, self.vxrs); |
| 92 | + } |
| 93 | + value |
| 94 | + } |
| 95 | +} |
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