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Stabilize Ratified RISC-V Target Features
As shortly discussed on Zulip (https://rust-lang.zulipchat.com/#narrow/stream/250483-t-compiler.2Frisc-v/topic/Stabilization.20of.20RISC-V.20Target.20Features/near/394793704), this commit stabilizes the ratified RISC-V instruction bases and extensions. Specifically, this commit stabilizes the: * Instruction-Fetch Fence (Zifencei) on v2.0 * Control and Status Register (Zcsr) on v2.0 * Pause Hint (Zihintpause) on v2.0 * Zicntr and Zihpm were ratified March 2023 * Supervisor-level Instructions (S) on v1.12 * Atomic Instructions (A) on v2.0 * Compressed Instructions (C) on v2.0 * Integer Multiplication and Division (M) on v2.0 * Bit Manipulations (B) on v1.0 listed as `zba`, `zbc`, `zbs` * Scalar Cryptography (Zk) v1.0.1 listed as `zk`, `zkn`, `zknd`, `zkne`, `zknh`, `zkr`, `zks`, `zksed`, `zksh`, `zkt`, `zbkb`, `zbkc` `zkbx`
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  • crates/std_detect/src/detect/arch

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Diff for: ‎crates/std_detect/src/detect/arch/riscv.rs

+59-70
Original file line numberDiff line numberDiff line change
@@ -24,26 +24,48 @@ features! {
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///
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/// The supported ratified RISC-V instruction sets are as follows:
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///
27+
/// * RV32E: `"rv32e"`
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/// * RV32I: `"rv32i"`
28-
/// * Zifencei: `"zifencei"`
29-
/// * Zihintpause: `"zihintpause"`
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/// * RV64I: `"rv64i"`
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/// * M: `"m"`
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/// * A: `"a"`
33-
/// * Zicsr: `"zicsr"`
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/// * Zicntr: `"zicntr"`
35-
/// * Zihpm: `"zihpm"`
36-
/// * F: `"f"`
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/// * B: `"b"`
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/// * Zba: `"zba"`
33+
/// * Zbb: `"zbb"`
34+
/// * Zbc: `"zbc"`
35+
/// * Zbs: `"zbs"`
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/// * C: `"c"`
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/// * D: `"d"`
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/// * F: `"f"`
39+
/// * M: `"m"`
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/// * Q: `"q"`
39-
/// * C: `"c"`
41+
/// * V: `"v"`
42+
/// * Zicntr: `"zicntr"`
43+
/// * Zicsr: `"zicsr"`
44+
/// * Zifencei: `"zifencei"`
45+
/// * Zihintpause: `"zihintpause"`
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/// * Zihpm: `"zihpm"`
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/// * Zk: `"zk"`
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/// * Zbkb: `"zbkb"`
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/// * Zbkc: `"zbkc"`
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/// * Zbkx: `"zbkx"`
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/// * Zkn: `"zkn"`
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/// * Zknd: `"zknd"`
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/// * Zkne: `"zkne"`
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/// * Zknh: `"zknh"`
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/// * Zkr: `"zkr"`
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/// * Zks: `"zks"`
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/// * Zksed: `"zksed"`
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/// * Zksh: `"zksh"`
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/// * Zkt: `"zkt"`
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///
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/// There's also bases and extensions marked as standard instruction set,
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/// but they are in frozen or draft state. These instruction sets are also
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/// reserved by this macro and can be detected in the future platforms.
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///
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/// Frozen RISC-V instruction sets:
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///
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/// * Zfh: `"zfh"`
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/// * Zfhmin: `"zfhmin"`
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/// * Zfinx: `"zfinx"`
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/// * Zdinx: `"zdinx"`
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/// * Zhinx: `"zhinx"`
@@ -52,14 +74,9 @@ features! {
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///
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/// Draft RISC-V instruction sets:
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///
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/// * RV32E: `"rv32e"`
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/// * RV128I: `"rv128i"`
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/// * Zfh: `"zfh"`
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/// * Zfhmin: `"zfhmin"`
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/// * B: `"b"`
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/// * J: `"j"`
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/// * P: `"p"`
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/// * V: `"v"`
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/// * Zam: `"zam"`
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///
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/// Defined by Privileged Specification:
@@ -70,61 +87,33 @@ features! {
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/// * Svinval: `"svinval"`
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/// * Hypervisor: `"h"`
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///
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/// # RISC-V Bit-Manipulation ISA-extensions
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///
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/// This document defined the following extensions:
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///
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/// * Zba: `"zba"`
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/// * Zbb: `"zbb"`
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/// * Zbc: `"zbc"`
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/// * Zbs: `"zbs"`
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///
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/// # RISC-V Cryptography Extensions
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///
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/// These extensions are defined in Volume I, Scalar & Entropy Source
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/// Instructions:
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///
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/// * Zbkb: `"zbkb"`
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/// * Zbkc: `"zbkc"`
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/// * Zbkx: `"zbkx"`
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/// * Zknd: `"zknd"`
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/// * Zkne: `"zkne"`
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/// * Zknh: `"zknh"`
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/// * Zksed: `"zksed"`
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/// * Zksh: `"zksh"`
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/// * Zkr: `"zkr"`
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/// * Zkn: `"zkn"`
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/// * Zks: `"zks"`
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/// * Zk: `"zk"`
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/// * Zkt: `"zkt"`
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///
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/// [ISA manual]: https://github.com/riscv/riscv-isa-manual/
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#[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")]
103-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32i: "rv32i";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] rv32i: "rv32i";
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/// RV32I Base Integer Instruction Set
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zifencei: "zifencei";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zifencei: "zifencei";
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/// "Zifencei" Instruction-Fetch Fence
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintpause: "zihintpause";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zihintpause: "zihintpause";
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/// "Zihintpause" Pause Hint
109-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv64i: "rv64i";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] rv64i: "rv64i";
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/// RV64I Base Integer Instruction Set
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] m: "m";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] m: "m";
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/// "M" Standard Extension for Integer Multiplication and Division
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] a: "a";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] a: "a";
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/// "A" Standard Extension for Atomic Instructions
115-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicsr: "zicsr";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zicsr: "zicsr";
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/// "Zicsr", Control and Status Register (CSR) Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicntr: "zicntr";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zicntr: "zicntr";
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/// "Zicntr", Standard Extension for Base Counters and Timers
119-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihpm: "zihpm";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zihpm: "zihpm";
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/// "Zihpm", Standard Extension for Hardware Performance Counters
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] f: "f";
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/// "F" Standard Extension for Single-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] d: "d";
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/// "D" Standard Extension for Double-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] q: "q";
126115
/// "Q" Standard Extension for Quad-Precision Floating-Point
127-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] c: "c";
116+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] c: "c";
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/// "C" Standard Extension for Compressed Instructions
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130119
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfinx: "zfinx";
@@ -146,7 +135,7 @@ features! {
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/// "Zfh" Standard Extension for 16-Bit Half-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfhmin: "zfhmin";
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/// "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point Support
149-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] b: "b";
138+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] b: "b";
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/// "B" Standard Extension for Bit Manipulation
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] j: "j";
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/// "J" Standard Extension for Dynamically Translated Languages
@@ -157,7 +146,7 @@ features! {
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam";
158147
/// "Zam" Standard Extension for Misaligned Atomics
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160-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] s: "s";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] s: "s";
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/// Supervisor-Level ISA
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svnapot: "svnapot";
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/// "Svnapot" Standard Extension for NAPOT Translation Contiguity
@@ -168,39 +157,39 @@ features! {
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] h: "h";
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/// Hypervisor Extension
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171-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zba: "zba";
160+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zba: "zba";
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/// "Zba" Standard Extension for Address Generation Instructions
173-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbb: "zbb";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbb: "zbb";
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/// "Zbb" Standard Extension for Basic Bit-Manipulation
175-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbc: "zbc";
164+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbc: "zbc";
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/// "Zbc" Standard Extension for Carry-less Multiplication
177-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbs: "zbs";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbs: "zbs";
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/// "Zbs" Standard Extension for Single-Bit instructions
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180-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbkb: "zbkb";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbkb: "zbkb";
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/// "Zbkb" Standard Extension for Bitmanip instructions for Cryptography
182-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbkc: "zbkc";
171+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbkc: "zbkc";
183172
/// "Zbkc" Standard Extension for Carry-less multiply instructions
184-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbkx: "zbkx";
173+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbkx: "zbkx";
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/// "Zbkx" Standard Extension for Crossbar permutation instructions
186-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zknd: "zknd";
175+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zknd: "zknd";
187176
/// "Zknd" Standard Extension for NIST Suite: AES Decryption
188-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zkne: "zkne";
177+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zkne: "zkne";
189178
/// "Zkne" Standard Extension for NIST Suite: AES Encryption
190-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zknh: "zknh";
179+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zknh: "zknh";
191180
/// "Zknh" Standard Extension for NIST Suite: Hash Function Instructions
192-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zksed: "zksed";
181+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zksed: "zksed";
193182
/// "Zksed" Standard Extension for ShangMi Suite: SM4 Block Cipher Instructions
194-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zksh: "zksh";
183+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zksh: "zksh";
195184
/// "Zksh" Standard Extension for ShangMi Suite: SM3 Hash Function Instructions
196-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zkr: "zkr";
185+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zkr: "zkr";
197186
/// "Zkr" Standard Extension for Entropy Source Extension
198-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zkn: "zkn";
187+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zkn: "zkn";
199188
/// "Zkn" Standard Extension for NIST Algorithm Suite
200-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zks: "zks";
189+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zks: "zks";
201190
/// "Zks" Standard Extension for ShangMi Algorithm Suite
202-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zk: "zk";
191+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zk: "zk";
203192
/// "Zk" Standard Extension for Standard scalar cryptography extension
204-
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zkt: "zkt";
193+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zkt: "zkt";
205194
/// "Zkt" Standard Extension for Data Independent Execution Latency
206195
}

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