std_detect: Remove RISC-V privileged features

Author: taiki-e

crates/std_detect/src/detect/arch/riscv.rs

@@ -79,14 +79,6 @@ features! {
     /// * P: `"p"`
     /// * Zam: `"zam"`
     ///
-    /// Defined by Privileged Specification:
-    ///
-    /// * Supervisor: `"s"`
-    /// * Svnapot: `"svnapot"`
-    /// * Svpbmt: `"svpbmt"`
-    /// * Svinval: `"svinval"`
-    /// * Hypervisor: `"h"`
-    ///
     /// [ISA manual]: https://github.com/riscv/riscv-isa-manual/
     #[stable(feature = "riscv_ratified", since = "1.78.0")]
 
@@ -254,22 +246,6 @@ features! {
     @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] unaligned_vector_mem: "unaligned-vector-mem";
     /// Has reasonably performant unaligned vector
 
-    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svnapot: "svnapot";
-    without cfg check: true;
-    /// "Svnapot" Extension for NAPOT Translation Contiguity
-    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svpbmt: "svpbmt";
-    without cfg check: true;
-    /// "Svpbmt" Extension for Page-Based Memory Types
-    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svinval: "svinval";
-    without cfg check: true;
-    /// "Svinval" Extension for Fine-Grained Address-Translation Cache Invalidation
-    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] h: "h";
-    without cfg check: true;
-    /// "H" Extension for Hypervisor Support
-
-    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] s: "s";
-    without cfg check: true;
-    /// Supervisor-Level ISA
     @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] j: "j";
     without cfg check: true;
     /// "J" Extension for Dynamically Translated Languages

crates/std_detect/src/detect/os/linux/riscv.rs

@@ -253,7 +253,7 @@ pub(crate) fn detect_features() -> cache::Initializer {
                 out[3].value == RISCV_HWPROBE_MISALIGNED_VECTOR_FAST,
             );
         }
-        // FIXME: should be enough with hwprobe only, but our code below checks h and e
+        // FIXME: should be enough with hwprobe only, but our code below checks e
         // unavailable in neither uapi/asm/hwprobe.h nor uapi/asm/hwcap.h.
         // https://github.com/torvalds/linux/blob/master/arch/riscv/include/uapi/asm/hwcap.h
         // return value;
@@ -321,20 +321,11 @@ pub(crate) fn detect_features() -> cache::Initializer {
         Feature::rv32e,
         bit::test(auxv.hwcap, (b'e' - b'a').into()),
     );
-    // FIXME: h is not exposed in uapi/asm/hwcap.h and uapi/asm/hwprobe.h
-    enable_feature(
-        &mut value,
-        Feature::h,
-        bit::test(auxv.hwcap, (b'h' - b'a').into()),
-    );
     enable_feature(
         &mut value,
         Feature::m,
         bit::test(auxv.hwcap, (b'm' - b'a').into()),
     );
 
-    // Neither hwprobe nor auxv supports detection of supervisor feature.
-    // Since target_os = "linux" is for user mode, their detection is not useful.
-
     value
 }

crates/std_detect/tests/cpu-detection.rs

@@ -308,11 +308,6 @@ fn riscv_linux() {
         "unaligned-vector-mem: {}",
         is_riscv_feature_detected!("unaligned-vector-mem")
     );
-    println!("svnapot: {}", is_riscv_feature_detected!("svnapot"));
-    println!("svpbmt: {}", is_riscv_feature_detected!("svpbmt"));
-    println!("svinval: {}", is_riscv_feature_detected!("svinval"));
-    println!("h: {}", is_riscv_feature_detected!("h"));
-    println!("s: {}", is_riscv_feature_detected!("s"));
     println!("j: {}", is_riscv_feature_detected!("j"));
     println!("p: {}", is_riscv_feature_detected!("p"));
 }