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adamgemmelladamgemmell
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Update core_arch tests for removal of crypto feature in rustc
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1 file changed

+54
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‎crates/core_arch/src/arm_shared/crypto.rs

+54-27
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,8 @@ use stdarch_test::assert_instr;
5353

5454
/// AES single round encryption.
5555
#[inline]
56-
#[target_feature(enable = "crypto")]
56+
#[cfg_attr(bootstrap, target_feature(enable = "crypto"))]
57+
#[cfg_attr(not(bootstrap), target_feature(enable = "aes"))]
5758
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5859
#[cfg_attr(test, assert_instr(aese))]
5960
pub unsafe fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
@@ -62,7 +63,8 @@ pub unsafe fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
6263

6364
/// AES single round decryption.
6465
#[inline]
65-
#[target_feature(enable = "crypto")]
66+
#[cfg_attr(bootstrap, target_feature(enable = "crypto"))]
67+
#[cfg_attr(not(bootstrap), target_feature(enable = "aes"))]
6668
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6769
#[cfg_attr(test, assert_instr(aesd))]
6870
pub unsafe fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
@@ -71,7 +73,8 @@ pub unsafe fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
7173

7274
/// AES mix columns.
7375
#[inline]
74-
#[target_feature(enable = "crypto")]
76+
#[cfg_attr(bootstrap, target_feature(enable = "crypto"))]
77+
#[cfg_attr(not(bootstrap), target_feature(enable = "aes"))]
7578
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
7679
#[cfg_attr(test, assert_instr(aesmc))]
7780
pub unsafe fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {
@@ -80,7 +83,8 @@ pub unsafe fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {
8083

8184
/// AES inverse mix columns.
8285
#[inline]
83-
#[target_feature(enable = "crypto")]
86+
#[cfg_attr(bootstrap, target_feature(enable = "crypto"))]
87+
#[cfg_attr(not(bootstrap), target_feature(enable = "aes"))]
8488
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8589
#[cfg_attr(test, assert_instr(aesimc))]
8690
pub unsafe fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {
@@ -89,7 +93,8 @@ pub unsafe fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {
8993

9094
/// SHA1 fixed rotate.
9195
#[inline]
92-
#[target_feature(enable = "crypto")]
96+
#[cfg_attr(bootstrap, target_feature(enable = "crypto"))]
97+
#[cfg_attr(not(bootstrap), target_feature(enable = "sha2"))]
9398
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9499
#[cfg_attr(test, assert_instr(sha1h))]
95100
pub unsafe fn vsha1h_u32(hash_e: u32) -> u32 {
@@ -98,7 +103,8 @@ pub unsafe fn vsha1h_u32(hash_e: u32) -> u32 {
98103

99104
/// SHA1 hash update accelerator, choose.
100105
#[inline]
101-
#[target_feature(enable = "crypto")]
106+
#[cfg_attr(bootstrap, target_feature(enable = "crypto"))]
107+
#[cfg_attr(not(bootstrap), target_feature(enable = "sha2"))]
102108
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
103109
#[cfg_attr(test, assert_instr(sha1c))]
104110
pub unsafe fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
@@ -107,7 +113,8 @@ pub unsafe fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) ->
107113

108114
/// SHA1 hash update accelerator, majority.
109115
#[inline]
110-
#[target_feature(enable = "crypto")]
116+
#[cfg_attr(bootstrap, target_feature(enable = "crypto"))]
117+
#[cfg_attr(not(bootstrap), target_feature(enable = "sha2"))]
111118
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
112119
#[cfg_attr(test, assert_instr(sha1m))]
113120
pub unsafe fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
@@ -116,7 +123,8 @@ pub unsafe fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) ->
116123

117124
/// SHA1 hash update accelerator, parity.
118125
#[inline]
119-
#[target_feature(enable = "crypto")]
126+
#[cfg_attr(bootstrap, target_feature(enable = "crypto"))]
127+
#[cfg_attr(not(bootstrap), target_feature(enable = "sha2"))]
120128
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
121129
#[cfg_attr(test, assert_instr(sha1p))]
122130
pub unsafe fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
@@ -125,7 +133,8 @@ pub unsafe fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) ->
125133

126134
/// SHA1 schedule update accelerator, first part.
127135
#[inline]
128-
#[target_feature(enable = "crypto")]
136+
#[cfg_attr(bootstrap, target_feature(enable = "crypto"))]
137+
#[cfg_attr(not(bootstrap), target_feature(enable = "sha2"))]
129138
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
130139
#[cfg_attr(test, assert_instr(sha1su0))]
131140
pub unsafe fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t {
@@ -134,7 +143,8 @@ pub unsafe fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_
134143

135144
/// SHA1 schedule update accelerator, second part.
136145
#[inline]
137-
#[target_feature(enable = "crypto")]
146+
#[cfg_attr(bootstrap, target_feature(enable = "crypto"))]
147+
#[cfg_attr(not(bootstrap), target_feature(enable = "sha2"))]
138148
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
139149
#[cfg_attr(test, assert_instr(sha1su1))]
140150
pub unsafe fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
@@ -143,7 +153,8 @@ pub unsafe fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t
143153

144154
/// SHA256 hash update accelerator.
145155
#[inline]
146-
#[target_feature(enable = "crypto")]
156+
#[cfg_attr(bootstrap, target_feature(enable = "crypto"))]
157+
#[cfg_attr(not(bootstrap), target_feature(enable = "sha2"))]
147158
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
148159
#[cfg_attr(test, assert_instr(sha256h))]
149160
pub unsafe fn vsha256hq_u32(
@@ -156,7 +167,8 @@ pub unsafe fn vsha256hq_u32(
156167

157168
/// SHA256 hash update accelerator, upper part.
158169
#[inline]
159-
#[target_feature(enable = "crypto")]
170+
#[cfg_attr(bootstrap, target_feature(enable = "crypto"))]
171+
#[cfg_attr(not(bootstrap), target_feature(enable = "sha2"))]
160172
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
161173
#[cfg_attr(test, assert_instr(sha256h2))]
162174
pub unsafe fn vsha256h2q_u32(
@@ -169,7 +181,8 @@ pub unsafe fn vsha256h2q_u32(
169181

170182
/// SHA256 schedule update accelerator, first part.
171183
#[inline]
172-
#[target_feature(enable = "crypto")]
184+
#[cfg_attr(bootstrap, target_feature(enable = "crypto"))]
185+
#[cfg_attr(not(bootstrap), target_feature(enable = "sha2"))]
173186
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
174187
#[cfg_attr(test, assert_instr(sha256su0))]
175188
pub unsafe fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t {
@@ -178,7 +191,8 @@ pub unsafe fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t
178191

179192
/// SHA256 schedule update accelerator, second part.
180193
#[inline]
181-
#[target_feature(enable = "crypto")]
194+
#[cfg_attr(bootstrap, target_feature(enable = "crypto"))]
195+
#[cfg_attr(not(bootstrap), target_feature(enable = "sha2"))]
182196
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
183197
#[cfg_attr(test, assert_instr(sha256su1))]
184198
pub unsafe fn vsha256su1q_u32(
@@ -209,7 +223,8 @@ mod tests {
209223
);
210224
}
211225

212-
#[simd_test(enable = "crypto")]
226+
#[cfg_attr(bootstrap, simd_test(enable = "crypto"))]
227+
#[cfg_attr(not(bootstrap), simd_test(enable = "aes"))]
213228
unsafe fn test_vaesdq_u8() {
214229
let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
215230
let key = mem::transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
@@ -220,7 +235,8 @@ mod tests {
220235
);
221236
}
222237

223-
#[simd_test(enable = "crypto")]
238+
#[cfg_attr(bootstrap, simd_test(enable = "crypto"))]
239+
#[cfg_attr(not(bootstrap), simd_test(enable = "aes"))]
224240
unsafe fn test_vaesmcq_u8() {
225241
let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
226242
let r: u8x16 = mem::transmute(vaesmcq_u8(data));
@@ -230,7 +246,8 @@ mod tests {
230246
);
231247
}
232248

233-
#[simd_test(enable = "crypto")]
249+
#[cfg_attr(bootstrap, simd_test(enable = "crypto"))]
250+
#[cfg_attr(not(bootstrap), simd_test(enable = "aes"))]
234251
unsafe fn test_vaesimcq_u8() {
235252
let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
236253
let r: u8x16 = mem::transmute(vaesimcq_u8(data));
@@ -240,13 +257,15 @@ mod tests {
240257
);
241258
}
242259

243-
#[simd_test(enable = "crypto")]
260+
#[cfg_attr(bootstrap, simd_test(enable = "crypto"))]
261+
#[cfg_attr(not(bootstrap), simd_test(enable = "sha2"))]
244262
unsafe fn test_vsha1h_u32() {
245263
assert_eq!(vsha1h_u32(0x1234), 0x048d);
246264
assert_eq!(vsha1h_u32(0x5678), 0x159e);
247265
}
248266

249-
#[simd_test(enable = "crypto")]
267+
#[cfg_attr(bootstrap, simd_test(enable = "crypto"))]
268+
#[cfg_attr(not(bootstrap), simd_test(enable = "sha2"))]
250269
unsafe fn test_vsha1su0q_u32() {
251270
let r: u32x4 = mem::transmute(vsha1su0q_u32(
252271
mem::transmute(u32x4::new(0x1234_u32, 0x5678_u32, 0x9abc_u32, 0xdef0_u32)),
@@ -256,7 +275,8 @@ mod tests {
256275
assert_eq!(r, u32x4::new(0x9abc, 0xdef0, 0x1234, 0x5678));
257276
}
258277

259-
#[simd_test(enable = "crypto")]
278+
#[cfg_attr(bootstrap, simd_test(enable = "crypto"))]
279+
#[cfg_attr(not(bootstrap), simd_test(enable = "sha2"))]
260280
unsafe fn test_vsha1su1q_u32() {
261281
let r: u32x4 = mem::transmute(vsha1su1q_u32(
262282
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
@@ -268,7 +288,8 @@ mod tests {
268288
);
269289
}
270290

271-
#[simd_test(enable = "crypto")]
291+
#[cfg_attr(bootstrap, simd_test(enable = "crypto"))]
292+
#[cfg_attr(not(bootstrap), simd_test(enable = "sha2"))]
272293
unsafe fn test_vsha1cq_u32() {
273294
let r: u32x4 = mem::transmute(vsha1cq_u32(
274295
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
@@ -281,7 +302,8 @@ mod tests {
281302
);
282303
}
283304

284-
#[simd_test(enable = "crypto")]
305+
#[cfg_attr(bootstrap, simd_test(enable = "crypto"))]
306+
#[cfg_attr(not(bootstrap), simd_test(enable = "sha2"))]
285307
unsafe fn test_vsha1pq_u32() {
286308
let r: u32x4 = mem::transmute(vsha1pq_u32(
287309
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
@@ -294,7 +316,8 @@ mod tests {
294316
);
295317
}
296318

297-
#[simd_test(enable = "crypto")]
319+
#[cfg_attr(bootstrap, simd_test(enable = "crypto"))]
320+
#[cfg_attr(not(bootstrap), simd_test(enable = "sha2"))]
298321
unsafe fn test_vsha1mq_u32() {
299322
let r: u32x4 = mem::transmute(vsha1mq_u32(
300323
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
@@ -307,7 +330,8 @@ mod tests {
307330
);
308331
}
309332

310-
#[simd_test(enable = "crypto")]
333+
#[cfg_attr(bootstrap, simd_test(enable = "crypto"))]
334+
#[cfg_attr(not(bootstrap), simd_test(enable = "sha2"))]
311335
unsafe fn test_vsha256hq_u32() {
312336
let r: u32x4 = mem::transmute(vsha256hq_u32(
313337
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
@@ -320,7 +344,8 @@ mod tests {
320344
);
321345
}
322346

323-
#[simd_test(enable = "crypto")]
347+
#[cfg_attr(bootstrap, simd_test(enable = "crypto"))]
348+
#[cfg_attr(not(bootstrap), simd_test(enable = "sha2"))]
324349
unsafe fn test_vsha256h2q_u32() {
325350
let r: u32x4 = mem::transmute(vsha256h2q_u32(
326351
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
@@ -333,7 +358,8 @@ mod tests {
333358
);
334359
}
335360

336-
#[simd_test(enable = "crypto")]
361+
#[cfg_attr(bootstrap, simd_test(enable = "crypto"))]
362+
#[cfg_attr(not(bootstrap), simd_test(enable = "sha2"))]
337363
unsafe fn test_vsha256su0q_u32() {
338364
let r: u32x4 = mem::transmute(vsha256su0q_u32(
339365
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
@@ -345,7 +371,8 @@ mod tests {
345371
);
346372
}
347373

348-
#[simd_test(enable = "crypto")]
374+
#[cfg_attr(bootstrap, simd_test(enable = "crypto"))]
375+
#[cfg_attr(not(bootstrap), simd_test(enable = "sha2"))]
349376
unsafe fn test_vsha256su1q_u32() {
350377
let r: u32x4 = mem::transmute(vsha256su1q_u32(
351378
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),

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