|
6 | 6 | pub struct ExceptionType(isize); |
7 | 7 |
|
8 | 8 | impl ExceptionType { |
9 | | - /// Undefined Exception |
| 9 | + /// Indicates an undefined EBC exception. |
10 | 10 | pub const EXCEPT_EBC_UNDEFINED: Self = Self(0); |
11 | | - /// Divide-by-zero Error |
| 11 | + /// Indicates an EBC divide-by-zero error. |
12 | 12 | pub const EXCEPT_EBC_DIVIDE_ERROR: Self = Self(1); |
13 | | - /// Debug Exception |
| 13 | + /// Indicates an EBC debug exception. |
14 | 14 | pub const EXCEPT_EBC_DEBUG: Self = Self(2); |
15 | | - /// Breakpoint |
| 15 | + /// Indicates an EBC breakpoint. |
16 | 16 | pub const EXCEPT_EBC_BREAKPOINT: Self = Self(3); |
17 | | - /// Overflow |
| 17 | + /// Indicates an EBC overflow. |
18 | 18 | pub const EXCEPT_EBC_OVERFLOW: Self = Self(4); |
19 | | - /// Invalid Opcode |
| 19 | + /// Indicates an invalid EBC opcode. |
20 | 20 | pub const EXCEPT_EBC_INVALID_OPCODE: Self = Self(5); |
21 | | - /// Stack-Segment Fault |
| 21 | + /// Indicates an EBC stack fault. |
22 | 22 | pub const EXCEPT_EBC_STACK_FAULT: Self = Self(6); |
23 | | - /// Alignment Check |
| 23 | + /// Indicates an EBC alignment check. |
24 | 24 | pub const EXCEPT_EBC_ALIGNMENT_CHECK: Self = Self(7); |
25 | | - /// Instruction Encoding Exception |
| 25 | + /// Indicates an EBC instruction-encoding exception. |
26 | 26 | pub const EXCEPT_EBC_INSTRUCTION_ENCODING: Self = Self(8); |
27 | | - /// Bad Breakpoint Exception |
| 27 | + /// Indicates an invalid EBC breakpoint. |
28 | 28 | pub const EXCEPT_EBC_BAD_BREAK: Self = Self(9); |
29 | | - /// Single Step Exception |
| 29 | + /// Indicates an EBC single-step exception. |
30 | 30 | pub const EXCEPT_EBC_SINGLE_STEP: Self = Self(10); |
31 | 31 | } |
32 | 32 |
|
33 | 33 | #[cfg(target_arch = "x86")] |
34 | 34 | impl ExceptionType { |
35 | | - /// Divide-by-zero Error |
| 35 | + /// Indicates a divide-by-zero error. |
36 | 36 | pub const EXCEPT_IA32_DIVIDE_ERROR: Self = Self(0); |
37 | | - /// Debug Exception |
| 37 | + /// Indicates a debug exception. |
38 | 38 | pub const EXCEPT_IA32_DEBUG: Self = Self(1); |
39 | | - /// Non-maskable Interrupt |
| 39 | + /// Indicates a non-maskable interrupt. |
40 | 40 | pub const EXCEPT_IA32_NMI: Self = Self(2); |
41 | | - /// Breakpoint |
| 41 | + /// Indicates a breakpoint. |
42 | 42 | pub const EXCEPT_IA32_BREAKPOINT: Self = Self(3); |
43 | | - /// Overflow |
| 43 | + /// Indicates an overflow. |
44 | 44 | pub const EXCEPT_IA32_OVERFLOW: Self = Self(4); |
45 | | - /// Bound Range Exceeded |
| 45 | + /// Indicates that a bound range was exceeded. |
46 | 46 | pub const EXCEPT_IA32_BOUND: Self = Self(5); |
47 | | - /// Invalid Opcode |
| 47 | + /// Indicates an invalid opcode. |
48 | 48 | pub const EXCEPT_IA32_INVALID_OPCODE: Self = Self(6); |
49 | | - /// Double Fault |
| 49 | + /// Indicates a double fault. |
50 | 50 | pub const EXCEPT_IA32_DOUBLE_FAULT: Self = Self(8); |
51 | | - /// Invalid TSS |
| 51 | + /// Indicates an invalid task-state segment. |
52 | 52 | pub const EXCEPT_IA32_INVALID_TSS: Self = Self(10); |
53 | | - /// Segment Not Present |
| 53 | + /// Indicates a missing segment. |
54 | 54 | pub const EXCEPT_IA32_SEG_NOT_PRESENT: Self = Self(11); |
55 | | - /// Stack-Segment Fault |
| 55 | + /// Indicates a stack-segment fault. |
56 | 56 | pub const EXCEPT_IA32_STACK_FAULT: Self = Self(12); |
57 | | - /// General Protection Fault |
| 57 | + /// Indicates a general-protection fault. |
58 | 58 | pub const EXCEPT_IA32_GP_FAULT: Self = Self(13); |
59 | | - /// Page Fault |
| 59 | + /// Indicates a page fault. |
60 | 60 | pub const EXCEPT_IA32_PAGE_FAULT: Self = Self(14); |
61 | | - /// x87 Floating-Point Exception |
| 61 | + /// Indicates an x87 floating-point exception. |
62 | 62 | pub const EXCEPT_IA32_FP_ERROR: Self = Self(16); |
63 | | - /// Alignment Check |
| 63 | + /// Indicates an alignment check. |
64 | 64 | pub const EXCEPT_IA32_ALIGNMENT_CHECK: Self = Self(17); |
65 | | - /// Machine Check |
| 65 | + /// Indicates a machine check. |
66 | 66 | pub const EXCEPT_IA32_MACHINE_CHECK: Self = Self(18); |
67 | | - /// SIMD Floating-Point Exception |
| 67 | + /// Indicates a SIMD floating-point exception. |
68 | 68 | pub const EXCEPT_IA32_SIMD: Self = Self(19); |
69 | 69 | } |
70 | 70 |
|
71 | 71 | #[cfg(target_arch = "x86_64")] |
72 | 72 | impl ExceptionType { |
73 | | - /// Divide-by-zero Error |
| 73 | + /// Indicates a divide-by-zero error. |
74 | 74 | pub const EXCEPT_X64_DIVIDE_ERROR: Self = Self(0); |
75 | | - /// Debug Exception |
| 75 | + /// Indicates a debug exception. |
76 | 76 | pub const EXCEPT_X64_DEBUG: Self = Self(1); |
77 | | - /// Non-maskable Interrupt |
| 77 | + /// Indicates a non-maskable interrupt. |
78 | 78 | pub const EXCEPT_X64_NMI: Self = Self(2); |
79 | | - /// Breakpoint |
| 79 | + /// Indicates a breakpoint. |
80 | 80 | pub const EXCEPT_X64_BREAKPOINT: Self = Self(3); |
81 | | - /// Overflow |
| 81 | + /// Indicates an overflow. |
82 | 82 | pub const EXCEPT_X64_OVERFLOW: Self = Self(4); |
83 | | - /// Bound Range Exceeded |
| 83 | + /// Indicates that a bound range was exceeded. |
84 | 84 | pub const EXCEPT_X64_BOUND: Self = Self(5); |
85 | | - /// Invalid Opcode |
| 85 | + /// Indicates an invalid opcode. |
86 | 86 | pub const EXCEPT_X64_INVALID_OPCODE: Self = Self(6); |
87 | | - /// Double Fault |
| 87 | + /// Indicates a double fault. |
88 | 88 | pub const EXCEPT_X64_DOUBLE_FAULT: Self = Self(8); |
89 | | - /// Invalid TSS |
| 89 | + /// Indicates an invalid task-state segment. |
90 | 90 | pub const EXCEPT_X64_INVALID_TSS: Self = Self(10); |
91 | | - /// Segment Not Present |
| 91 | + /// Indicates a missing segment. |
92 | 92 | pub const EXCEPT_X64_SEG_NOT_PRESENT: Self = Self(11); |
93 | | - /// Stack-Segment Fault |
| 93 | + /// Indicates a stack-segment fault. |
94 | 94 | pub const EXCEPT_X64_STACK_FAULT: Self = Self(12); |
95 | | - /// General Protection Fault |
| 95 | + /// Indicates a general-protection fault. |
96 | 96 | pub const EXCEPT_X64_GP_FAULT: Self = Self(13); |
97 | | - /// Page Fault |
| 97 | + /// Indicates a page fault. |
98 | 98 | pub const EXCEPT_X64_PAGE_FAULT: Self = Self(14); |
99 | | - /// x87 Floating-Point Exception |
| 99 | + /// Indicates an x87 floating-point exception. |
100 | 100 | pub const EXCEPT_X64_FP_ERROR: Self = Self(16); |
101 | | - /// Alignment Check |
| 101 | + /// Indicates an alignment check. |
102 | 102 | pub const EXCEPT_X64_ALIGNMENT_CHECK: Self = Self(17); |
103 | | - /// Machine Check |
| 103 | + /// Indicates a machine check. |
104 | 104 | pub const EXCEPT_X64_MACHINE_CHECK: Self = Self(18); |
105 | | - /// SIMD Floating-Point Exception |
| 105 | + /// Indicates a SIMD floating-point exception. |
106 | 106 | pub const EXCEPT_X64_SIMD: Self = Self(19); |
107 | 107 | } |
108 | 108 |
|
109 | 109 | #[cfg(target_arch = "arm")] |
110 | 110 | impl ExceptionType { |
111 | | - /// Processor reset |
| 111 | + /// Indicates a processor reset. |
112 | 112 | pub const EXCEPT_ARM_RESET: Self = Self(0); |
113 | | - /// Undefined instruction |
| 113 | + /// Indicates an undefined instruction. |
114 | 114 | pub const EXCEPT_ARM_UNDEFINED_INSTRUCTION: Self = Self(1); |
115 | | - /// Software Interrupt |
| 115 | + /// Indicates a software interrupt. |
116 | 116 | pub const EXCEPT_ARM_SOFTWARE_INTERRUPT: Self = Self(2); |
117 | | - /// Prefetch aborted |
| 117 | + /// Indicates an aborted prefetch. |
118 | 118 | pub const EXCEPT_ARM_PREFETCH_ABORT: Self = Self(3); |
119 | | - /// Data access memory abort |
| 119 | + /// Indicates a data-access memory abort. |
120 | 120 | pub const EXCEPT_ARM_DATA_ABORT: Self = Self(4); |
121 | | - /// Reserved |
| 121 | + /// Represents the reserved exception value. |
122 | 122 | pub const EXCEPT_ARM_RESERVED: Self = Self(5); |
123 | | - /// Normal interrupt |
| 123 | + /// Indicates a normal interrupt. |
124 | 124 | pub const EXCEPT_ARM_IRQ: Self = Self(6); |
125 | | - /// Fast interrupt |
| 125 | + /// Indicates a fast interrupt. |
126 | 126 | pub const EXCEPT_ARM_FIQ: Self = Self(7); |
127 | | - /// In the UEFI spec for "convenience", unsure if we'll need it. Set to `EXCEPT_ARM_FIQ` |
| 127 | + /// Provides the maximum ARM exception value defined by UEFI. |
128 | 128 | pub const MAX_ARM_EXCEPTION: Self = Self::EXCEPT_ARM_FIQ; |
129 | 129 | } |
130 | 130 |
|
131 | 131 | #[cfg(target_arch = "aarch64")] |
132 | 132 | impl ExceptionType { |
133 | | - /// Synchronous exception, such as attempting to execute an invalid instruction |
| 133 | + /// Indicates a synchronous exception, such as an invalid instruction. |
134 | 134 | pub const EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS: Self = Self(0); |
135 | | - /// Normal interrupt |
| 135 | + /// Indicates a normal interrupt. |
136 | 136 | pub const EXCEPT_AARCH64_IRQ: Self = Self(1); |
137 | | - /// Fast interrupt |
| 137 | + /// Indicates a fast interrupt. |
138 | 138 | pub const EXCEPT_AARCH64_FIQ: Self = Self(2); |
139 | | - /// System Error |
| 139 | + /// Indicates a system error. |
140 | 140 | pub const EXCEPT_AARCH64_SERROR: Self = Self(3); |
141 | | - /// In the UEFI spec for "convenience", unsure if we'll need it. Set to `EXCEPT_AARCH64_SERROR` |
| 141 | + /// Provides the maximum AArch64 exception value defined by UEFI. |
142 | 142 | pub const MAX_AARCH64_EXCEPTION: Self = Self::EXCEPT_AARCH64_SERROR; |
143 | 143 | } |
144 | 144 |
|
145 | 145 | #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] |
146 | 146 | impl ExceptionType { |
147 | | - /// Instruction misaligned |
| 147 | + /// Indicates a misaligned instruction address. |
148 | 148 | pub const EXCEPT_RISCV_INST_MISALIGNED: Self = Self(0); |
149 | | - /// Instruction access fault |
| 149 | + /// Indicates an instruction-access fault. |
150 | 150 | pub const EXCEPT_RISCV_INST_ACCESS_FAULT: Self = Self(1); |
151 | | - /// Illegal instruction |
| 151 | + /// Indicates an illegal instruction. |
152 | 152 | pub const EXCEPT_RISCV_ILLEGAL_INST: Self = Self(2); |
153 | | - /// Breakpoint |
| 153 | + /// Indicates a breakpoint. |
154 | 154 | pub const EXCEPT_RISCV_BREAKPOINT: Self = Self(3); |
155 | | - /// Load address misaligned |
| 155 | + /// Indicates a misaligned load address. |
156 | 156 | pub const EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED: Self = Self(4); |
157 | | - /// Load accept fault |
| 157 | + /// Indicates a load-access fault. |
158 | 158 | pub const EXCEPT_RISCV_LOAD_ACCESS_FAULT: Self = Self(5); |
159 | | - /// Store AMO address misaligned |
| 159 | + /// Indicates a misaligned store or AMO address. |
160 | 160 | pub const EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED: Self = Self(6); |
161 | | - /// Store AMO access fault |
| 161 | + /// Indicates a store or AMO access fault. |
162 | 162 | pub const EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT: Self = Self(7); |
163 | | - /// ECALL from User mode |
| 163 | + /// Indicates an environment call from user mode. |
164 | 164 | pub const EXCEPT_RISCV_ENV_CALL_FROM_UMODE: Self = Self(8); |
165 | | - /// ECALL from Supervisor mode |
| 165 | + /// Indicates an environment call from supervisor mode. |
166 | 166 | pub const EXCEPT_RISCV_ENV_CALL_FROM_SMODE: Self = Self(9); |
167 | | - /// ECALL from Machine mode |
| 167 | + /// Indicates an environment call from machine mode. |
168 | 168 | pub const EXCEPT_RISCV_ENV_CALL_FROM_MMODE: Self = Self(11); |
169 | | - /// Instruction page fault |
| 169 | + /// Indicates an instruction page fault. |
170 | 170 | pub const EXCEPT_RISCV_INST_PAGE_FAULT: Self = Self(12); |
171 | | - /// Load page fault |
| 171 | + /// Indicates a load page fault. |
172 | 172 | pub const EXCEPT_RISCV_LOAD_PAGE_FAULT: Self = Self(13); |
173 | | - /// Store AMO page fault |
| 173 | + /// Indicates a store or AMO page fault. |
174 | 174 | pub const EXCEPT_RISCV_STORE_AMO_PAGE_FAULT: Self = Self(15); |
175 | 175 | // RISC-V interrupt types |
176 | | - /// Supervisor software interrupt |
| 176 | + /// Indicates a supervisor software interrupt. |
177 | 177 | pub const EXCEPT_RISCV_SUPERVISOR_SOFTWARE_INT: Self = Self(1); |
178 | | - /// Machine software interrupt |
| 178 | + /// Indicates a machine software interrupt. |
179 | 179 | pub const EXCEPT_RISCV_MACHINE_SOFTWARE_INT: Self = Self(3); |
180 | | - /// Supervisor timer interrupt |
| 180 | + /// Indicates a supervisor timer interrupt. |
181 | 181 | pub const EXCEPT_RISCV_SUPERVISOR_TIMER_INT: Self = Self(5); |
182 | | - /// Machine timer interrupt |
| 182 | + /// Indicates a machine timer interrupt. |
183 | 183 | pub const EXCEPT_RISCV_MACHINE_TIMER_INT: Self = Self(7); |
184 | | - /// Supervisor external interrupt |
| 184 | + /// Indicates a supervisor external interrupt. |
185 | 185 | pub const EXCEPT_RISCV_SUPERVISOR_EXTERNAL_INT: Self = Self(9); |
186 | | - /// Machine external interrupt |
| 186 | + /// Indicates a machine external interrupt. |
187 | 187 | pub const EXCEPT_RISCV_MACHINE_EXTERNAL_INT: Self = Self(11); |
188 | 188 | } |
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