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| 1 | +// Copyright (C) 2019-2020 Alibaba Cloud. All rights reserved. |
| 2 | +// SPDX-License-Identifier: Apache-2.0 |
| 3 | + |
| 4 | +//! Traits and Structs to manage interrupt sources for devices. |
| 5 | +//! |
| 6 | +//! In system programming, an interrupt is a signal to the processor emitted by hardware or |
| 7 | +//! software indicating an event that needs immediate attention. An interrupt alerts the processor |
| 8 | +//! to a high-priority condition requiring the interruption of the current code the processor is |
| 9 | +//! executing. The processor responds by suspending its current activities, saving its state, and |
| 10 | +//! executing a function called an interrupt handler (or an interrupt service routine, ISR) to deal |
| 11 | +//! with the event. This interruption is temporary, and, after the interrupt handler finishes, |
| 12 | +//! unless handling the interrupt has emitted a fatal error, the processor resumes normal |
| 13 | +//! activities. |
| 14 | +//! |
| 15 | +//! Hardware interrupts are used by devices to communicate that they require attention from the |
| 16 | +//! operating system, or a bare-metal program running on the CPU if there are no OSes. The act of |
| 17 | +//! initiating a hardware interrupt is referred to as an interrupt request (IRQ). Different devices |
| 18 | +//! are usually associated with different interrupts using a unique value associated with each |
| 19 | +//! interrupt. This makes it possible to know which hardware device caused which interrupts. |
| 20 | +//! These interrupt values are often called IRQ lines, or just interrupt lines. |
| 21 | +//! |
| 22 | +//! Nowadays, IRQ lines is not the only mechanism to deliver device interrupts to processors. |
| 23 | +//! MSI [(Message Signaled Interrupt)](https://en.wikipedia.org/wiki/Message_Signaled_Interrupts) |
| 24 | +//! is another commonly used alternative in-band method of signaling an interrupt, using special |
| 25 | +//! in-band messages to replace traditional out-of-band assertion of dedicated interrupt lines. |
| 26 | +//! While more complex to implement in a device, message signaled interrupts have some significant |
| 27 | +//! advantages over pin-based out-of-band interrupt signaling. Message signaled interrupts are |
| 28 | +//! supported in PCI bus since its version 2.2, and in later available PCI Express bus. Some non-PCI |
| 29 | +//! architectures also use message signaled interrupts. |
| 30 | +//! |
| 31 | +//! While IRQ is a term commonly used by Operating Systems when dealing with hardware |
| 32 | +//! interrupts, the IRQ numbers managed by OSes are independent of the ones managed by VMM. |
| 33 | +//! For simplicity sake, the term `Interrupt Source` is used instead of IRQ to represent both pin-based |
| 34 | +//! interrupts and MSI interrupts. |
| 35 | +//! |
| 36 | +//! A device may support multiple types of interrupts, and each type of interrupt may support one |
| 37 | +//! or multiple interrupt sources. For example, a PCI device may support: |
| 38 | +//! * Legacy Irq: exactly one interrupt source. |
| 39 | +//! * PCI MSI Irq: 1,2,4,8,16,32 interrupt sources. |
| 40 | +//! * PCI MSIx Irq: 2^n(n=0-11) interrupt sources. |
| 41 | +//! |
| 42 | +//! A distinct Interrupt Source Identifier (ISID) will be assigned to each interrupt source. |
| 43 | +//! An ID allocator will be used to allocate and free Interrupt Source Identifiers for devices. |
| 44 | +//! To decouple the vm-device crate from the ID allocator, the vm-device crate doesn't take the |
| 45 | +//! responsibility to allocate/free Interrupt Source IDs but only makes use of assigned IDs. |
| 46 | +
|
| 47 | +use vmm_sys_util::eventfd::EventFd; |
| 48 | + |
| 49 | +/// Reuse std::io::Result to simplify interoperability among crates. |
| 50 | +pub type Result<T> = std::io::Result<T>; |
| 51 | + |
| 52 | +/// Data type to store an interrupt source identifier. |
| 53 | +pub type InterruptIndex = u32; |
| 54 | + |
| 55 | +/// Trait to manage a group of interrupt sources for a device. |
| 56 | +/// |
| 57 | +/// A device may support several types of interrupts, and each type of interrupt may contain one or |
| 58 | +/// multiple continuous interrupt sources. For example, a PCI device may concurrently support: |
| 59 | +/// * Legacy Irq: exactly one interrupt source. |
| 60 | +/// * PCI MSI Irq: 1,2,4,8,16,32 interrupt sources. |
| 61 | +/// * PCI MSIx Irq: 2^n(n=0-11) interrupt sources. |
| 62 | +/// |
| 63 | +/// PCI MSI interrupts of a device may not be configured individually, and must configured as a |
| 64 | +/// whole block. So all interrupts of the same type of a device are abstracted as an |
| 65 | +/// [InterruptSourceGroup](trait.InterruptSourceGroup.html) object, instead of abstracting each |
| 66 | +/// interrupt source as a distinct InterruptSource. |
| 67 | +pub trait InterruptSourceGroup: Send + Sync { |
| 68 | + /// Type of configuration information for interrupt source. |
| 69 | + type C; |
| 70 | + |
| 71 | + /// Enable the interrupt sources in the group to generate interrupts. |
| 72 | + /// |
| 73 | + /// The `enable()` should be invoked before invoking other methods to manipulate the |
| 74 | + /// InterruptSourceGroup object. |
| 75 | + fn enable(&self, configs: &[Self::C]) -> Result<()>; |
| 76 | + |
| 77 | + /// Disable the interrupt sources in the group to generate interrupts. |
| 78 | + fn disable(&self) -> Result<()>; |
| 79 | + |
| 80 | + /// Update the interrupt source group configuration. |
| 81 | + /// |
| 82 | + /// # Arguments |
| 83 | + /// * index: sub-index into the group. |
| 84 | + /// * config: configuration data for the interrupt source. |
| 85 | + fn update(&self, index: InterruptIndex, config: &Self::C) -> Result<()>; |
| 86 | + |
| 87 | + /// Returns an interrupt notifier from this interrupt. |
| 88 | + /// |
| 89 | + /// An interrupt notifier allows for external components and processes |
| 90 | + /// to inject interrupts into a guest, by writing to the file returned |
| 91 | + /// by this method. |
| 92 | + fn notifier(&self, _index: InterruptIndex) -> Option<&EventFd> { |
| 93 | + None |
| 94 | + } |
| 95 | + |
| 96 | + /// Inject an interrupt from this interrupt source into the guest. |
| 97 | + /// |
| 98 | + /// If the interrupt has an associated `interrupt_status` register, all bits set in `flag` |
| 99 | + /// will be atomically ORed into the `interrupt_status` register. |
| 100 | + fn trigger(&self, index: InterruptIndex) -> Result<()>; |
| 101 | + |
| 102 | + /// Mask an interrupt from this interrupt source. |
| 103 | + fn mask(&self, _index: InterruptIndex) -> Result<()> { |
| 104 | + Err(std::io::Error::from(std::io::ErrorKind::InvalidInput)) |
| 105 | + } |
| 106 | + |
| 107 | + /// Unmask an interrupt from this interrupt source. |
| 108 | + fn unmask(&self, _index: InterruptIndex) -> Result<()> { |
| 109 | + Err(std::io::Error::from(std::io::ErrorKind::InvalidInput)) |
| 110 | + } |
| 111 | + |
| 112 | + /// Check whether there are pending interrupts. |
| 113 | + fn get_pending_state(&self, _index: InterruptIndex) -> bool { |
| 114 | + false |
| 115 | + } |
| 116 | +} |
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