From 5d0eeb42b1d5c21b6513ad0b8ec4b6ffd5dd2dc8 Mon Sep 17 00:00:00 2001 From: Zhouqi Jiang Date: Sun, 15 Dec 2024 23:26:36 +0800 Subject: [PATCH] riscv: asm: amend documents to mention Xuantie C907 core supported assembly functions Signed-off-by: Zhouqi Jiang --- xuantie-riscv/src/asm/xtheadcmo.rs | 48 ++++++++++++++++++----------- xuantie-riscv/src/asm/xtheadsync.rs | 8 ++--- 2 files changed, 34 insertions(+), 22 deletions(-) diff --git a/xuantie-riscv/src/asm/xtheadcmo.rs b/xuantie-riscv/src/asm/xtheadcmo.rs index 71ce767..37741f3 100644 --- a/xuantie-riscv/src/asm/xtheadcmo.rs +++ b/xuantie-riscv/src/asm/xtheadcmo.rs @@ -15,7 +15,7 @@ use core::arch::asm; /// /// # Platform support /// -/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores. +/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores. #[inline] pub unsafe fn dcache_call() { // th.dcache.call @@ -37,7 +37,7 @@ pub unsafe fn dcache_call() { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores. +/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores. #[inline] pub unsafe fn dcache_iall() { // th.dcache.iall @@ -59,7 +59,7 @@ pub unsafe fn dcache_iall() { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores. +/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores. #[inline] pub unsafe fn dcache_ciall() { // th.dcache.ciall @@ -81,7 +81,7 @@ pub unsafe fn dcache_ciall() { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910, C906, E907, E906 and E902 cores. +/// This instruction is supported on Xuantie C910, C906, C907, E907, E906 and E902 cores. #[inline] pub unsafe fn icache_iall() { // th.icache.iall @@ -104,7 +104,7 @@ pub unsafe fn icache_iall() { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910 and C906 cores. +/// This instruction is supported on Xuantie C910, C906 and C907 cores. #[inline] pub unsafe fn icache_ialls() { // th.icache.ialls @@ -192,7 +192,7 @@ pub unsafe fn l2cache_ciall() { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores. +/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores. /// /// The C910 core has a 2-way set-associative D-cache. Input variable `rs1[31]` represents number of way, /// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13; @@ -202,6 +202,10 @@ pub unsafe fn l2cache_ciall() { /// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13; /// when configured 64 Kibibytes, `w` equals 14. /// +/// The C907 core has a 2-way set-associative D-cache. Input variable `rs1[31]` represents number of way, +/// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13; +/// when configured 64 Kibibytes, `w` equals 14. +/// /// The E907 core has a 2-way set-associative D-cache. Input variable `rs1[31]` represents number of way, /// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13; /// when configured 16 Kibibytes, `w` equals 12, and so on. @@ -230,7 +234,7 @@ pub unsafe fn dcache_csw(way_and_set: usize) { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores. +/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores. /// /// The C910 core has a 2-way set-associative D-cache. Input variable `rs1[31]` represents number of way, /// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13; @@ -240,6 +244,10 @@ pub unsafe fn dcache_csw(way_and_set: usize) { /// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13; /// when configured 64 Kibibytes, `w` equals 14. /// +/// The C907 core has a 2-way set-associative D-cache. Input variable `rs1[31]` represents number of way, +/// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13; +/// when configured 64 Kibibytes, `w` equals 14. +/// /// The E907 core has a 2-way set-associative D-cache. Input variable `rs1[31]` represents number of way, /// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13; /// when configured 16 Kibibytes, `w` equals 12, and so on. @@ -270,7 +278,7 @@ pub unsafe fn dcache_isw(way_and_set: usize) { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores. +/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores. /// /// The C910 core has a 2-way set-associative D-cache. Input variable `rs1[31]` represents number of way, /// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13; @@ -280,6 +288,10 @@ pub unsafe fn dcache_isw(way_and_set: usize) { /// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13; /// when configured 64 Kibibytes, `w` equals 14. /// +/// The C907 core has a 2-way set-associative D-cache. Input variable `rs1[31]` represents number of way, +/// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13; +/// when configured 64 Kibibytes, `w` equals 14. +/// /// The E907 core has a 2-way set-associative D-cache. Input variable `rs1[31]` represents number of way, /// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13; /// when configured 16 Kibibytes, `w` equals 12, and so on. @@ -313,7 +325,7 @@ pub unsafe fn dcache_cisw(way_and_set: usize) { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910 and C906 cores. +/// This instruction is supported on Xuantie C910, C906 and C907 cores. /// On Xuantie C906 User Manual, this instruction is named `DCACHE.CVA`. #[inline] pub unsafe fn dcache_cval1(va: usize) { @@ -341,7 +353,7 @@ pub unsafe fn dcache_cval1(va: usize) { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910 core. +/// This instruction is supported on Xuantie C910 and C907 cores. /// /// The Xuantie C906 User Manual names `DCACHE.CVAL1` as `DCACHE.CVA`; to clean dirty item on /// C906 you may need to use function [`dcache_cval1`] on this library. @@ -372,7 +384,7 @@ pub unsafe fn dcache_cva(va: usize) { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910 and C906 cores. +/// This instruction is supported on Xuantie C910, C906 and C907 cores. #[inline] pub unsafe fn dcache_iva(va: usize) { // th.dcache.iva @@ -403,7 +415,7 @@ pub unsafe fn dcache_iva(va: usize) { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910 and C906 cores. +/// This instruction is supported on Xuantie C910, C906 and C907 cores. #[inline] pub unsafe fn dcache_civa(va: usize) { // th.dcache.civa @@ -426,7 +438,7 @@ pub unsafe fn dcache_civa(va: usize) { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores. +/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores. /// On Xuantie C906 User Manual, Xuantie E907 User Manual and Xuantie E906 User Manual, /// this instruction is named `DCACHE.CPA`. #[inline] @@ -451,7 +463,7 @@ pub unsafe fn dcache_cpal1(pa: usize) { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910 core. +/// This instruction is supported on Xuantie C910 and C907 cores. /// /// The Xuantie C906 User Manual, Xuantie E907 User Manual and Xuantie E906 User Manual /// names `DCACHE.CPAL1` as `DCACHE.CPA`; to clean dirty item on @@ -478,7 +490,7 @@ pub unsafe fn dcache_cpa(pa: usize) { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores. +/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores. pub unsafe fn dcache_ipa(pa: usize) { // th.dcache.ipa asm!(".insn i 0x0B, 0, x0, {}, 0x02A", in(reg) pa) @@ -501,7 +513,7 @@ pub unsafe fn dcache_ipa(pa: usize) { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores. +/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores. #[inline] pub unsafe fn dcache_cipa(pa: usize) { // th.dcache.cipa @@ -531,7 +543,7 @@ pub unsafe fn dcache_cipa(pa: usize) { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910 and C906 cores. +/// This instruction is supported on Xuantie C910, C906 and C907 cores. #[inline] pub unsafe fn icache_iva(va: usize) { // th.icache.iva @@ -554,7 +566,7 @@ pub unsafe fn icache_iva(va: usize) { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910, C906, E907, E906 and E902 cores. +/// This instruction is supported on Xuantie C910, C906, C907, E907, E906 and E902 cores. #[inline] pub unsafe fn icache_ipa(pa: usize) { // th.icache.ipa diff --git a/xuantie-riscv/src/asm/xtheadsync.rs b/xuantie-riscv/src/asm/xtheadsync.rs index c4903ef..84ce9bf 100644 --- a/xuantie-riscv/src/asm/xtheadsync.rs +++ b/xuantie-riscv/src/asm/xtheadsync.rs @@ -18,7 +18,7 @@ use core::arch::asm; /// /// # Platform support /// -/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores. +/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores. #[inline] pub unsafe fn sync() { // th.sync @@ -42,7 +42,7 @@ pub unsafe fn sync() { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910 core. +/// This instruction is supported on Xuantie C910 and C907 cores. #[inline] pub unsafe fn sync_s() { // th.sync.s @@ -66,7 +66,7 @@ pub unsafe fn sync_s() { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores. +/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores. #[inline] pub unsafe fn sync_i() { // th.sync.i @@ -91,7 +91,7 @@ pub unsafe fn sync_i() { /// /// # Platform support /// -/// This instruction is supported on Xuantie C910 core. +/// This instruction is supported on Xuantie C910 and C907 cores. #[inline] pub unsafe fn sync_is() { // th.sync.is