Added OpenCV to xfOpenCV migration instructions

Author: amantalwar04

README.md

@@ -9,6 +9,7 @@
     <td width="17%" align="center">Overview</a></td>
     <td width="16%" align="center"><a href="./getting-started-tutorial/README.md">SDSoC Environment Tutorial: Introduction</a></td>
     <td width="17%" align="center"><a href="./platform-creation-tutorial/README.md">SDSoC Environment Tutorial: Platform Creation </a></td>
+    <td width="17%" align="center"><a href="./opencv-to-xfopencv-migration-tutorial/README.md">SDSoC Environment Tutorial: Migrate OpenCV to xfOpenCV</a></td>	
   </tr>
 </table>
 
@@ -23,3 +24,4 @@ The SDSoC environment 2018.2 release includes support for the ZC702, ZC706, and
 ## Related information
  - <a href="./getting-started-tutorial/README.md">SDSoC Environment Tutorial: Introduction</a>
  - <a href="./platform-creation-tutorial/README.md">SDSoC Environment Tutorial: Platform Creation </a>
+ - <a href="./opencv-to-xfopencv-migration-tutorial/README.md">SDSoC Environment Tutorial: Migrate OpenCV to xfOpenCV</a>

opencv-to-xfopencv-migration-tutorial/README.md

@@ -0,0 +1,42 @@
+<!-- <div style="page-break-after: always;"></div> -->
+<!-- <div style="display: none;" media="print"> -->
+<table style="width:100%">
+    <tr>
+        <th width="100%" colspan="6"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>SDSoC Environment Tutorial: Migrate OpenCV to xfOpenCV</h2>
+        </th>
+    </tr>
+    <tr>
+    <td align="center"><a >Introduction</a></td>
+    <td align="center"><a href="lab-1-migrate-opencv-to-xfopencv.md">Lab 1: Migrate OpenCV to xfOpenCV</a></td>
+    <td align="center"><a href="lab2-build-sdsoc-acceleration-project.md">Lab 2: Build the SDSoC Acceleration Project</a></td>
+    </tr>
+</table>
+<!-- </div> -->
+
+# Introduction
+
+xfOpenCV is hardware-accelerated OpenCV functions optimized for Xilinx SoCs and FPGAs. The functions are written completely in C/C++ that is targeted for High-level Synthesis (HLS).  This lab is designed to be used with SDx 2018.2 and using the released ZCU102 reVISION Platform.
+
+The major difference between OpenCV and xfOpenCV is that typical OpenCV is written for and run on CPUs (x86, Arm, etc), whereas xfOpenCV is written and optimized for running on Xilinx SoCs and FPGAs. By optimizing for SoCs and FPGAs the code is up to 40x faster than embedded GPUs and 100x faster than CPUs. Since all the code is written in C/C++ it is easier to customize to your own computer vision functions.
+
+**:pushpin: NOTE**
+**This tutorial assumes you are already familiar with OpenCV and the reVISION platform as described at [reVISION Getting Started Guide](https://github.com/Xilinx/Revision-Getting-Started-Guide/blob/master/software-tools-system-requirements.md). You may want to review this information before proceeding.**
+
+## Revision History
+This is the initial release of the tutorial.
+
+## Change Log
+### 2018.2
+Initial Release
+
+## Support
+To obtain technical support for the tutorial design, go to the:
+
+* [Xilinx Community Forums](https://forums.xilinx.com/)  to ask questions or discuss technical details and issues. Please make sure to browse the existing topics first before filing a new topic. If you do need to file a new topic, make sure it is filed in the sub-forum that best describes the issue or question and that it refers to the tutorial specifically.
+
+<hr/>
+
+:arrow_forward:**Next Topic:**  [Lab 1 - Migrate OpenCV to xfOpenCV](lab-1-migrate-opencv-to-xfopencv.md)
+
+<hr/>
+<p align="center"><sup>Copyright&copy; 2018 Xilinx</sup></p>

opencv-to-xfopencv-migration-tutorial/images/accel_out.png

@@ -183,7 +183,7 @@ Concat Block (PL)
 
     Alternatively, you can click the Add IP button (**+**) on the IP integrator canvas.
 
-    ![](/images/image13.png)
+    ![](./images/image13.png)
 
 2. The IP catalog **Search** dialog box appears. In the Search field, type **zynq** to find the ZYNQ7 Processing System IP.
 
@@ -529,20 +529,22 @@ You can now generate the HDL files for the design.
 
     ![](./images/image42.png)
 
-4. Create an top-level HDL wrapper for the IP integrator block design.
-
-5. Right-click on **zynq7_board.bd** in Sources window and click on **Create HDL Wrapper**.
+4. Right-click on **zynq7_board.bd** in Sources window and click on **Create HDL Wrapper**  to create a top-level HDL wrapper for the IP integrator block design.
 
    ![](./images/image43.png)
 
-6. Click **OK**.
+5. Click **OK**.
 
     ![](./images/image44.png)
 
-7. In the Flow Navigator, click **Generate Bitstream**.
+6. In the Flow Navigator, click **Generate Bitstream**.
+
+7. Click **File > Export > Export Hardware**.
+
+8. Select the **Include Bitstream** checkbox.
 
 
-> You now have a Zynq-7000 SoC bitstream that includes a hardware design without any SDSoC accelerators. This bitstream can be used as a check of hardware functionality prior to running the design through the SDx IDE to generate hardware accelerators.
+> You now have a Zynq-7000 SoC bitstream that includes a hardware design without any SDSoC accelerators. This bitstream can be used as a check of hardware functionality before running the design through the SDx IDE to generate hardware accelerators.
 </details>
 
 <details>

opencv-to-xfopencv-migration-tutorial/images/application_project_dialog.png

@@ -17,9 +17,9 @@
 </div>
 
 
-## Lab 3: Creating a Custom Platform Using the SDx IDE
+## Lab 3: Creating a Custom Platform Using the SDx&trade; IDE
 
-<details><summary><big><strong>Step 1: Invoking the SDx&trade; IDE and Creating a Platform Project</strong></big></summary>
+<details><summary><big><strong>Step 1: Invoking the SDx IDE and Creating a Platform Project</strong></big></summary>
 
 #### On a Linux host machine:
 
@@ -60,21 +60,21 @@ For a Windows host machine, use one of the following methods to launch Vivado&re
 
    As an alternative, the SDx IDE menu selection **File \> New \> SDx Project** can be used.
 
-1.  Select **Platform** on the Project Type dialog.
+1. Select **Platform** on the Project Type dialog.
 
    ![](./images/image70.png)
 
-    We will create an SDSoC&trade; platform and populate it with the hardware and software components we created in the earlier labs.
+   You will create an SDSoC&trade; platform and populate it with the hardware and software components created in the earlier labs.
 
-2. Click **Next**.
+1. Click **Next**.
 
-3.  On the Platform Specification dialog.
+1.  On the Platform Specification dialog.
 
     1. Click **Browse** to select **/tmp/sdx\_workspace/zynq7\_board.dsa** for the Hardware specification file.
 
     1. Leave the default to select Import software platform components.
 
-4. Click **Finish**.
+1. Click **Finish**.
 
    ![](./images/image71.png)
 </details>