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Ariane Cache #61
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Thank you for your interest @jctullos. This branch is still not stable, but it supports already Linux booting with one Ariane core and the cache hierarchy present. In addition, all accelerators coherence models (non-coherent DMA, LLC-coherent DMA, coherent DMA and fully-coherent mode) are working properly. In order to enable multi-core, however, we must first change the Ariane L1 and bus interfaces to enable L1 cache invalidation. Once this edit is complete and merged to the upstream repository in Ariane, we will be able to merge the feature in ESP as well. |
@paulmnt Oh that's perfect, thank you for the response! For my research, I only need 1 core instantiated. I will check out the branch and see how it does! One last question, does ESP incorporate the Ariane changes to add PMP from around 14 July? |
Not yet, but I plan to bump Ariane before changing its code.
After you pull, most likely you will have to apply minor patches to the following files:
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Thank you for the information. I was able to build and boot on the VCU118 before doing an Ariane bump. But Linux had some problems. It gets through the bootup until mounting a files system and I get this error: It happens each time I try to boot. I'm assuming it's having trouble with the initramfs. Have you seen this before? |
Hi, It seems you don't have the full file system, that happens when you don't run the If you run applications bin dev etc init lib lib64 linuxrc media mnt opt proc root run sbin sys tmp usr var Instead, if you didn't run the script correctly you will get this: etc usr The instructions for running the script are here: https://www.esp.cs.columbia.edu/docs/setup/setup-guide/#software-toolchain. |
Thanks @davide-giri ! I was in the process of running the riscv scripts as you posted that. I already had the tools built for another build, but figured there's added things that ESP includes. After deleting the sysroot folder and running make-linux again, all the folders show up now. Once it loads, I'll let you know if it works! |
It worked! Was able to reach login. Thank you both! |
Perfect! If you have already installed the toolchain once on a machine, you just have to repeat the third step of the
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Am I able to change the ram size easily? The build only has 500mb, but the vcu118 has extra I'd like to use. |
The current setup builds with 1GB of addressable DRAM, of which 512MB are cached in Ariane's L1 and used by the OS (`0x80000000 - 0xA0000000). You may easily expand the OS memory up to almost 2GB (0x80000000 - 0xF8000000). For the time being, if 2GB can do, edit these lines DRAMLength => X"0000_0000_7800_0000",
DRAMCachedLength => X"0000_0000_7800_0000") This setup will not leave any area for the ESP allocator, so ESP accelerators will not work correctly, not even in fully-coherent mode, because Ariane is still missing the invalidate interface for the L1. If you wish to preserve some area for accelerators, reduce the Note that after changing these parameters, you need to update the device tree Optionally, you can update the size of the available DRAM for the bootloader as well. |
We've added an If you don't want those to be loaded at all, you can remove |
Ah thank you! And sorry for so many questions! I didn't see any documentation for changing the CPU frequency. If I change the freq in top.vhd to 100MHz instead of 78, are there any additional changes I would make that would affect either the UART or Ethernet clocks? I synthesized the build and at first glance, everything was generated correctly. No issues with timing on the design. I'm remaking Linux right now to test it. |
We are happy to answer questions, no worries! We have set frequencies on all boards to make sure that most designs will meet timing, regardless of the number of accelerator tiles that you add and considering the performance achievable by the third-party IPs (such as Ariane). Having said that, changing the If you want to change the frequency of the design, then you must also edit the constraint files. For VCU118, for example, all constraints and pin allocations are stored in the folder set_property -dict [list \
CONFIG.C0_CLOCK_BOARD_INTERFACE {default_250mhz_clk1} \
CONFIG.C0.DDR4_TimePeriod {1600} \
CONFIG.C0.DDR4_InputClockPeriod {4000} \
CONFIG.C0.DDR4_CLKOUT0_DIVIDE {8} \
CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-083E} \
CONFIG.C0.DDR4_DataWidth {64} \
CONFIG.C0.DDR4_DataMask {DM_NO_DBI} \
CONFIG.C0.DDR4_Ordering {Strict} \
CONFIG.C0.DDR4_CasLatency {9} \
CONFIG.C0.DDR4_CasWriteLatency {9} \
CONFIG.C0.DDR4_Mem_Add_Map {BANK_ROW_COLUMN} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {78} \ # EDIT THIS LINE to change Ariane's clock
CONFIG.C0.BANK_GROUP_WIDTH {1}\
] [get_ips mig] After applying this change, make sure to run |
That's great! I'll try it out later. FYI, bumping the Ariane submodule so that I can include PMP works! The files you mentioned earlier were exactly the ones needing to be patched. Nothing needed to be changed in ariane_soc_pkg.sv file. |
Great and thank you for letting me know! |
Hi, did you went through the whole process, from building bootroom, bbl to vmlinux? |
Hey Kendidi, I used the whole process. You can build bbl and Linux without generating the entire bitstream. But it has configurations and patches specific to ESP, so it probably wouldn't work on other builds. |
Hi Jctullos, I see. I do not have the Xilinx license to build bitfiles. Would be nice if they have pre-built bit files for Ariane on Xilinx VCU128. |
Hi @Kendidi, I have uploaded on the ESP website the pre-built files for the Xilinx VCU128 board for an SoC with 1 Ariane core. You can find it here https://www.esp.cs.columbia.edu/prebuilt/singlecore/ with the name The guide on how to design and use a single core ESP SoC is here: https://www.esp.cs.columbia.edu/docs/singlecore/singlecore-guide. At the bottom, the guide includes the instructions on how to use the prebuilt material. Please, let us know if you have any further question. Thank you! |
Yes, the generated bbl file can be used for Ariane's SD card boot. The patches in Linux and BBL are simply adding support for peripherals from GRLIB, which we use in ESP. Other than that, both Linux and BBL are not modified. Please note that ESP drivers are not necessary with the CVA6 design, so you can remove their init scripts from the sysroot/etc/init.d to avoid error messages after boot completes. The scripts are S64 and S65. After removing them, you just need to recompile with 'make linux'. |
Thank you @davide-giri !! I will check it out. Appreciate it. Hi @paulmnt, the Xilinx VCU128 board I have has no SD card slot. It has jTAG support though. Can I use OpenOCD & GDB to load the bbl (with vmlinux embedded) to certain memory address and run instead? |
Hi @Kendidi When I mentioned the SD card, I was referring to the FPGA bit built with the CVA6 repo. Their default flow to run on FPGA relies on SD card and, for that flow, you may use the bbl image built within ESP, instead of the image built with Ariane SDK. Instead, if you use the ESP prebuilt image that @davide-giri created, you only need to connect the VCU128 to the same local Ethernet network of your computer and use the included We are not relying on GDB to load programs. Instead, ESP has an Ethernet link based on the GRLIB EDCL IP, which allows for faster boot. The ESP guide to configure the debug link describes a couple of options to get the connection with the FPGA working. I recommend using a router, if available, but the direct link does work as well. If you use a router, your computer can connect to it via Wi-Fi, while the FPGA must use a cable. The prebuilt image for VCU128 is configured as follows:
Whether you're using a router or a direct link with your computer NIC, it is possible to configure DHCP such that 192.168.1.12 is a valid IP. When you run the
Please let us know if you have troubles booting the system. Thank you! |
Thank you @paulmnt for the detailed information. I will try it out. |
I am curious which FPGA board have you been using? |
I've been using the VCU118. But having some trouble with Linux again. It's hanging now between BBL and Linux. I was having the same proble with the openpiton build. I wonder if it's because of PMP, there might be an issue with it. |
Just a clarification, the pre-built material for the single-core SoC tutorial does not contain the |
Ooh, I see. Thank you @davide-giri !! |
I am looking into the PMP implementation in Ariane. The objective is to track which new information is exposed (if any) to the bus to "tag" the address accesses. Or, at least, to see if there is any of the recent change is likely trigger it. |
Thank you @paulmnt very much for your help!! It works. FPGA was programmed, binary files were loaded and Kernel was running all the way to the "esp login" prompt. Are the pre-built files using the latest source code? I wonder if I build files from scratch, will it be able to boot again or will I encounter the PMP issue. Thanks. |
That's great news @Kendidi ! The prebuilt for VCU128 uses the latest commit on the |
Cool! So which Ariane repository ESP is pointing to? Thanks. |
The repo is the same, but it's pointing to an older commit: 465bb209a "wt_cache_subsystem: Fix spelling mistakes (#453)" |
Thanks @paulmnt ! As an experiment, I tried to build from existing ESP source code on my system and see if the generated files work or not.
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This happened to me earlier, it's due to not running the script build_riscv_toolchain, make sure to run that in the utils/scripts directory. It builds RISCV and buildroot, which builds the initramfs system. |
Ohh. I see. I will run it. Thanks @jctullos ! |
Correct, that step is part of the setup guide: https://www.esp.cs.columbia.edu/docs/setup/setup-guide/#software-toolchain. |
I followed the steps from the beginning but have trouble installing the toolchain. Folder "/opt/riscv/bin" was not installed. There is only a "sysroot" folder under "/opt/riscv/". Please advise.
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The error you are reporting is the consequence of a previous error, what's the first error you get? |
OK. Backtracking the toolchian installation process showed that package "bison" was missing. Now it appears something is being installing because the system responses very very slowly and the disk drive LED keeps flashing. Thanks! |
It went a lot further and then encountered a lot of "g++: internal compiler error: Killed (program cc1plus)".
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It's possible your system ran out of memory. If you run |
Yup, Out of Memory. I did not specify. I just pressed "ENTER". dmesg:
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So my guess was right, there is an "out of memory". Pressing "ENTER" executes the default option, which is always listed between brackets. Specify 1 this time, that will be slow, but hopefully it will avoid the "out of memory" issue. |
Yup. You are right. I tried '4' and everything seems built OK. In my case (for a freshly installed Ubuntu 18.04 platform), I needed to run the following as well.
Thanks a lot for your help!! |
I run the bbl+Kernel built with ESP today against a bit file built from recent Ariane code and encountered the following.
The bbl+kernel built yesterday (w/o initramfs system built) did not encounter this. Could this be PMP related or something else? Thanks. |
The following is resulted from pre-built top.bit, prom.bit and systest.bin downloaded today, plus the linux.bin that I built today with "make linux". Please advise if I have missed any steps that may caused the PANIC? Thanks a lot in advance!
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This issue appears to be related to the changes I made to config file ariane_defconfig. After I reverted the changes and rebuilt linux.bin, it can boot successfully again. Thanks.. |
It appears riscv64-unknown-elf-gdb is not included in the toolchain build. Is it possible to enable it? Thanks. |
@Kendidi Yes, you would just enable it in the build toolchain script, if you go through it you'll see where it takes out GDB build so that it builds faster. |
@paulmnt I'm going to close this so it doesn't continue to build in messages. Sorry for so many different issues to jump into one github issue! |
Got it. Thank you! |
My bad. Sorry! But appreciate all your help!! |
Hello,
I saw on the website cache isn't implemented yet for Ariane. Is that still the case? Is there any branches that I could test out that uses cache?
Thank you!
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