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ntt_kyber_12_345_67_opt_speed_m85.s
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///
/// Copyright (c) 2021 Arm Limited
/// Copyright (c) 2022 Hanno Becker
/// Copyright (c) 2023 Amin Abdulrahman, Matthias Kannwischer
/// SPDX-License-Identifier: MIT
///
/// Permission is hereby granted, free of charge, to any person obtaining a copy
/// of this software and associated documentation files (the "Software"), to deal
/// in the Software without restriction, including without limitation the rights
/// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
/// copies of the Software, and to permit persons to whom the Software is
/// furnished to do so, subject to the following conditions:
///
/// The above copyright notice and this permission notice shall be included in all
/// copies or substantial portions of the Software.
///
/// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
/// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
/// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
/// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
/// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
/// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
/// SOFTWARE.
///
.data
.p2align 4
roots:
#include "ntt_kyber_12_345_67_twiddles.s"
.text
#define QSTACK4 (0*16)
#define QSTACK5 (1*16)
#define QSTACK6 (2*16)
#define STACK0 (3*16)
#define POS_ROOT_1 1
#define POS_ROOT_2 2
#define POS_ROOT_3 3
#define POS_ROOT_4 4
#define POS_ROOT_5 5
#define POS_ROOT_6 6
#define STACK_SIZE (3*16 + 8)
.macro qsave loc, a // slothy:no-unfold
vstrw.32 \a, [sp, #\loc\()]
.endm
.macro qrestore a, loc // slothy:no-unfold
vldrw.32 \a, [sp, #\loc\()]
.endm
.macro restored a, b, loc // slothy:no-unfold
ldrd \a, \b, [sp, #\loc\()]
.endm
.macro saved loc, a, b // slothy:no-unfold
strd \a, \b, [sp, #\loc\()]
.endm
.macro restore a, loc // slothy:no-unfold
ldr \a, [sp, #\loc\()]
.endm
.macro save loc, a // slothy:no-unfold
str \a, [sp, #\loc\()]
.endm
// Barrett multiplication
.macro mulmod dst, src, const, const_tw
vmul.s16 \dst, \src, \const
vqrdmulh.s16 \src, \src, \const_tw
vmla.s16 \dst, \src, modulus
.endm
.macro ct_butterfly a, b, root, root_tw
mulmod tmp, \b, \root, \root_tw
vsub.u16 \b, \a, tmp
vadd.u16 \a, \a, tmp
.endm
// Aligns stack =0 mod 16
.macro align_stack_do // slothy:no-unfold
mov r11, sp
and r12, r11, #0xC
sub sp, sp, r12 // Align stack to 16 byte
sub sp, sp, #16
str r12, [sp]
.endm
// Reverts initial stack correction
.macro align_stack_undo // slothy:no-unfold
ldr r12, [sp]
add sp, sp, #16
add sp, sp, r12
.endm
.align 4
roots_addr: .word roots
.syntax unified
.type ntt_kyber_12_345_67_opt_speed_m85, %function
.global ntt_kyber_12_345_67_opt_speed_m85
modulus .req r12
r_ptr .req r11
.equ modulus_const, -3329
in .req r0
inp .req r1
in_low .req r0
in_high .req r1
root0 .req r2
root0_tw .req r3
root1 .req r4
root1_tw .req r5
root2 .req r6
root2_tw .req r7
data0 .req q0
data1 .req q1
data2 .req q2
data3 .req q3
data4 .req q1
data5 .req q2
data6 .req q3
data7 .req q4
tmp .req q7
rtmp .req r3
rtmp_tw .req r4
qtmp .req q5
qtmp_tw .req q6
ntt_kyber_12_345_67_opt_speed_m85:
push {r4-r11,lr}
// Save MVE vector registers
vpush {d8-d15}
align_stack_do
sub sp, sp, #STACK_SIZE
movw modulus, #:lower16:modulus_const
ldr r_ptr, roots_addr
// Layers 1,2
save STACK0, in
add in_high, in_low, #(2*128)
ldrd root0, root0_tw, [r_ptr], #+24
ldrd root1, root1_tw, [r_ptr, #-16]
ldrd root2, root2_tw, [r_ptr, #-8]
mov lr, #8
.p2align 2
vldrw.32 q5, [r1] // *.
vmul.s16 q4, q5, r2 // .*
// original source code
// vldrw.32 q5, [r1] // *.
// vmul.s16 q4, q5, r2 // .*
sub lr, lr, #1
.p2align 2
layer12_loop:
vqrdmulh.s16 q2, q5, r3 // .....*......................
vldrw.32 q3, [r1, #128] // ...*........................
vqrdmulh.s16 q5, q3, r3 // ..........*.................
vldrw.32 q0, [r0] // *...........................
vmul.s16 q1, q3, r2 // .........*..................
vldrw.32 q6, [r0, #128] // .*..........................
vmla.s16 q1, q5, r12 // ...........*................
vldrw.32 q5, [r1, #16] // ..e.........................
vmla.s16 q4, q2, r12 // ......*.....................
vadd.u16 q2, q6, q1 // .............*..............
vmul.s16 q3, q2, r4 // ..............*.............
vsub.u16 q7, q0, q4 // .......*....................
vqrdmulh.s16 q2, q2, r5 // ...............*............
vadd.u16 q0, q0, q4 // ........*...................
vmla.s16 q3, q2, r12 // ................*...........
vsub.u16 q6, q6, q1 // ............*...............
vmul.s16 q1, q6, r6 // ...................*........
vadd.u16 q4, q0, q3 // ..................*.........
vqrdmulh.s16 q2, q6, r7 // ....................*.......
vsub.u16 q6, q0, q3 // .................*..........
vmla.s16 q1, q2, r12 // .....................*......
vstrw.u32 q4, [r0] , #16 // ........................*...
vsub.u16 q3, q7, q1 // ......................*.....
vstrw.u32 q6, [r0, #112] // .........................*..
vadd.u16 q2, q7, q1 // .......................*....
vstrw.u32 q2, [r1] , #16 // ..........................*.
vmul.s16 q4, q5, r2 // ....e.......................
vstrw.u32 q3, [r1, #112] // ...........................*
// original source code
// vldrw.32 q0, [r0] // ........................*........................
// vldrw.32 q1, [r0, #128] // ..........................*......................
// vldrw.32 q2, [r1] // e................................................
// vldrw.32 q3, [r1, #128] // ......................*..........................
// vmul.s16 q7, q2, r2 // ...................e.............................
// vqrdmulh.s16 q2, q2, r3 // .....................*...........................
// vmla.s16 q7, q2, r12 // .............................*...................
// vsub.u16 q2, q0, q7 // ................................*................
// vadd.u16 q0, q0, q7 // ..................................*..............
// vmul.s16 q7, q3, r2 // .........................*.......................
// vqrdmulh.s16 q3, q3, r3 // .......................*.........................
// vmla.s16 q7, q3, r12 // ...........................*.....................
// vsub.u16 q3, q1, q7 // ....................................*............
// vadd.u16 q1, q1, q7 // ..............................*..................
// vmul.s16 q7, q1, r4 // ...............................*.................
// vqrdmulh.s16 q1, q1, r5 // .................................*...............
// vmla.s16 q7, q1, r12 // ...................................*.............
// vsub.u16 q1, q0, q7 // ........................................*........
// vadd.u16 q0, q0, q7 // ......................................*..........
// vmul.s16 q7, q3, r6 // .....................................*...........
// vqrdmulh.s16 q3, q3, r7 // .......................................*.........
// vmla.s16 q7, q3, r12 // .........................................*.......
// vsub.u16 q3, q2, q7 // ...........................................*.....
// vadd.u16 q2, q2, q7 // .............................................*...
// vstrw.u32 q0, [r0] , #16 // ..........................................*......
// vstrw.u32 q1, [r0, #112] // ............................................*....
// vstrw.u32 q2, [r1] , #16 // ..............................................*..
// vstrw.u32 q3, [r1, #112] // ................................................*
le lr, layer12_loop
layer12_loop_end:
mov r14, #3 // ...........................*............................................
vqrdmulh.s16 q0, q5, r3 // *.......................................................................
vldrw.32 q7, [r1, #128] // .*......................................................................
vmul.s16 q2, q7, r2 // ....*...................................................................
vldrw.32 q1, [r0] // ...*....................................................................
vqrdmulh.s16 q5, q7, r3 // ..*.....................................................................
vldrw.32 q3, [r0, #128] // .....*..................................................................
vmla.s16 q2, q5, r12 // ......*.................................................................
ldrd r9, r3, [r11] , #56 // ............................*...........................................
vmla.s16 q4, q0, r12 // .......*................................................................
vadd.u16 q7, q3, q2 // ........*...............................................................
vqrdmulh.s16 q6, q7, r5 // ...........*............................................................
vsub.u16 q5, q3, q2 // ..............*.........................................................
vmul.s16 q3, q7, r4 // .........*..............................................................
vadd.u16 q0, q1, q4 // ............*...........................................................
vmla.s16 q3, q6, r12 // .............*..........................................................
vsub.u16 q2, q1, q4 // ..........*.............................................................
vqrdmulh.s16 q7, q5, r7 // .................*......................................................
vadd.u16 q1, q0, q3 // ................*.......................................................
vstrw.u32 q1, [r0] , #16 // ..................*.....................................................
vsub.u16 q3, q0, q3 // ....................*...................................................
vmul.s16 q4, q5, r6 // ...............*........................................................
vstrw.u32 q3, [r0, #112] // .....................*..................................................
vmla.s16 q4, q7, r12 // ...................*....................................................
restore r0, STACK0 // ..........................*.............................................
vadd.u16 q6, q2, q4 // ........................*...............................................
vldrw.32 q3, [r0, #96] // ...............................*........................................
vstrw.u32 q6, [r1] , #16 // .........................*..............................................
vqrdmulh.s16 q1, q3, r3 // ................................*.......................................
vldrw.32 q6, [r0, #64] // .............................*..........................................
vmul.s16 q7, q6, r9 // ..............................*.........................................
vsub.u16 q4, q2, q4 // ......................*.................................................
vldrw.32 q5, [r0, #32] // .................................*......................................
vmul.s16 q2, q3, r9 // ..................................*.....................................
ldrd r2, r10, [r11, #8*POS_ROOT_1 - 56] // .....................................*..................................
vmla.s16 q2, q1, r12 // ....................................*...................................
vldrw.32 q3, [r0] // ...................................*....................................
vqrdmulh.s16 q0, q6, r3 // ......................................*.................................
vadd.u16 q6, q5, q2 // .......................................*................................
vqrdmulh.s16 q1, q6, r10 // ..........................................*.............................
vsub.u16 q5, q5, q2 // .........................................*..............................
vmla.s16 q7, q0, r12 // ........................................*...............................
ldrd r7, r8, [r11, #8*POS_ROOT_4 - 56] // .....................................................*..................
vmul.s16 q6, q6, r2 // ............................................*...........................
vsub.u16 q0, q3, q7 // ...........................................*............................
vmla.s16 q6, q1, r12 // ..............................................*.........................
vadd.u16 q7, q3, q7 // .......................................................*................
vldrw.32 q1, [r0, #80] // ...............................................*........................
vmul.s16 q3, q1, r9 // ..................................................*.....................
vadd.u16 q2, q7, q6 // ..............................................................*.........
vqrdmulh.s16 q1, q1, r3 // ................................................*.......................
vsub.u16 q6, q7, q6 // .........................................................*..............
vmla.s16 q3, q1, r12 // ......................................................*.................
vldrw.32 q7, [r0, #112] // ...................................................*....................
vmul.s16 q1, q7, r9 // ........................................................*...............
vstrw.u32 q4, [r1, #112] // .......................*................................................
vqrdmulh.s16 q4, q7, r3 // ....................................................*...................
vldrw.32 q7, [r0, #48] // ...........................................................*............
vmla.s16 q1, q4, r12 // ..........................................................*.............
qsave QSTACK4, q0 // .................................................*......................
vsub.u16 q4, q7, q1 // ............................................................*...........
vmul.s16 q0, q4, r7 // ...............................................................*........
vadd.u16 q1, q7, q1 // ..................................................................*.....
vqrdmulh.s16 q7, q4, r8 // .............................................................*..........
qsave QSTACK6, q5 // .............................................*..........................
vmul.s16 q5, q1, r2 // .....................................................................*..
vldrw.32 q4, [r0, #16] // ................................................................*.......
vmla.s16 q0, q7, r12 // .................................................................*......
vadd.u16 q7, q4, q3 // ......................................................................*.
vqrdmulh.s16 q1, q1, r10 // ...................................................................*....
vsub.u16 q3, q4, q3 // ....................................................................*...
vmla.s16 q5, q1, r12 // .......................................................................*
// original source code
// vqrdmulh.s16 q7, q5, r3 // .*......................................................................
// vldrw.32 q1, [r1, #128] // ..*.....................................................................
// vqrdmulh.s16 q0, q1, r3 // .....*..................................................................
// vldrw.32 q6, [r0] // ....*...................................................................
// vmul.s16 q1, q1, r2 // ...*....................................................................
// vldrw.32 q5, [r0, #128] // ......*.................................................................
// vmla.s16 q1, q0, r12 // .......*................................................................
// vmla.s16 q4, q7, r12 // .........*..............................................................
// vadd.u16 q7, q5, q1 // ..........*.............................................................
// vmul.s16 q0, q7, r4 // .............*..........................................................
// vsub.u16 q3, q6, q4 // ................*.......................................................
// vqrdmulh.s16 q7, q7, r5 // ...........*............................................................
// vadd.u16 q6, q6, q4 // ..............*.........................................................
// vmla.s16 q0, q7, r12 // ...............*........................................................
// vsub.u16 q7, q5, q1 // ............*...........................................................
// vmul.s16 q1, q7, r6 // .....................*..................................................
// vadd.u16 q5, q6, q0 // ..................*.....................................................
// vqrdmulh.s16 q7, q7, r7 // .................*......................................................
// vstrw.u32 q5, [r0] , #16 // ...................*....................................................
// vmla.s16 q1, q7, r12 // .......................*................................................
// vsub.u16 q7, q6, q0 // ....................*...................................................
// vstrw.u32 q7, [r0, #112] // ......................*.................................................
// vsub.u16 q7, q3, q1 // ...............................*........................................
// vstrw.u32 q7, [r1, #128] // .......................................................*................
// vadd.u16 q7, q3, q1 // .........................*..............................................
// vstrw.u32 q7, [r1] , #16 // ...........................*............................................
// restore r0, STACK0 // ........................*...............................................
// mov r14, #3 // *.......................................................................
// ldrd r3, r2, [r11] , #56 // ........*...............................................................
// vldrw.32 q1, [r0, #64] // .............................*..........................................
// vmul.s16 q6, q1, r3 // ..............................*.........................................
// vldrw.32 q5, [r0, #96] // ..........................*.............................................
// vqrdmulh.s16 q2, q5, r2 // ............................*...........................................
// vldrw.32 q4, [r0, #32] // ................................*.......................................
// vmul.s16 q0, q5, r3 // .................................*......................................
// vldrw.32 q5, [r0] // ....................................*...................................
// vmla.s16 q0, q2, r12 // ...................................*....................................
// ldrd r9, r5, [r11, #8*POS_ROOT_1 - 56] // ..................................*.....................................
// vqrdmulh.s16 q3, q1, r2 // .....................................*..................................
// vadd.u16 q2, q4, q0 // ......................................*.................................
// vmla.s16 q6, q3, r12 // .........................................*..............................
// vsub.u16 q4, q4, q0 // ........................................*...............................
// vqrdmulh.s16 q1, q2, r5 // .......................................*................................
// vsub.u16 q3, q5, q6 // ............................................*...........................
// vmul.s16 q2, q2, r9 // ...........................................*............................
// qsave QSTACK6, q4 // ................................................................*.......
// vmla.s16 q2, q1, r12 // .............................................*..........................
// vldrw.32 q0, [r0, #80] // ...............................................*........................
// vqrdmulh.s16 q7, q0, r2 // ..................................................*.....................
// qsave QSTACK4, q3 // ...........................................................*............
// vmul.s16 q1, q0, r3 // ................................................*.......................
// vldrw.32 q0, [r0, #112] // .....................................................*..................
// vqrdmulh.s16 q4, q0, r2 // ........................................................*...............
// ldrd r7, r8, [r11, #8*POS_ROOT_4 - 56] // ..........................................*.............................
// vmla.s16 q1, q7, r12 // ....................................................*...................
// vadd.u16 q7, q5, q6 // ..............................................*.........................
// vmul.s16 q5, q0, r3 // ......................................................*.................
// vsub.u16 q6, q7, q2 // ...................................................*....................
// vmla.s16 q5, q4, r12 // ..........................................................*.............
// vldrw.32 q3, [r0, #48] // .........................................................*..............
// vsub.u16 q0, q3, q5 // ............................................................*...........
// vqrdmulh.s16 q4, q0, r8 // ...............................................................*........
// vadd.u16 q2, q7, q2 // .................................................*......................
// vmul.s16 q0, q0, r7 // .............................................................*..........
// vldrw.32 q7, [r0, #16] // ..................................................................*.....
// vmla.s16 q0, q4, r12 // ...................................................................*....
// vadd.u16 q5, q3, q5 // ..............................................................*.........
// vqrdmulh.s16 q4, q5, r5 // .....................................................................*..
// vsub.u16 q3, q7, q1 // ......................................................................*.
// vmul.s16 q5, q5, r9 // .................................................................*......
// vadd.u16 q7, q7, q1 // ....................................................................*...
// vmla.s16 q5, q4, r12 // .......................................................................*
layer345_loop:
ldrd r9, r5, [r11, #8*POS_ROOT_3 - 56] // .......*.................................................................................
vsub.u16 q1, q7, q5 // .........*...............................................................................
vmul.s16 q4, q1, r9 // ..............*..........................................................................
vadd.u16 q7, q7, q5 // .*.......................................................................................
vqrdmulh.s16 q5, q1, r5 // ............*............................................................................
qsave QSTACK5, q3 // *........................................................................................
vmla.s16 q4, q5, r12 // ................*........................................................................
qrestore q3, QSTACK6 // .......................*.................................................................
vsub.u16 q5, q6, q4 // ...................*.....................................................................
vqrdmulh.s16 q1, q3, r8 // ..........................*..............................................................
vadd.u16 q4, q6, q4 // .........................*...............................................................
vmul.s16 q6, q3, r7 // ........................*................................................................
vstrw.u32 q5, [r0, #48] // .....................*...................................................................
vmla.s16 q6, q1, r12 // ............................*............................................................
qrestore q1, QSTACK4 // .............................*...........................................................
vadd.u16 q3, q1, q6 // ...............................*.........................................................
ldrd r9, r1, [r11, #8*POS_ROOT_5 - 56] // .............*...........................................................................
vsub.u16 q6, q1, q6 // .......................................*.................................................
ldrd r4, r3, [r11, #8*POS_ROOT_2 - 56] // ....*....................................................................................
vstrw.u32 q4, [r0, #32] // ...........................*.............................................................
vqrdmulh.s16 q4, q7, r3 // ........*................................................................................
qrestore q5, QSTACK5 // ..*......................................................................................
vsub.u16 q1, q5, q0 // ...*.....................................................................................
vmul.s16 q7, q7, r4 // ......*..................................................................................
ldrd r5, r10, [r11, #8*POS_ROOT_6 - 56] // ...........*.............................................................................
vmla.s16 q7, q4, r12 // ..........*..............................................................................
vadd.u16 q0, q5, q0 // .....*...................................................................................
vmul.s16 q5, q1, r5 // ..............................*..........................................................
vadd.u16 q4, q2, q7 // ...............*.........................................................................
vqrdmulh.s16 q1, q1, r10 // ................................*........................................................
vsub.u16 q7, q2, q7 // .................................*.......................................................
vmla.s16 q5, q1, r12 // ..................................*......................................................
vldrw.32 q1, [r0, #192] // ..............................................*..........................................
vsub.u16 q2, q6, q5 // .........................................*...............................................
vstrw.u32 q2, [r0, #112] // ..........................................*..............................................
vadd.u16 q2, q6, q5 // ...........................................*.............................................
vqrdmulh.s16 q5, q0, r1 // ....................*....................................................................
vstrw.u32 q4, [r0] , #128 // .................*.......................................................................
vmul.s16 q4, q0, r9 // ..................*......................................................................
vstrw.u32 q2, [r0, #-32] // ............................................*............................................
vmla.s16 q4, q5, r12 // ......................*..................................................................
ldrd r4, r3, [r11] , #56 // .............................................*...........................................
vadd.u16 q0, q3, q4 // ...................................*.....................................................
vmul.s16 q2, q1, r4 // ...............................................*.........................................
vsub.u16 q5, q3, q4 // .....................................*...................................................
vqrdmulh.s16 q4, q1, r3 // .......................................................*.................................
vstrw.u32 q0, [r0, #-64] // ........................................*................................................
vmla.s16 q2, q4, r12 // .........................................................*...............................
vldrw.32 q0, [r0] // ....................................................*....................................
vsub.u16 q1, q0, q2 // ............................................................*............................
qsave QSTACK4, q1 // ..................................................................*......................
vldrw.32 q3, [r0, #80] // ................................................................*........................
vmul.s16 q1, q3, r4 // ...................................................................*.....................
vldrw.32 q6, [r0, #96] // ................................................*........................................
vqrdmulh.s16 q3, q3, r3 // .................................................................*.......................
vstrw.u32 q5, [r0, #-48] // ......................................*..................................................
vmul.s16 q5, q6, r4 // ...................................................*.....................................
ldrd r9, r1, [r11, #8*POS_ROOT_1 - 56] // ......................................................*..................................
vmla.s16 q1, q3, r12 // .......................................................................*.................
vstrw.u32 q7, [r0, #-112] // ....................................*....................................................
vqrdmulh.s16 q7, q6, r3 // .................................................*.......................................
vldrw.32 q4, [r0, #112] // ....................................................................*....................
vmla.s16 q5, q7, r12 // .....................................................*...................................
vldrw.32 q3, [r0, #32] // ..................................................*......................................
vmul.s16 q6, q4, r4 // .........................................................................*...............
vsub.u16 q7, q3, q5 // ..........................................................*..............................
vqrdmulh.s16 q4, q4, r3 // .....................................................................*...................
vadd.u16 q3, q3, q5 // ........................................................*................................
vmla.s16 q6, q4, r12 // ...........................................................................*.............
qsave QSTACK6, q7 // ..............................................................*..........................
vldrw.32 q7, [r0, #48] // ............................................................................*............
vadd.u16 q4, q7, q6 // ...................................................................................*.....
vmul.s16 q5, q4, r9 // ......................................................................................*..
vadd.u16 q2, q0, q2 // ........................................................................*................
vqrdmulh.s16 q0, q4, r1 // ....................................................................................*....
ldrd r7, r8, [r11, #8*POS_ROOT_4 - 56] // ......................................................................*..................
vmla.s16 q5, q0, r12 // ........................................................................................*
vsub.u16 q0, q7, q6 // .............................................................................*...........
vqrdmulh.s16 q6, q3, r1 // ...........................................................*.............................
vldrw.32 q7, [r0, #16] // .................................................................................*.......
vmul.s16 q4, q3, r9 // .............................................................*...........................
vsub.u16 q3, q7, q1 // .....................................................................................*...
vmla.s16 q4, q6, r12 // ...............................................................*.........................
vadd.u16 q7, q7, q1 // .......................................................................................*.
vqrdmulh.s16 q1, q0, r8 // ..............................................................................*..........
vsub.u16 q6, q2, q4 // ..........................................................................*..............
vmul.s16 q0, q0, r7 // ................................................................................*........
vadd.u16 q2, q2, q4 // ...............................................................................*.........
vmla.s16 q0, q1, r12 // ..................................................................................*......
// original source code
// qsave QSTACK5, q3 // .....*...................................................................................
// vadd.u16 q3, q7, q5 // ...*.....................................................................................
// qrestore q4, QSTACK5 // .....................*...................................................................
// vsub.u16 q1, q4, q0 // ......................*..................................................................
// ldrd r3, r5, [r11, #8*POS_ROOT_2 - 56] // ..................*......................................................................
// vadd.u16 q4, q4, q0 // ..........................*..............................................................
// vmul.s16 q0, q3, r3 // .......................*.................................................................
// ldrd r6, r10, [r11, #8*POS_ROOT_3 - 56] // *........................................................................................
// vqrdmulh.s16 q3, q3, r5 // ....................*....................................................................
// vsub.u16 q5, q7, q5 // .*.......................................................................................
// vmla.s16 q0, q3, r12 // .........................*...............................................................
// ldrd r2, r1, [r11, #8*POS_ROOT_6 - 56] // ........................*................................................................
// vqrdmulh.s16 q7, q5, r10 // ....*....................................................................................
// ldrd r5, r4, [r11, #8*POS_ROOT_5 - 56] // ................*........................................................................
// vmul.s16 q3, q5, r6 // ..*......................................................................................
// vadd.u16 q5, q2, q0 // ............................*............................................................
// vmla.s16 q3, q7, r12 // ......*..................................................................................
// vstrw.u32 q5, [r0] , #128 // .....................................*...................................................
// vmul.s16 q7, q4, r5 // ......................................*..................................................
// vsub.u16 q5, q6, q3 // ........*................................................................................
// vqrdmulh.s16 q4, q4, r4 // ....................................*....................................................
// vstrw.u32 q5, [r0, #-80] // ............*............................................................................
// vmla.s16 q7, q4, r12 // ........................................*................................................
// qrestore q4, QSTACK6 // .......*.................................................................................
// vmul.s16 q5, q4, r7 // ...........*.............................................................................
// vadd.u16 q3, q6, q3 // ..........*..............................................................................
// vqrdmulh.s16 q4, q4, r8 // .........*...............................................................................
// vstrw.u32 q3, [r0, #-96] // ...................*.....................................................................
// vmla.s16 q5, q4, r12 // .............*...........................................................................
// qrestore q3, QSTACK4 // ..............*..........................................................................
// vmul.s16 q4, q1, r2 // ...........................*.............................................................
// vadd.u16 q6, q3, q5 // ...............*.........................................................................
// vqrdmulh.s16 q1, q1, r1 // .............................*...........................................................
// vsub.u16 q0, q2, q0 // ..............................*..........................................................
// vmla.s16 q4, q1, r12 // ...............................*.........................................................
// vadd.u16 q1, q6, q7 // ..........................................*..............................................
// vstrw.u32 q0, [r0, #-112] // ...........................................................*.............................
// vsub.u16 q6, q6, q7 // ............................................*............................................
// vstrw.u32 q6, [r0, #-48] // .......................................................*.................................
// vsub.u16 q6, q3, q5 // .................*.......................................................................
// vstrw.u32 q1, [r0, #-64] // ..............................................*..........................................
// vsub.u16 q3, q6, q4 // .................................*.......................................................
// vstrw.u32 q3, [r0, #-16] // ..................................*......................................................
// vadd.u16 q1, q6, q4 // ...................................*.....................................................
// vstrw.u32 q1, [r0, #-32] // .......................................*.................................................
// ldrd r3, r2, [r11] , #56 // .........................................*...............................................
// vldrw.32 q1, [r0, #64] // ................................*........................................................
// vmul.s16 q6, q1, r3 // ...........................................*.............................................
// vldrw.32 q5, [r0, #96] // .....................................................*...................................
// vqrdmulh.s16 q2, q5, r2 // ............................................................*............................
// vldrw.32 q4, [r0, #32] // ...............................................................*.........................
// vmul.s16 q0, q5, r3 // ........................................................*................................
// vldrw.32 q5, [r0] // ................................................*........................................
// vmla.s16 q0, q2, r12 // ..............................................................*..........................
// ldrd r9, r5, [r11, #8*POS_ROOT_1 - 56] // .........................................................*...............................
// vqrdmulh.s16 q3, q1, r2 // .............................................*...........................................
// vadd.u16 q2, q4, q0 // ...................................................................*.....................
// vmla.s16 q6, q3, r12 // ...............................................*.........................................
// vsub.u16 q4, q4, q0 // .................................................................*.......................
// vqrdmulh.s16 q1, q2, r5 // ..............................................................................*..........
// vsub.u16 q3, q5, q6 // .................................................*.......................................
// vmul.s16 q2, q2, r9 // ................................................................................*........
// qsave QSTACK6, q4 // .....................................................................*...................
// vmla.s16 q2, q1, r12 // ..................................................................................*......
// vldrw.32 q0, [r0, #80] // ...................................................*.....................................
// vqrdmulh.s16 q7, q0, r2 // ......................................................*..................................
// qsave QSTACK4, q3 // ..................................................*......................................
// vmul.s16 q1, q0, r3 // ....................................................*....................................
// vldrw.32 q0, [r0, #112] // .............................................................*...........................
// vqrdmulh.s16 q4, q0, r2 // ..................................................................*......................
// ldrd r7, r8, [r11, #8*POS_ROOT_4 - 56] // ...........................................................................*.............
// vmla.s16 q1, q7, r12 // ..........................................................*..............................
// vadd.u16 q7, q5, q6 // .........................................................................*...............
// vmul.s16 q5, q0, r3 // ................................................................*........................
// vsub.u16 q6, q7, q2 // .....................................................................................*...
// vmla.s16 q5, q4, r12 // ....................................................................*....................
// vldrw.32 q3, [r0, #48] // ......................................................................*..................
// vsub.u16 q0, q3, q5 // .............................................................................*...........
// vqrdmulh.s16 q4, q0, r8 // ....................................................................................*....
// vadd.u16 q2, q7, q2 // .......................................................................................*.
// vmul.s16 q0, q0, r7 // ......................................................................................*..
// vldrw.32 q7, [r0, #16] // ...............................................................................*.........
// vmla.s16 q0, q4, r12 // ........................................................................................*
// vadd.u16 q5, q3, q5 // .......................................................................*.................
// vqrdmulh.s16 q4, q5, r5 // ..........................................................................*..............
// vsub.u16 q3, q7, q1 // .................................................................................*.......
// vmul.s16 q5, q5, r9 // ........................................................................*................
// vadd.u16 q7, q7, q1 // ...................................................................................*.....
// vmla.s16 q5, q4, r12 // ............................................................................*............
le lr, layer345_loop
layer345_loop_end:
qsave QSTACK5, q3 // *....................................................
qrestore q1, QSTACK6 // .......................*.............................
vmul.s16 q3, q1, r7 // ........................*............................
qrestore q4, QSTACK4 // .............................*.......................
vqrdmulh.s16 q1, q1, r8 // ..........................*..........................
restore r1, STACK0 // .............................................*.......
vmla.s16 q3, q1, r12 // ............................*........................
vadd.u16 q1, q7, q5 // .*...................................................
ldrd r6, r8, [r11, #8*POS_ROOT_2 - 56] // ....*................................................
vsub.u16 q7, q7, q5 // .........*...........................................
vmul.s16 q5, q1, r6 // ......*..............................................
ldrd r10, r6, [r11, #8*POS_ROOT_6 - 56] // ...........*.........................................
vqrdmulh.s16 q1, q1, r8 // ........*............................................
ldrd r8, r2, [r11, #8*POS_ROOT_3 - 56] // .......*.............................................
vmla.s16 q5, q1, r12 // ..........*..........................................
ldrd r4, r3, [r11, #8*POS_ROOT_5 - 56] // .............*.......................................
vadd.u16 q1, q2, q5 // ...............*.....................................
vstrw.u32 q1, [r0] , #128 // .................*...................................
vsub.u16 q1, q2, q5 // .................................*...................
qrestore q5, QSTACK5 // ..*..................................................
vsub.u16 q2, q5, q0 // ...*.................................................
vstrw.u32 q1, [r0, #-112] // ....................................*................
vadd.u16 q1, q5, q0 // .....*...............................................
vmul.s16 q5, q7, r8 // ..............*......................................
vadd.u16 q0, q4, q3 // ...............................*.....................
vqrdmulh.s16 q7, q7, r2 // ............*........................................
vsub.u16 q3, q4, q3 // .......................................*.............
vmla.s16 q5, q7, r12 // ................*....................................
mov r14, #7 // ..............................................*......
vsub.u16 q7, q6, q5 // ...................*.................................
vmul.s16 q4, q2, r10 // ..............................*......................
vadd.u16 q6, q6, q5 // .........................*...........................
vqrdmulh.s16 q5, q2, r6 // ................................*....................
vstrw.u32 q7, [r0, #-80] // .....................*...............................
vmla.s16 q4, q5, r12 // ..................................*..................
vstrw.u32 q6, [r0, #-96] // ...........................*.........................
vsub.u16 q7, q3, q4 // .........................................*...........
vmul.s16 q2, q1, r4 // ..................*..................................
vadd.u16 q6, q3, q4 // ...........................................*.........
vqrdmulh.s16 q1, q1, r3 // ....................*................................
vstrw.u32 q6, [r0, #-32] // ............................................*........
vld40.32 {q3,q4,q5,q6}, [r1] // ...............................................*.....
vmla.s16 q2, q1, r12 // ......................*..............................
vld41.32 {q3,q4,q5,q6}, [r1] // ................................................*....
vadd.u16 q1, q0, q2 // ...................................*.................
vstrw.u32 q7, [r0, #-16] // ..........................................*..........
vld42.32 {q3,q4,q5,q6}, [r1] // .................................................*...
vstrw.u32 q1, [r0, #-64] // ........................................*............
vld43.32 {q3,q4,q5,q6}, [r1]! // ..................................................*..
vsub.u16 q7, q0, q2 // .....................................*...............
vstrw.u32 q7, [r0, #-48] // ......................................*..............
vldrh.16 q7, [r11] , #96 // ...................................................*.
vmul.s16 q1, q6, q7 // ....................................................*
// original source code
// qsave QSTACK5, q3 // *....................................................
// vadd.u16 q3, q7, q5 // .......*.............................................
// qrestore q4, QSTACK5 // ...................*.................................
// vsub.u16 q1, q4, q0 // ....................*................................
// ldrd r3, r5, [r11, #8*POS_ROOT_2 - 56] // ........*............................................
// vadd.u16 q4, q4, q0 // ......................*..............................
// vmul.s16 q0, q3, r3 // ..........*..........................................
// ldrd r6, r10, [r11, #8*POS_ROOT_3 - 56] // .............*.......................................
// vqrdmulh.s16 q3, q3, r5 // ............*........................................
// vsub.u16 q5, q7, q5 // .........*...........................................
// vmla.s16 q0, q3, r12 // ..............*......................................
// ldrd r2, r1, [r11, #8*POS_ROOT_6 - 56] // ...........*.........................................
// vqrdmulh.s16 q7, q5, r10 // .........................*...........................
// ldrd r5, r4, [r11, #8*POS_ROOT_5 - 56] // ...............*.....................................
// vmul.s16 q3, q5, r6 // .......................*.............................
// vadd.u16 q5, q2, q0 // ................*....................................
// vmla.s16 q3, q7, r12 // ...........................*.........................
// vstrw.u32 q5, [r0] , #128 // .................*...................................
// vmul.s16 q7, q4, r5 // .....................................*...............
// vsub.u16 q5, q6, q3 // .............................*.......................
// vqrdmulh.s16 q4, q4, r4 // .......................................*.............
// vstrw.u32 q5, [r0, #-80] // .................................*...................
// vmla.s16 q7, q4, r12 // ..........................................*..........
// qrestore q4, QSTACK6 // .*...................................................
// vmul.s16 q5, q4, r7 // ..*..................................................
// vadd.u16 q3, q6, q3 // ...............................*.....................
// vqrdmulh.s16 q4, q4, r8 // ....*................................................
// vstrw.u32 q3, [r0, #-96] // ...................................*.................
// vmla.s16 q5, q4, r12 // ......*..............................................
// qrestore q3, QSTACK4 // ...*.................................................
// vmul.s16 q4, q1, r2 // ..............................*......................
// vadd.u16 q6, q3, q5 // ........................*............................
// vqrdmulh.s16 q1, q1, r1 // ................................*....................
// vsub.u16 q0, q2, q0 // ..................*..................................
// vmla.s16 q4, q1, r12 // ..................................*..................
// vadd.u16 q1, q6, q7 // ............................................*........
// vstrw.u32 q0, [r0, #-112] // .....................*...............................
// vsub.u16 q6, q6, q7 // .................................................*...
// vstrw.u32 q6, [r0, #-48] // ..................................................*..
// vsub.u16 q6, q3, q5 // ..........................*..........................
// vstrw.u32 q1, [r0, #-64] // ...............................................*.....
// vsub.u16 q3, q6, q4 // ....................................*................
// vstrw.u32 q3, [r0, #-16] // .............................................*.......
// vadd.u16 q1, q6, q4 // ......................................*..............
// vstrw.u32 q1, [r0, #-32] // ........................................*............
// restore r1, STACK0 // .....*...............................................
// mov r14, #7 // ............................*........................
// vld40.32 {q3,q4,q5,q6}, [r1] // .........................................*...........
// vld41.32 {q3,q4,q5,q6}, [r1] // ...........................................*.........
// vld42.32 {q3,q4,q5,q6}, [r1] // ..............................................*......
// vld43.32 {q3,q4,q5,q6}, [r1]! // ................................................*....
// vldrh.16 q7, [r11] , #96 // ...................................................*.
// vmul.s16 q1, q6, q7 // ....................................................*
layer67_loop:
vmul.s16 q2, q5, q7 // ......*...........................
vldrh.16 q7, [r11, #-80] // .....*............................
vqrdmulh.s16 q6, q6, q7 // ............*.....................
vldrh.16 q0, [r11, #-32] // .......................*..........
vmla.s16 q1, q6, r12 // .............*....................
vldrh.16 q6, [r11, #-16] // ........................*.........
vqrdmulh.s16 q5, q5, q7 // .......*..........................
vadd.u16 q7, q4, q1 // ...............*..................
vmla.s16 q2, q5, r12 // ........*.........................
vsub.u16 q1, q4, q1 // ..............*...................
vmul.s16 q5, q1, q0 // .........................*........
vsub.u16 q0, q3, q2 // .........*........................
vqrdmulh.s16 q6, q1, q6 // ..........................*.......
vadd.u16 q2, q3, q2 // ..........*.......................
vmla.s16 q5, q6, r12 // ...........................*......
vldrh.16 q1, [r11, #-64] // ................*.................
vadd.u16 q3, q0, q5 // .............................*....
vmul.s16 q1, q7, q1 // ..................*...............
vsub.u16 q0, q0, q5 // ............................*.....
vstrw.u32 q0, [r1, #-16] // .................................*
vldrh.16 q0, [r11, #-48] // .................*................
vstrw.u32 q3, [r1, #-32] // ................................*.
vld40.32 {q3,q4,q5,q6}, [r1] // e.................................
vqrdmulh.s16 q7, q7, q0 // ...................*..............
vld41.32 {q3,q4,q5,q6}, [r1] // .e................................
vmla.s16 q1, q7, r12 // ....................*.............
vld42.32 {q3,q4,q5,q6}, [r1] // ..e...............................
vadd.u16 q0, q2, q1 // ......................*...........
vld43.32 {q3,q4,q5,q6}, [r1]! // ...e..............................
vstrw.u32 q0, [r1, #-128] // ..............................*...
vsub.u16 q2, q2, q1 // .....................*............
vldrh.16 q7, [r11] , #96 // ....e.............................
vmul.s16 q1, q6, q7 // ...........e......................
vstrw.u32 q2, [r1, #-112] // ...............................*..
// original source code
// vld40.32 {q0,q1,q2,q3}, [r1] // e.............................................
// vld41.32 {q0,q1,q2,q3}, [r1] // ..e...........................................
// vld42.32 {q0,q1,q2,q3}, [r1] // ....e.........................................
// vld43.32 {q0,q1,q2,q3}, [r1]! // ......e.......................................
// vldrh.16 q5, [r11] , #96 // .........e....................................
// vldrh.16 q6, [r11, #-80] // .............*................................
// vmul.s16 q7, q2, q5 // ............*.................................
// vqrdmulh.s16 q2, q2, q6 // ..................*...........................
// vmla.s16 q7, q2, r12 // ....................*.........................
// vsub.u16 q2, q0, q7 // .......................*......................
// vadd.u16 q0, q0, q7 // .........................*....................
// vmul.s16 q7, q3, q5 // ..........e...................................
// vqrdmulh.s16 q3, q3, q6 // ..............*...............................
// vmla.s16 q7, q3, r12 // ................*.............................
// vsub.u16 q3, q1, q7 // .....................*........................
// vadd.u16 q1, q1, q7 // ...................*..........................
// vldrh.16 q5, [r11, #-64] // ...........................*..................
// vldrh.16 q6, [r11, #-48] // ................................*.............
// vmul.s16 q7, q1, q5 // .............................*................
// vqrdmulh.s16 q1, q1, q6 // ...................................*..........
// vmla.s16 q7, q1, r12 // .....................................*........
// vsub.u16 q1, q0, q7 // ..........................................*...
// vadd.u16 q0, q0, q7 // .......................................*......
// vldrh.16 q5, [r11, #-32] // ...............*..............................
// vldrh.16 q6, [r11, #-16] // .................*............................
// vmul.s16 q7, q3, q5 // ......................*.......................
// vqrdmulh.s16 q3, q3, q6 // ........................*.....................
// vmla.s16 q7, q3, r12 // ..........................*...................
// vsub.u16 q3, q2, q7 // ..............................*...............
// vadd.u16 q2, q2, q7 // ............................*.................
// vstrw.u32 q0, [r1, #-64] // .........................................*....
// vstrw.u32 q1, [r1, #-48] // .............................................*
// vstrw.u32 q2, [r1, #-32] // .................................*............
// vstrw.u32 q3, [r1, #-16] // ...............................*..............
le lr, layer67_loop
vmul.s16 q2, q5, q7 // *...........................
vldrh.16 q7, [r11, #-80] // .*..........................
vqrdmulh.s16 q0, q6, q7 // ..*.........................
vldrh.16 q6, [r11, #-16] // .....*......................
vmla.s16 q1, q0, r12 // ....*.......................
vldrh.16 q0, [r11, #-32] // ...*........................
vqrdmulh.s16 q5, q5, q7 // ......*.....................
vsub.u16 q7, q4, q1 // .........*..................
vmla.s16 q2, q5, r12 // ........*...................
vadd.u16 q4, q4, q1 // .......*....................
vmul.s16 q5, q7, q0 // ..........*.................
vsub.u16 q0, q3, q2 // ...........*................
vqrdmulh.s16 q7, q7, q6 // ............*...............
vadd.u16 q6, q3, q2 // .............*..............
vmla.s16 q5, q7, r12 // ..............*.............
vldrh.16 q1, [r11, #-64] // ...............*............
vsub.u16 q7, q0, q5 // ..................*.........
vstrw.u32 q7, [r1, #-16] // ...................*........
vmul.s16 q1, q4, q1 // .................*..........
vldrh.16 q7, [r11, #-48] // ....................*.......
vqrdmulh.s16 q7, q4, q7 // ......................*.....
vadd.u16 q0, q0, q5 // ................*...........
vmla.s16 q1, q7, r12 // .......................*....
vstrw.u32 q0, [r1, #-32] // .....................*......
vadd.u16 q7, q6, q1 // ........................*...
vstrw.u32 q7, [r1, #-64] // .........................*..
vsub.u16 q7, q6, q1 // ..........................*.
vstrw.u32 q7, [r1, #-48] // ...........................*
// original source code
// vmul.s16 q2, q5, q7 // *...........................
// vldrh.16 q7, [r11, #-80] // .*..........................
// vqrdmulh.s16 q6, q6, q7 // ..*.........................
// vldrh.16 q0, [r11, #-32] // .....*......................
// vmla.s16 q1, q6, r12 // ....*.......................
// vldrh.16 q6, [r11, #-16] // ...*........................
// vqrdmulh.s16 q5, q5, q7 // ......*.....................
// vadd.u16 q7, q4, q1 // .........*..................
// vmla.s16 q2, q5, r12 // ........*...................
// vsub.u16 q1, q4, q1 // .......*....................
// vmul.s16 q5, q1, q0 // ..........*.................
// vsub.u16 q0, q3, q2 // ...........*................
// vqrdmulh.s16 q6, q1, q6 // ............*...............
// vadd.u16 q2, q3, q2 // .............*..............
// vmla.s16 q5, q6, r12 // ..............*.............
// vldrh.16 q1, [r11, #-64] // ...............*............
// vadd.u16 q3, q0, q5 // .....................*......
// vmul.s16 q1, q7, q1 // ..................*.........
// vsub.u16 q0, q0, q5 // ................*...........
// vstrw.u32 q0, [r1, #-16] // .................*..........
// vldrh.16 q0, [r11, #-48] // ...................*........
// vstrw.u32 q3, [r1, #-32] // .......................*....
// vqrdmulh.s16 q7, q7, q0 // ....................*.......
// vmla.s16 q1, q7, r12 // ......................*.....
// vadd.u16 q0, q2, q1 // ........................*...
// vstrw.u32 q0, [r1, #-64] // .........................*..
// vsub.u16 q2, q2, q1 // ..........................*.
// vstrw.u32 q2, [r1, #-48] // ...........................*
add sp, sp, #STACK_SIZE
align_stack_undo
// Restore MVE vector registers
vpop {d8-d15}
// Restore GPRs
pop {r4-r11,lr}
bx lr