Currently, the Cortex-A72 microarchitectural model contains two load units:
def LOAD(cls):
return [ExecutionUnit.LOAD0, ExecutionUnit.LOAD1]
However, according to the SWOG there is only one load unit and the maximum throughput of load instructions is 1.
Neither @dop-amin nor I remember why this was modelled differently from the SWOG. @hanno-becker, do you?
It would be good to run some experiment confirming that the current modelling has any benefits over modelling only a single load unit.
Currently, the Cortex-A72 microarchitectural model contains two load units:
However, according to the SWOG there is only one load unit and the maximum throughput of load instructions is 1.
Neither @dop-amin nor I remember why this was modelled differently from the SWOG. @hanno-becker, do you?
It would be good to run some experiment confirming that the current modelling has any benefits over modelling only a single load unit.