diff --git a/example.py b/example.py index 61a8562d8..9c0284904 100644 --- a/example.py +++ b/example.py @@ -83,6 +83,10 @@ example_instances as example_instances_armv8m_cmplx_mag_sqr_fx, ) +from examples.naive.armv8m.keccak._example import ( + example_instances as example_instances_armv8m_keccak, +) + def main(): examples = ( @@ -98,6 +102,7 @@ def main(): + example_instances_armv8m_flt_r4_fft + example_instances_armv8m_fx_r4_fft + example_instances_armv8m_ntt_256 + + example_instances_armv8m_keccak + example_instances_armv8m_cmplx_mag_sqr_fx ) diff --git a/examples/naive/armv8m/keccak/_example.py b/examples/naive/armv8m/keccak/_example.py new file mode 100644 index 000000000..bdc4bda15 --- /dev/null +++ b/examples/naive/armv8m/keccak/_example.py @@ -0,0 +1,90 @@ +# +# Copyright (c) 2022 Arm Limited +# Copyright (c) 2022 Hanno Becker +# Copyright (c) 2023 Amin Abdulrahman, Matthias Kannwischer +# SPDX-License-Identifier: MIT +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Author: Amin Abdulrahman +# + +import os + +from common.OptimizationRunner import OptimizationRunner +import slothy.targets.arm_v81m.arch_v81m as Arch_Armv81M +import slothy.targets.arm_v81m.cortex_m55r1 as Target_CortexM55r1 +import slothy.targets.arm_v81m.cortex_m85r1 as Target_CortexM85r1 + +SUBFOLDER = os.path.basename(os.path.dirname(__file__)) + "/" + + +class keccak_mve_4x(OptimizationRunner): + def __init__( + self, var="", arch=Arch_Armv81M, target=Target_CortexM55r1, timeout=None + ): + name = "mve-keccak-4x" + infile = name + + super().__init__( + infile, + name=name, + arch=arch, + target=target, + rename=True, + var=var, + subfolder=SUBFOLDER, + funcname="mve_keccak_state_permute_4fold", + ) + self.var = var + self.timeout = timeout + + def core(self, slothy): + # first pass: replace symbolic register names by architectural registers + slothy.config.unsafe_address_offset_fixup = False + slothy.config.inputs_are_outputs = True + slothy.config.constraints.functional_only = True + slothy.config.constraints.allow_reordering = True + slothy.config.allow_useless_instructions = True + slothy.config.constraints.max_displacement = 0.1 + slothy.optimize(start="roundstart", end="roundend_pre") + + # second pass: splitting heuristic + slothy.config.constraints.functional_only = False + slothy.config.constraints.allow_reordering = True + slothy.config.variable_size = True + slothy.config.constraints.stalls_first_attempt = 64 + slothy.config.constraints.max_displacement = 1 + slothy.config.constraints.stalls_maximum_attempt = 4096 + slothy.config.split_heuristic = True + slothy.config.split_heuristic_stepsize = 0.05 + slothy.config.split_heuristic_factor = 20 + slothy.config.split_heuristic_repeat = 2 + slothy.config.split_heuristic_estimate_performance = False + slothy.config.split_heuristic_optimize_seam = 2 + + slothy.optimize(start="roundstart", end="roundend_pre") + + +example_instances = [ + # Cortex-M85 + keccak_mve_4x(target=Target_CortexM85r1), + # Cortex-M55 + keccak_mve_4x(), +] diff --git a/examples/naive/armv8m/keccak/mve-keccak-4x.s b/examples/naive/armv8m/keccak/mve-keccak-4x.s new file mode 100644 index 000000000..600ae817f --- /dev/null +++ b/examples/naive/armv8m/keccak/mve-keccak-4x.s @@ -0,0 +1,514 @@ + +/// +/// Copyright (c) 2025 Arm Limited +/// SPDX-License-Identifier: Apache-2.0 OR MIT OR ISC +/// + +.thumb +.syntax unified +.text +.equ QSTACK0, 0 +.equ A__00, 0 +.equ A__01, 80 +.equ A__02, 160 +.equ A__03, 240 +.equ A__04, 320 +.equ A__10, 16 +.equ A__11, 96 +.equ A__12, 176 +.equ A__13, 256 +.equ A__14, 336 +.equ A__20, 32 +.equ A__21, 112 +.equ A__22, 192 +.equ A__23, 272 +.equ A__24, 352 +.equ A__30, 48 +.equ A__31, 128 +.equ A__32, 208 +.equ A__33, 288 +.equ A__34, 368 +.equ A__40, 64 +.equ A__41, 144 +.equ A__42, 224 +.equ A__43, 304 +.equ A__44, 384 +.equ B__00, 0 +.equ B__01, 256 +.equ B__02, 112 +.equ B__03, 368 +.equ B__04, 224 +.equ B__10, 160 +.equ B__11, 16 +.equ B__12, 272 +.equ B__13, 128 +.equ B__14, 384 +.equ B__20, 320 +.equ B__21, 176 +.equ B__22, 32 +.equ B__23, 288 +.equ B__24, 144 +.equ B__30, 80 +.equ B__31, 336 +.equ B__32, 192 +.equ B__33, 48 +.equ B__34, 304 +.equ B__40, 240 +.equ B__41, 96 +.equ B__42, 352 +.equ B__43, 208 +.equ B__44, 64 +.equ RCxy_00, 0 +.equ RCxy_01, 36 +.equ RCxy_02, 3 +.equ RCxy_03, 41 +.equ RCxy_04, 18 +.equ RCxy_10, 1 +.equ RCxy_11, 44 +.equ RCxy_12, 10 +.equ RCxy_13, 45 +.equ RCxy_14, 2 +.equ RCxy_20, 62 +.equ RCxy_21, 6 +.equ RCxy_22, 43 +.equ RCxy_23, 15 +.equ RCxy_24, 61 +.equ RCxy_30, 28 +.equ RCxy_31, 55 +.equ RCxy_32, 25 +.equ RCxy_33, 21 +.equ RCxy_34, 56 +.equ RCxy_40, 27 +.equ RCxy_41, 20 +.equ RCxy_42, 39 +.equ RCxy_43, 8 +.equ RCxy_44, 14 +.equ RC0_l, 0x1 +.equ RC0_h, 0x0 +.equ RC1_l, 0x0 +.equ RC1_h, 0x89 +.equ RC2_l, 0x0 +.equ RC2_h, 0x8000008b +.equ RC3_l, 0x0 +.equ RC3_h, 0x80008080 +.equ RC4_l, 0x1 +.equ RC4_h, 0x8b +.equ RC5_l, 0x1 +.equ RC5_h, 0x8000 +.equ RC6_l, 0x1 +.equ RC6_h, 0x80008088 +.equ RC7_l, 0x1 +.equ RC7_h, 0x80000082 +.equ RC8_l, 0x0 +.equ RC8_h, 0xb +.equ RC9_l, 0x0 +.equ RC9_h, 0xa +.equ RC10_l, 0x1 +.equ RC10_h, 0x8082 +.equ RC11_l, 0x0 +.equ RC11_h, 0x8003 +.equ RC12_l, 0x1 +.equ RC12_h, 0x808b +.equ RC13_l, 0x1 +.equ RC13_h, 0x8000000b +.equ RC14_l, 0x1 +.equ RC14_h, 0x8000008a +.equ RC15_l, 0x1 +.equ RC15_h, 0x80000081 +.equ RC16_l, 0x0 +.equ RC16_h, 0x80000081 +.equ RC17_l, 0x0 +.equ RC17_h, 0x80000008 +.equ RC18_l, 0x0 +.equ RC18_h, 0x83 +.equ RC19_l, 0x0 +.equ RC19_h, 0x80008003 +.equ RC20_l, 0x1 +.equ RC20_h, 0x80008088 +.equ RC21_l, 0x0 +.equ RC21_h, 0x80000088 +.equ RC22_l, 0x1 +.equ RC22_h, 0x8000 +.equ RC23_l, 0x0 +.equ RC23_h, 0x80008082 + +qA00_h .req q0 +qA00_l .req q1 +qA20_l .req q2 + +.macro ld_xor5 state, round, x, C, A + vldrw.u32 q<\C>, [\state, #A__\x\()0] // @slothy:reads=A\state\()__\x\()0 + vldrw.u32 q<\A>, [\state, #A__\x\()1] // @slothy:reads=A\state\()__\x\()1 + veor q<\C>, q<\C>, q<\A> + vldrw.u32 q<\A>, [\state, #A__\x\()2] // @slothy:reads=A\state\()__\x\()2 + veor q<\C>, q<\C>, q<\A> + vldrw.u32 q<\A>, [\state, #A__\x\()3] // @slothy:reads=A\state\()__\x\()3 + veor q<\C>, q<\C>, q<\A> + vldrw.u32 q<\A>, [\state, #A__\x\()4] // @slothy:reads=A\state\()__\x\()4 + veor q<\C>, q<\C>, q<\A> + .endm + +.macro ld_xor5_0 state, round, x, C, A, A0 + vldrw.u32 q<\C>, [\state, #A__\x\()1] // @slothy:reads=A\state\()__\x\()1 + veor q<\C>, q<\C>, q<\A0> + vldrw.u32 q<\A>, [\state, #A__\x\()2] // @slothy:reads=A\state\()__\x\()2 + veor q<\C>, q<\C>, q<\A> + vldrw.u32 q<\A>, [\state, #A__\x\()3] // @slothy:reads=A\state\()__\x\()3 + veor q<\C>, q<\C>, q<\A> + vldrw.u32 q<\A>, [\state, #A__\x\()4] // @slothy:reads=A\state\()__\x\()4 + veor q<\C>, q<\C>, q<\A> + .endm + + +.macro rot1_xor_l D1_l, C0_l, C2_h + vshr.u32 q<\D1_l>, q<\C2_h>, #31 + vsli.32 q<\D1_l>, q<\C2_h>, #1 + veor q<\D1_l>, q<\D1_l>, q<\C0_l> + .endm + +.macro rot1_xor_h D1_h, C0_h, C2_l + veor q<\D1_h>, q<\C2_l>, q<\C0_h> + .endm + +.macro rot_str_e s_l, s_h, A_l, A_h, RC, x, y + vshr.u32 q, q, #32-(\RC/2) + vsli.u32 q, q, #\RC/2 + vstrw.32 q, [\s_l, #B__\x\()\y] + vshr.u32 q, q, #32-(\RC/2) + vsli.u32 q, q, #\RC/2 + vstrw.32 q, [\s_h, #B__\x\()\y] +.endm + +.macro rot_str_o s_l, s_h, A_l, A_h, RC, x, y + .if (\RC-1)/2 == 0 + vstrw.32 q, [\s_h, #B__\x\()\y] + .else + vshr.u32 q, q, #32-((\RC-1)/2) + vsli.u32 q, q, #(\RC-1)/2 + vstrw.32 q, [\s_h, #B__\x\()\y] + .endif + + .if (\RC+1)/2 == 0 + // should never happen + vstrw.32 q, [\s_l, #B__\x\()\y] + .else + vshr.u32 q, q, #32-((\RC+1)/2) + vsli.u32 q, q, #(\RC+1)/2 + vstrw.32 q, [\s_l, #B__\x\()\y] + .endif +.endm + +.macro ld_xorD_rot_str_e state_l, state_h, state_nl, state_nh, x, y, Dx_l, Dx_h + vldrw.u32 q, [\state_l, #A__\x\()\y] // @slothy:reads=A\state_l\()__\x\()\y + vldrw.u32 q, [\state_h, #A__\x\()\y] // @slothy:reads=A\state_h\()__\x\()\y + veor q, q, q<\Dx_l> + veor q, q, q<\Dx_h> + rot_str_e \state_nl, \state_nh, A_l, A_h, RCxy_\x\()\y, \x, \y +.endm + +.macro rot_str_e_0 s_l, s_h, A_l, A_h, RC, x, y, regl, regh + vshr.u32 q<\regl>, q, #32-(\RC/2) + vsli.u32 q<\regl>, q, #\RC/2 + //vstrw.32 q, [\s_l, #B__\x\()\y] + vshr.u32 q<\regh>, q, #32-(\RC/2) + vsli.u32 q<\regh>, q, #\RC/2 + //vstrw.32 q, [\s_h, #B__\x\()\y] +.endm + +.macro ld_xorD_rot_str_e_0 state_l, state_h, state_nl, state_nh, x, y, Dx_l, Dx_h, regl, regh + vldrw.u32 q, [\state_l, #A__\x\()\y] // @slothy:reads=A\state_l\()__\x\()\y + vldrw.u32 q, [\state_h, #A__\x\()\y] // @slothy:reads=A\state_h\()__\x\()\y + veor q, q, q<\Dx_l> + veor q, q, q<\Dx_h> + rot_str_e_0 \state_nl, \state_nh, A_l, A_h, RCxy_\x\()\y, \x, \y, \regl, \regh +.endm + +.macro ld_xorD_rot_str_o state_l, state_h, state_nl, state_nh, x, y, Dx_l, Dx_h + vldrw.u32 q, [\state_l, #A__\x\()\y] // @slothy:reads=A\state_l\()__\x\()\y + vldrw.u32 q, [\state_h, #A__\x\()\y] // @slothy:reads=A\state_h\()__\x\()\y + veor q, q, q<\Dx_l> + veor q, q, q<\Dx_h> + rot_str_o \state_nl, \state_nh, A_l, A_h, RCxy_\x\()\y, \x, \y +.endm + +.macro ld_bic_str state, state_n, round, y + vldrw.u32 q, [\state_n, #A__0\y] // @slothy:reads=A\state_n\()__0\y + vldrw.u32 q, [\state_n, #A__1\y] // @slothy:reads=A\state_n\()__1\y + vldrw.u32 q, [\state_n, #A__2\y] // @slothy:reads=A\state_n\()__2\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__0\y] // @slothy:writes=A\state\()__0\y + vldrw.u32 q, [\state_n, #A__3\y] // @slothy:reads=A\state_n\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__1\y] // @slothy:writes=A\state\()__1\y + vldrw.u32 q, [\state_n, #A__4\y] // @slothy:reads=A\state_n\()__4\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__2\y] // @slothy:writes=A\state\()__2\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__3\y] // @slothy:writes=A\state\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__4\y] // @slothy:writes=A\state\()__4\y +.endm + +.macro ld_bic_str_0 state, state_n round, y, A0 + vldrw.u32 q, [\state_n, #A__1\y] // @slothy:reads=A\state_n\()__1\y + vldrw.u32 q, [\state_n, #A__2\y] // @slothy:reads=A\state_n\()__2\y + vldrw.u32 q, [\state_n, #A__3\y] // @slothy:reads=A\state_n\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__1\y] // @slothy:writes=A\state\()__1\y + vldrw.u32 q, [\state_n, #A__4\y] // @slothy:reads=A\state_n\()__4\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__2\y] // @slothy:writes=A\state\()__2\y + vldrw.u32 q, [\state_n, #A__0\y] // @slothy:reads=A\state_n\()__0\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__3\y] // @slothy:writes=A\state\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__4\y] // @slothy:writes=A\state\()__4\y + vbic q, q, q + veor q<\A0>, q, q + // A0 is stored later after the round-constant is added +.endm + +.macro ld_bic_str_1 state, state_n, round, y, A0, A2 + vldrw.u32 q, [\state_n, #A__1\y] // @slothy:reads=A\state_n\()__1\y + vldrw.u32 q, [\state_n, #A__2\y] // @slothy:reads=A\state_n\()__2\y + vldrw.u32 q, [\state_n, #A__3\y] // @slothy:reads=A\state_n\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__1\y] // @slothy:writes=A\state\()__1\y + vldrw.u32 q, [\state_n, #A__4\y] // @slothy:reads=A\state_n\()__4\y + vbic q, q, q + veor q<\A2>, q, q + vstrw.32 q<\A2>, [\state, #A__2\y] // @slothy:writes=A\state\()__2\y + vldrw.u32 q, [\state_n, #A__0\y] // @slothy:reads=A\state_n\()__0\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__3\y] // @slothy:writes=A\state\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__4\y] // @slothy:writes=A\state\()__4\y + vbic q, q, q + veor q<\A0>, q, q + // A0 is stored later after the round-constant is added +.endm + +.macro ld_1_bic_str state, state_n, round, y, B1 + vldrw.u32 q, [\state_n, #A__0\y] // @slothy:reads=A\state_n\()__0\y + //vldrw.u32 q, [\state_n, #A__1\y] // @slothy:reads=A\state_n\()__1\y + vldrw.u32 q, [\state_n, #A__2\y] // @slothy:reads=A\state_n\()__2\y + vbic q, q, q<\B1> + veor q, q, q + vstrw.32 q, [\state, #A__0\y] // @slothy:writes=A\state\()__0\y + vldrw.u32 q, [\state_n, #A__3\y] // @slothy:reads=A\state_n\()__3\y + vbic q, q, q + veor q, q<\B1>, q + vstrw.32 q, [\state, #A__1\y] // @slothy:writes=A\state\()__1\y + vldrw.u32 q, [\state_n, #A__4\y] // @slothy:reads=A\state_n\()__4\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__2\y] // @slothy:writes=A\state\()__2\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__3\y] // @slothy:writes=A\state\()__3\y + vbic q, q<\B1>, q + veor q, q, q + vstrw.32 q, [\state, #A__4\y] // @slothy:writes=A\state\()__4\y +.endm + +.macro ld_3_bic_str state, state_n, round, y, B3 + vldrw.u32 q, [\state_n, #A__0\y] // @slothy:reads=A\state_n\()__0\y + vldrw.u32 q, [\state_n, #A__1\y] // @slothy:reads=A\state_n\()__1\y + vldrw.u32 q, [\state_n, #A__2\y] // @slothy:reads=A\state_n\()__2\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__0\y] // @slothy:writes=A\state\()__0\y + //vldrw.u32 q, [\state_n, #A__3\y] // @slothy:reads=A\state_n\()__3\y + vbic q, q<\B3>, q + veor q, q, q + vstrw.32 q, [\state, #A__1\y] // @slothy:writes=A\state\()__1\y + vldrw.u32 q, [\state_n, #A__4\y] // @slothy:reads=A\state_n\()__4\y + vbic q, q, q<\B3> + veor q, q, q + vstrw.32 q, [\state, #A__2\y] // @slothy:writes=A\state\()__2\y + vbic q, q, q + veor q, q<\B3>, q + vstrw.32 q, [\state, #A__3\y] // @slothy:writes=A\state\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__4\y] // @slothy:writes=A\state\()__4\y +.endm + + + +.macro keccak_4fold_round_theta_rho_pi state_l, state_h, state_nl, state_nh, rc + ld_xor5_0 \state_h, 0, 0, C0_h, A0_h, qA00_h + ld_xor5_0 \state_l, 0, 2, C2_l, A2_l, qA20_l + rot1_xor_h D1_h, C0_h, C2_l + vstrw.32 q, [r13, #QSTACK0] // @slothy:writes=stack0 + + ld_xor5_0 \state_l, 0, 0, C0_l, A0_l, qA00_l + ld_xor5 \state_h, 0, 2, C2_h, A2_h + rot1_xor_l D1_l, C0_l, C2_h + + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 1, 0, D1_l, D1_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 1, 1, D1_l, D1_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 1, 2, D1_l, D1_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 1, 3, D1_l, D1_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 1, 4, D1_l, D1_h + + ld_xor5 \state_h, 0, 4, C4_h, A4_h + rot1_xor_l D3_l, C2_l, C4_h + + ld_xor5 \state_l, 0, 4, C4_l, A4_l + rot1_xor_h D3_h, C2_h, C4_l + + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 3, 0, D3_l, D3_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 3, 1, D3_l, D3_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 3, 2, D3_l, D3_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 3, 3, D3_l, D3_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 3, 4, D3_l, D3_h + + ld_xor5 \state_h, 0, 1, C1_h, A1_h + rot1_xor_l D0_l, C4_l, C1_h + ld_xor5 \state_l, 0, 1, C1_l, A1_l + rot1_xor_h D0_h, C4_h, C1_l + + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 0, 0, D0_l, D0_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 0, 1, D0_l, D0_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 0, 2, D0_l, D0_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 0, 3, D0_l, D0_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 0, 4, D0_l, D0_h + + ld_xor5 \state_l, 0, 3, C3_l, A3_l + rot1_xor_h D2_h, C1_h, C3_l + ld_xor5 \state_h, 0, 3, C3_h, A3_h + rot1_xor_l D2_l, C1_l, C3_h + + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 2, 0, D2_l, D2_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 2, 1, D2_l, D2_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 2, 2, D2_l, D2_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 2, 3, D2_l, D2_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 2, 4, D2_l, D2_h + + rot1_xor_h D4_h, C3_h, C0_l + vldrw.32 q, [r13, #QSTACK0] // @slothy:reads=stack0 + rot1_xor_l D4_l, C3_l, C0_h + + + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 4, 0, D4_l, D4_h // B40 = A03 + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 4, 2, D4_l, D4_h // B42 = A24 + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 4, 4, D4_l, D4_h // B44 = A40 + // A11_l, A11_h, A32_l are held in registers from the next step + ld_xorD_rot_str_e_0 \state_l, \state_h, \state_nl, \state_nh, 4, 3, D4_l, D4_h, A32_l, A32_h // B43 = A32 + vstrw.32 q, [\state_nh, #B__43] + ld_xorD_rot_str_e_0 \state_l, \state_h, \state_nl, \state_nh, 4, 1, D4_l, D4_h, A11_l, A11_h // B41 = A11 +.endm + +.macro keccak_4fold_round_chi_iota state_l, state_h, state_nl, state_nh, rc // now BIC + // A11_l, A11_h, A32_l are held in registers from the previous step + ld_1_bic_str \state_l, \state_nl, 0, 1, A11_l + ld_1_bic_str \state_h, \state_nh, 0, 1, A11_h + + ld_3_bic_str \state_l, \state_nl, 0, 2, A32_l + ld_bic_str \state_h, \state_nh, 0, 2 + + ld_bic_str \state_l, \state_nl, 0, 3 + ld_bic_str \state_h, \state_nh, 0, 3 + + ld_bic_str \state_l, \state_nl, 0, 4 + ld_bic_str \state_h, \state_nh, 0, 4 + + ld_bic_str_1 \state_l, \state_nl, 0, 0, A00_l, qA20_l + ld_bic_str_0 \state_h, \state_nh, 0, 0, A00_h + + + ldrd r, r, [\rc] + vdup.32 q, r + veor qA00_l, q, q + vstrw.32 qA00_l, [\state_l, #A__00] // @slothy:writes=A\state_l\()__00 + vdup.32 q, r + veor qA00_h, q, q + vstrw.32 qA00_h, [\state_h, #A__00] // @slothy:writes=A\state_h\()__00 +.endm + +.text +RC_table: + .word RC0_l, RC0_h + .word RC1_l, RC1_h + .word RC2_l, RC2_h + .word RC3_l, RC3_h + .word RC4_l, RC4_h + .word RC5_l, RC5_h + .word RC6_l, RC6_h + .word RC7_l, RC7_h + .word RC8_l, RC8_h + .word RC9_l, RC9_h + .word RC10_l, RC10_h + .word RC11_l, RC11_h + .word RC12_l, RC12_h + .word RC13_l, RC13_h + .word RC14_l, RC14_h + .word RC15_l, RC15_h + .word RC16_l, RC16_h + .word RC17_l, RC17_h + .word RC18_l, RC18_h + .word RC19_l, RC19_h + .word RC20_l, RC20_h + .word RC21_l, RC21_h + .word RC22_l, RC22_h + .word RC23_l, RC23_h + +.align 8 +.type mve_keccak_state_permute_4fold, %function +.global mve_keccak_state_permute_4fold +mve_keccak_state_permute_4fold: + + push {r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} + vpush {d8-d15} + sub sp, #8*16 + + adr r6, RC_table + + // r0: state 0 + // r1: state 1 + // r2: this state low + // r3: this state high + // r4: next state low + // r5: next state high + // r6: rc table + + + mov lr, #24 + + mov r2, r0 + mov r4, r1 + + // pre-fetch so we can keep in registers between rounds + add r3, r2, #400 + vldrw.u32 qA00_h, [r3, #A__00] + vldrw.u32 qA00_l, [r2, #A__00] + vldrw.u32 qA20_l, [r2, #A__20] + + wls lr, lr, roundend +roundstart: + add r3, r2, #400 + add r5, r4, #400 + keccak_4fold_round_theta_rho_pi r2, r3, r4, r5, r6 + keccak_4fold_round_chi_iota r2, r3, r4, r5, r6 + + add r6, r6, #8 +roundend_pre: + le lr, roundstart +roundend: + add sp, #8*16 + + vpop {d8-d15} + ldmia.w sp!, {r3,r4,r5,r6,r7,r8,r9,r10,r11,r12, pc} \ No newline at end of file diff --git a/examples/opt/armv8m/keccak/mve-keccak-4x_opt_m55.s b/examples/opt/armv8m/keccak/mve-keccak-4x_opt_m55.s new file mode 100644 index 000000000..9ebc1c80b --- /dev/null +++ b/examples/opt/armv8m/keccak/mve-keccak-4x_opt_m55.s @@ -0,0 +1,1640 @@ + +/// +/// Copyright (c) 2025 Arm Limited +/// SPDX-License-Identifier: Apache-2.0 OR MIT OR ISC +/// + +.thumb +.syntax unified +.text +.equ QSTACK0, 0 +.equ A__00, 0 +.equ A__01, 80 +.equ A__02, 160 +.equ A__03, 240 +.equ A__04, 320 +.equ A__10, 16 +.equ A__11, 96 +.equ A__12, 176 +.equ A__13, 256 +.equ A__14, 336 +.equ A__20, 32 +.equ A__21, 112 +.equ A__22, 192 +.equ A__23, 272 +.equ A__24, 352 +.equ A__30, 48 +.equ A__31, 128 +.equ A__32, 208 +.equ A__33, 288 +.equ A__34, 368 +.equ A__40, 64 +.equ A__41, 144 +.equ A__42, 224 +.equ A__43, 304 +.equ A__44, 384 +.equ B__00, 0 +.equ B__01, 256 +.equ B__02, 112 +.equ B__03, 368 +.equ B__04, 224 +.equ B__10, 160 +.equ B__11, 16 +.equ B__12, 272 +.equ B__13, 128 +.equ B__14, 384 +.equ B__20, 320 +.equ B__21, 176 +.equ B__22, 32 +.equ B__23, 288 +.equ B__24, 144 +.equ B__30, 80 +.equ B__31, 336 +.equ B__32, 192 +.equ B__33, 48 +.equ B__34, 304 +.equ B__40, 240 +.equ B__41, 96 +.equ B__42, 352 +.equ B__43, 208 +.equ B__44, 64 +.equ RCxy_00, 0 +.equ RCxy_01, 36 +.equ RCxy_02, 3 +.equ RCxy_03, 41 +.equ RCxy_04, 18 +.equ RCxy_10, 1 +.equ RCxy_11, 44 +.equ RCxy_12, 10 +.equ RCxy_13, 45 +.equ RCxy_14, 2 +.equ RCxy_20, 62 +.equ RCxy_21, 6 +.equ RCxy_22, 43 +.equ RCxy_23, 15 +.equ RCxy_24, 61 +.equ RCxy_30, 28 +.equ RCxy_31, 55 +.equ RCxy_32, 25 +.equ RCxy_33, 21 +.equ RCxy_34, 56 +.equ RCxy_40, 27 +.equ RCxy_41, 20 +.equ RCxy_42, 39 +.equ RCxy_43, 8 +.equ RCxy_44, 14 +.equ RC0_l, 0x1 +.equ RC0_h, 0x0 +.equ RC1_l, 0x0 +.equ RC1_h, 0x89 +.equ RC2_l, 0x0 +.equ RC2_h, 0x8000008b +.equ RC3_l, 0x0 +.equ RC3_h, 0x80008080 +.equ RC4_l, 0x1 +.equ RC4_h, 0x8b +.equ RC5_l, 0x1 +.equ RC5_h, 0x8000 +.equ RC6_l, 0x1 +.equ RC6_h, 0x80008088 +.equ RC7_l, 0x1 +.equ RC7_h, 0x80000082 +.equ RC8_l, 0x0 +.equ RC8_h, 0xb +.equ RC9_l, 0x0 +.equ RC9_h, 0xa +.equ RC10_l, 0x1 +.equ RC10_h, 0x8082 +.equ RC11_l, 0x0 +.equ RC11_h, 0x8003 +.equ RC12_l, 0x1 +.equ RC12_h, 0x808b +.equ RC13_l, 0x1 +.equ RC13_h, 0x8000000b +.equ RC14_l, 0x1 +.equ RC14_h, 0x8000008a +.equ RC15_l, 0x1 +.equ RC15_h, 0x80000081 +.equ RC16_l, 0x0 +.equ RC16_h, 0x80000081 +.equ RC17_l, 0x0 +.equ RC17_h, 0x80000008 +.equ RC18_l, 0x0 +.equ RC18_h, 0x83 +.equ RC19_l, 0x0 +.equ RC19_h, 0x80008003 +.equ RC20_l, 0x1 +.equ RC20_h, 0x80008088 +.equ RC21_l, 0x0 +.equ RC21_h, 0x80000088 +.equ RC22_l, 0x1 +.equ RC22_h, 0x8000 +.equ RC23_l, 0x0 +.equ RC23_h, 0x80008082 + +qA00_h .req q0 +qA00_l .req q1 +qA20_l .req q2 + +.macro ld_xor5 state, round, x, C, A + vldrw.u32 q<\C>, [\state, #A__\x\()0] // @slothy:reads=A\state\()__\x\()0 + vldrw.u32 q<\A>, [\state, #A__\x\()1] // @slothy:reads=A\state\()__\x\()1 + veor q<\C>, q<\C>, q<\A> + vldrw.u32 q<\A>, [\state, #A__\x\()2] // @slothy:reads=A\state\()__\x\()2 + veor q<\C>, q<\C>, q<\A> + vldrw.u32 q<\A>, [\state, #A__\x\()3] // @slothy:reads=A\state\()__\x\()3 + veor q<\C>, q<\C>, q<\A> + vldrw.u32 q<\A>, [\state, #A__\x\()4] // @slothy:reads=A\state\()__\x\()4 + veor q<\C>, q<\C>, q<\A> + .endm + +.macro ld_xor5_0 state, round, x, C, A, A0 + vldrw.u32 q<\C>, [\state, #A__\x\()1] // @slothy:reads=A\state\()__\x\()1 + veor q<\C>, q<\C>, q<\A0> + vldrw.u32 q<\A>, [\state, #A__\x\()2] // @slothy:reads=A\state\()__\x\()2 + veor q<\C>, q<\C>, q<\A> + vldrw.u32 q<\A>, [\state, #A__\x\()3] // @slothy:reads=A\state\()__\x\()3 + veor q<\C>, q<\C>, q<\A> + vldrw.u32 q<\A>, [\state, #A__\x\()4] // @slothy:reads=A\state\()__\x\()4 + veor q<\C>, q<\C>, q<\A> + .endm + + +.macro rot1_xor_l D1_l, C0_l, C2_h + vshr.u32 q<\D1_l>, q<\C2_h>, #31 + vsli.32 q<\D1_l>, q<\C2_h>, #1 + veor q<\D1_l>, q<\D1_l>, q<\C0_l> + .endm + +.macro rot1_xor_h D1_h, C0_h, C2_l + veor q<\D1_h>, q<\C2_l>, q<\C0_h> + .endm + +.macro rot_str_e s_l, s_h, A_l, A_h, RC, x, y + vshr.u32 q, q, #32-(\RC/2) + vsli.u32 q, q, #\RC/2 + vstrw.32 q, [\s_l, #B__\x\()\y] + vshr.u32 q, q, #32-(\RC/2) + vsli.u32 q, q, #\RC/2 + vstrw.32 q, [\s_h, #B__\x\()\y] +.endm + +.macro rot_str_o s_l, s_h, A_l, A_h, RC, x, y + .if (\RC-1)/2 == 0 + vstrw.32 q, [\s_h, #B__\x\()\y] + .else + vshr.u32 q, q, #32-((\RC-1)/2) + vsli.u32 q, q, #(\RC-1)/2 + vstrw.32 q, [\s_h, #B__\x\()\y] + .endif + + .if (\RC+1)/2 == 0 + // should never happen + vstrw.32 q, [\s_l, #B__\x\()\y] + .else + vshr.u32 q, q, #32-((\RC+1)/2) + vsli.u32 q, q, #(\RC+1)/2 + vstrw.32 q, [\s_l, #B__\x\()\y] + .endif +.endm + +.macro ld_xorD_rot_str_e state_l, state_h, state_nl, state_nh, x, y, Dx_l, Dx_h + vldrw.u32 q, [\state_l, #A__\x\()\y] // @slothy:reads=A\state_l\()__\x\()\y + vldrw.u32 q, [\state_h, #A__\x\()\y] // @slothy:reads=A\state_h\()__\x\()\y + veor q, q, q<\Dx_l> + veor q, q, q<\Dx_h> + rot_str_e \state_nl, \state_nh, A_l, A_h, RCxy_\x\()\y, \x, \y +.endm + +.macro rot_str_e_0 s_l, s_h, A_l, A_h, RC, x, y, regl, regh + vshr.u32 q<\regl>, q, #32-(\RC/2) + vsli.u32 q<\regl>, q, #\RC/2 + // vstrw.32 q, [\s_l, #B__\x\()\y] + vshr.u32 q<\regh>, q, #32-(\RC/2) + vsli.u32 q<\regh>, q, #\RC/2 + // vstrw.32 q, [\s_h, #B__\x\()\y] +.endm + +.macro ld_xorD_rot_str_e_0 state_l, state_h, state_nl, state_nh, x, y, Dx_l, Dx_h, regl, regh + vldrw.u32 q, [\state_l, #A__\x\()\y] // @slothy:reads=A\state_l\()__\x\()\y + vldrw.u32 q, [\state_h, #A__\x\()\y] // @slothy:reads=A\state_h\()__\x\()\y + veor q, q, q<\Dx_l> + veor q, q, q<\Dx_h> + rot_str_e_0 \state_nl, \state_nh, A_l, A_h, RCxy_\x\()\y, \x, \y, \regl, \regh +.endm + +.macro ld_xorD_rot_str_o state_l, state_h, state_nl, state_nh, x, y, Dx_l, Dx_h + vldrw.u32 q, [\state_l, #A__\x\()\y] // @slothy:reads=A\state_l\()__\x\()\y + vldrw.u32 q, [\state_h, #A__\x\()\y] // @slothy:reads=A\state_h\()__\x\()\y + veor q, q, q<\Dx_l> + veor q, q, q<\Dx_h> + rot_str_o \state_nl, \state_nh, A_l, A_h, RCxy_\x\()\y, \x, \y +.endm + +.macro ld_bic_str state, state_n, round, y + vldrw.u32 q, [\state_n, #A__0\y] // @slothy:reads=A\state_n\()__0\y + vldrw.u32 q, [\state_n, #A__1\y] // @slothy:reads=A\state_n\()__1\y + vldrw.u32 q, [\state_n, #A__2\y] // @slothy:reads=A\state_n\()__2\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__0\y] // @slothy:writes=A\state\()__0\y + vldrw.u32 q, [\state_n, #A__3\y] // @slothy:reads=A\state_n\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__1\y] // @slothy:writes=A\state\()__1\y + vldrw.u32 q, [\state_n, #A__4\y] // @slothy:reads=A\state_n\()__4\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__2\y] // @slothy:writes=A\state\()__2\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__3\y] // @slothy:writes=A\state\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__4\y] // @slothy:writes=A\state\()__4\y +.endm + +.macro ld_bic_str_0 state, state_n round, y, A0 + vldrw.u32 q, [\state_n, #A__1\y] // @slothy:reads=A\state_n\()__1\y + vldrw.u32 q, [\state_n, #A__2\y] // @slothy:reads=A\state_n\()__2\y + vldrw.u32 q, [\state_n, #A__3\y] // @slothy:reads=A\state_n\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__1\y] // @slothy:writes=A\state\()__1\y + vldrw.u32 q, [\state_n, #A__4\y] // @slothy:reads=A\state_n\()__4\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__2\y] // @slothy:writes=A\state\()__2\y + vldrw.u32 q, [\state_n, #A__0\y] // @slothy:reads=A\state_n\()__0\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__3\y] // @slothy:writes=A\state\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__4\y] // @slothy:writes=A\state\()__4\y + vbic q, q, q + veor q<\A0>, q, q + // A0 is stored later after the round-constant is added +.endm + +.macro ld_bic_str_1 state, state_n, round, y, A0, A2 + vldrw.u32 q, [\state_n, #A__1\y] // @slothy:reads=A\state_n\()__1\y + vldrw.u32 q, [\state_n, #A__2\y] // @slothy:reads=A\state_n\()__2\y + vldrw.u32 q, [\state_n, #A__3\y] // @slothy:reads=A\state_n\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__1\y] // @slothy:writes=A\state\()__1\y + vldrw.u32 q, [\state_n, #A__4\y] // @slothy:reads=A\state_n\()__4\y + vbic q, q, q + veor q<\A2>, q, q + vstrw.32 q<\A2>, [\state, #A__2\y] // @slothy:writes=A\state\()__2\y + vldrw.u32 q, [\state_n, #A__0\y] // @slothy:reads=A\state_n\()__0\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__3\y] // @slothy:writes=A\state\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__4\y] // @slothy:writes=A\state\()__4\y + vbic q, q, q + veor q<\A0>, q, q + // A0 is stored later after the round-constant is added +.endm + +.macro ld_1_bic_str state, state_n, round, y, B1 + vldrw.u32 q, [\state_n, #A__0\y] // @slothy:reads=A\state_n\()__0\y + // vldrw.u32 q, [\state_n, #A__1\y] // @slothy:reads=A\state_n\()__1\y + vldrw.u32 q, [\state_n, #A__2\y] // @slothy:reads=A\state_n\()__2\y + vbic q, q, q<\B1> + veor q, q, q + vstrw.32 q, [\state, #A__0\y] // @slothy:writes=A\state\()__0\y + vldrw.u32 q, [\state_n, #A__3\y] // @slothy:reads=A\state_n\()__3\y + vbic q, q, q + veor q, q<\B1>, q + vstrw.32 q, [\state, #A__1\y] // @slothy:writes=A\state\()__1\y + vldrw.u32 q, [\state_n, #A__4\y] // @slothy:reads=A\state_n\()__4\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__2\y] // @slothy:writes=A\state\()__2\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__3\y] // @slothy:writes=A\state\()__3\y + vbic q, q<\B1>, q + veor q, q, q + vstrw.32 q, [\state, #A__4\y] // @slothy:writes=A\state\()__4\y +.endm + +.macro ld_3_bic_str state, state_n, round, y, B3 + vldrw.u32 q, [\state_n, #A__0\y] // @slothy:reads=A\state_n\()__0\y + vldrw.u32 q, [\state_n, #A__1\y] // @slothy:reads=A\state_n\()__1\y + vldrw.u32 q, [\state_n, #A__2\y] // @slothy:reads=A\state_n\()__2\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__0\y] // @slothy:writes=A\state\()__0\y + // vldrw.u32 q, [\state_n, #A__3\y] // @slothy:reads=A\state_n\()__3\y + vbic q, q<\B3>, q + veor q, q, q + vstrw.32 q, [\state, #A__1\y] // @slothy:writes=A\state\()__1\y + vldrw.u32 q, [\state_n, #A__4\y] // @slothy:reads=A\state_n\()__4\y + vbic q, q, q<\B3> + veor q, q, q + vstrw.32 q, [\state, #A__2\y] // @slothy:writes=A\state\()__2\y + vbic q, q, q + veor q, q<\B3>, q + vstrw.32 q, [\state, #A__3\y] // @slothy:writes=A\state\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__4\y] // @slothy:writes=A\state\()__4\y +.endm + + + +.macro keccak_4fold_round_theta_rho_pi state_l, state_h, state_nl, state_nh, rc + ld_xor5_0 \state_h, 0, 0, C0_h, A0_h, qA00_h + ld_xor5_0 \state_l, 0, 2, C2_l, A2_l, qA20_l + rot1_xor_h D1_h, C0_h, C2_l + vstrw.32 q, [r13, #QSTACK0] // @slothy:writes=stack0 + + ld_xor5_0 \state_l, 0, 0, C0_l, A0_l, qA00_l + ld_xor5 \state_h, 0, 2, C2_h, A2_h + rot1_xor_l D1_l, C0_l, C2_h + + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 1, 0, D1_l, D1_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 1, 1, D1_l, D1_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 1, 2, D1_l, D1_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 1, 3, D1_l, D1_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 1, 4, D1_l, D1_h + + ld_xor5 \state_h, 0, 4, C4_h, A4_h + rot1_xor_l D3_l, C2_l, C4_h + + ld_xor5 \state_l, 0, 4, C4_l, A4_l + rot1_xor_h D3_h, C2_h, C4_l + + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 3, 0, D3_l, D3_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 3, 1, D3_l, D3_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 3, 2, D3_l, D3_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 3, 3, D3_l, D3_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 3, 4, D3_l, D3_h + + ld_xor5 \state_h, 0, 1, C1_h, A1_h + rot1_xor_l D0_l, C4_l, C1_h + ld_xor5 \state_l, 0, 1, C1_l, A1_l + rot1_xor_h D0_h, C4_h, C1_l + + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 0, 0, D0_l, D0_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 0, 1, D0_l, D0_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 0, 2, D0_l, D0_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 0, 3, D0_l, D0_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 0, 4, D0_l, D0_h + + ld_xor5 \state_l, 0, 3, C3_l, A3_l + rot1_xor_h D2_h, C1_h, C3_l + ld_xor5 \state_h, 0, 3, C3_h, A3_h + rot1_xor_l D2_l, C1_l, C3_h + + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 2, 0, D2_l, D2_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 2, 1, D2_l, D2_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 2, 2, D2_l, D2_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 2, 3, D2_l, D2_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 2, 4, D2_l, D2_h + + rot1_xor_h D4_h, C3_h, C0_l + vldrw.32 q, [r13, #QSTACK0] // @slothy:reads=stack0 + rot1_xor_l D4_l, C3_l, C0_h + + + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 4, 0, D4_l, D4_h // B40 = A03 + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 4, 2, D4_l, D4_h // B42 = A24 + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 4, 4, D4_l, D4_h // B44 = A40 + // A11_l, A11_h, A32_l are held in registers from the next step + ld_xorD_rot_str_e_0 \state_l, \state_h, \state_nl, \state_nh, 4, 3, D4_l, D4_h, A32_l, A32_h // B43 = A32 + vstrw.32 q, [\state_nh, #B__43] + ld_xorD_rot_str_e_0 \state_l, \state_h, \state_nl, \state_nh, 4, 1, D4_l, D4_h, A11_l, A11_h // B41 = A11 +.endm + +.macro keccak_4fold_round_chi_iota state_l, state_h, state_nl, state_nh, rc // now BIC + // A11_l, A11_h, A32_l are held in registers from the previous step + ld_1_bic_str \state_l, \state_nl, 0, 1, A11_l + ld_1_bic_str \state_h, \state_nh, 0, 1, A11_h + + ld_3_bic_str \state_l, \state_nl, 0, 2, A32_l + ld_bic_str \state_h, \state_nh, 0, 2 + + ld_bic_str \state_l, \state_nl, 0, 3 + ld_bic_str \state_h, \state_nh, 0, 3 + + ld_bic_str \state_l, \state_nl, 0, 4 + ld_bic_str \state_h, \state_nh, 0, 4 + + ld_bic_str_1 \state_l, \state_nl, 0, 0, A00_l, qA20_l + ld_bic_str_0 \state_h, \state_nh, 0, 0, A00_h + + + ldrd r, r, [\rc] + vdup.32 q, r + veor qA00_l, q, q + vstrw.32 qA00_l, [\state_l, #A__00] // @slothy:writes=A\state_l\()__00 + vdup.32 q, r + veor qA00_h, q, q + vstrw.32 qA00_h, [\state_h, #A__00] // @slothy:writes=A\state_h\()__00 +.endm + +.text +RC_table: + .word RC0_l, RC0_h + .word RC1_l, RC1_h + .word RC2_l, RC2_h + .word RC3_l, RC3_h + .word RC4_l, RC4_h + .word RC5_l, RC5_h + .word RC6_l, RC6_h + .word RC7_l, RC7_h + .word RC8_l, RC8_h + .word RC9_l, RC9_h + .word RC10_l, RC10_h + .word RC11_l, RC11_h + .word RC12_l, RC12_h + .word RC13_l, RC13_h + .word RC14_l, RC14_h + .word RC15_l, RC15_h + .word RC16_l, RC16_h + .word RC17_l, RC17_h + .word RC18_l, RC18_h + .word RC19_l, RC19_h + .word RC20_l, RC20_h + .word RC21_l, RC21_h + .word RC22_l, RC22_h + .word RC23_l, RC23_h + +.align 8 +.type mve_keccak_state_permute_4fold_opt_m55, %function +.global mve_keccak_state_permute_4fold_opt_m55 +mve_keccak_state_permute_4fold_opt_m55: + + push {r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} + vpush {d8-d15} + sub sp, #8*16 + + adr r6, RC_table + + // r0: state 0 + // r1: state 1 + // r2: this state low + // r3: this state high + // r4: next state low + // r5: next state high + // r6: rc table + + + mov lr, #24 + + mov r2, r0 + mov r4, r1 + + // pre-fetch so we can keep in registers between rounds + add r3, r2, #400 + vldrw.u32 qA00_h, [r3, #A__00] + vldrw.u32 qA00_l, [r2, #A__00] + vldrw.u32 qA20_l, [r2, #A__20] + + wls lr, lr, roundend + roundstart: + // Instructions: 559 + // Expected cycles: 559 + // Expected IPC: 1.00 + // + // ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ cycle (expected) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------> + // 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 550 + // |------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|-------- + vldrw.U32 q6, [r2, #112] // *.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__21 + veor q7, q6, q2 // .*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q2, [r2, #80] // ..*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar2__01 + veor q1, q2, q1 // ...*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + add r5, r2, #400 // ....*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q5, [r5, #80] // .....*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__01 + veor q4, q5, q0 // ......*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q0, [r2, #192] // .......*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__22 + veor q3, q7, q0 // ........*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q0, [r2, #160] // .........*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__02 + veor q1, q1, q0 // ..........*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q0, [r5, #160] // ...........*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__02 + veor q0, q4, q0 // ............*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q6, [r2, #272] // .............*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__23 + veor q2, q3, q6 // ..............*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q7, [r2, #240] // ...............*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__03 + veor q5, q1, q7 // ................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q4, [r5, #240] // .................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__03 + veor q4, q0, q4 // ..................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q6, [r2, #352] // ...................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__24 + veor q3, q2, q6 // ....................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q0, [r2, #320] // .....................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__04 + veor q2, q5, q0 // ......................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q1, [r5, #320] // .......................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__04 + veor q5, q4, q1 // ........................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q4, [r5, #32] // .........................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__20 + veor q0, q3, q5 // ..........................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r5, #16] // ...........................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__10 + veor q6, q1, q0 // ............................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vstrw.32 q5, [r13, #0] // .............................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:writes=stack0 + vshr.U32 q7, q6, #32-((1+1)/2) // ..............................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + add r10, r4, #400 // ...............................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q7, q6, #(1+1)/2 // ................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q6, [r5, #112] // .................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__21 + veor q6, q4, q6 // ..................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q4, [r5, #192] // ...................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__22 + veor q4, q6, q4 // ....................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q6, [r5, #272] // .....................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__23 + veor q4, q4, q6 // ......................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q6, [r5, #352] // .......................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__24 + veor q5, q4, q6 // ........................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q7, [r4, #160] // .........................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q4, q5, #31 // ..........................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vsli.32 q4, q5, #1 // ...........................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q6, [r2, #16] // ............................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__10 + veor q7, q4, q2 // .............................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + veor q1, q6, q7 // ..............................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q6, [r5, #96] // ...............................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__11 + veor q6, q6, q0 // ................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vstrw.32 q1, [r10, #160] // .................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vshr.U32 q1, q6, #32-(44/2) // ..................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vsli.U32 q1, q6, #44/2 // ...................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q6, [r2, #96] // ....................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__11 + veor q4, q6, q7 // .....................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q1, [r10, #16] // ......................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vshr.U32 q6, q4, #32-(44/2) // .......................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q6, q4, #44/2 // ........................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r5, #336] // .........................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__14 + veor q4, q1, q0 // ..........................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r2, #176] // ...........................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__12 + veor q1, q1, q7 // ............................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vstrw.32 q6, [r4, #16] // .............................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vshr.U32 q6, q1, #32-(10/2) // ..............................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vsli.U32 q6, q1, #10/2 // ...............................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r2, #256] // ................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__13 + veor q1, q1, q7 // .................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vstrw.32 q6, [r4, #272] // ..................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vshr.U32 q6, q1, #32-((45-1)/2) // ...................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q6, q1, #(45-1)/2 // ....................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r2, #336] // .....................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__14 + veor q1, q1, q7 // ......................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vstrw.32 q6, [r10, #128] // .......................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q6, q1, #32-(2/2) // ........................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q6, q1, #2/2 // .........................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q7, [r5, #176] // ..........................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__12 + veor q7, q7, q0 // ...........................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q6, [r4, #384] // ............................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vshr.U32 q1, q7, #32-(10/2) // .............................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vsli.U32 q1, q7, #10/2 // ..............................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q6, [r5, #256] // ...............................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__13 + veor q0, q6, q0 // ................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vstrw.32 q1, [r10, #272] // .................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vshr.U32 q1, q4, #32-(2/2) // ..................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q7, [r5, #64] // ...................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__40 + vsli.U32 q1, q4, #2/2 // ....................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q4, [r5, #144] // .....................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__41 + vshr.U32 q6, q0, #32-((45+1)/2) // ......................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vstrw.32 q1, [r10, #384] // .......................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q6, q0, #(45+1)/2 // ........................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + veor q7, q7, q4 // .........................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r5, #224] // ..........................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__42 + veor q4, q7, q1 // ...........................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q7, [r5, #304] // ............................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__43 + veor q1, q4, q7 // .............................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q0, [r5, #384] // ..............................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar3__44 + veor q7, q1, q0 // ...............................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q6, [r4, #128] // ................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vshr.U32 q1, q7, #31 // .................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vsli.32 q1, q7, #1 // ..................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q6, [r2, #144] // ...................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__41 + veor q0, q1, q3 // ....................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r2, #64] // .....................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__40 + veor q1, q3, q6 // ......................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q6, [r2, #224] // .......................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__42 + veor q1, q1, q6 // ........................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r2, #304] // .........................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__43 + veor q6, q1, q3 // ..........................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q4, [r2, #384] // ...........................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__44 + veor q3, q6, q4 // ............................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q4, [r2, #48] // .............................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__30 + veor q5, q3, q5 // ..............................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q1, [r5, #48] // ...............................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__30 + veor q1, q1, q5 // ................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vshr.U32 q6, q1, #32-(28/2) // .................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vsli.U32 q6, q1, #28/2 // ..................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q1, [r2, #128] // ...................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__31 + veor q1, q1, q0 // ....................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q6, [r10, #80] // .....................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q6, q1, #32-((55-1)/2) // ......................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vsli.U32 q6, q1, #(55-1)/2 // .......................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r5, #128] // ........................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__31 + veor q1, q1, q5 // .........................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q6, [r10, #336] // ..........................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q6, q1, #32-((55+1)/2) // ...........................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q6, q1, #(55+1)/2 // ............................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................. + veor q1, q4, q0 // .............................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vstrw.32 q6, [r4, #336] // ..............................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vshr.U32 q4, q1, #32-(28/2) // ...............................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q4, q1, #28/2 // ................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q6, [r2, #208] // .................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__32 + veor q6, q6, q0 // ..................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................ + vstrw.32 q4, [r4, #80] // ...................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q1, q6, #32-((25-1)/2) // ....................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q1, q6, #(25-1)/2 // .....................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q4, [r2, #288] // ......................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar2__33 + veor q4, q4, q0 // .......................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q6, [r2, #368] // ........................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__34 + veor q0, q6, q0 // .........................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q6, q0, #32-(56/2) // ..........................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q1, [r10, #192] // ...........................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q6, q0, #56/2 // ............................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................. + vshr.U32 q0, q4, #32-((21-1)/2) // .............................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q1, [r5, #368] // ..............................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar3__34 + vsli.U32 q0, q4, #(21-1)/2 // ...............................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q6, [r4, #304] // ................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................. + veor q4, q1, q5 // .................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................. + vstrw.32 q0, [r10, #48] // ..................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................ + vshr.U32 q1, q4, #32-(56/2) // ...................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q1, q4, #56/2 // ....................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q6, [r5, #208] // .....................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__32 + veor q6, q6, q5 // ......................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q0, [r5, #288] // .......................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__33 + veor q5, q0, q5 // ........................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q1, [r10, #304] // .........................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q0, q6, #32-((25+1)/2) // ..........................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q0, q6, #(25+1)/2 // ...........................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r5, #96] // ............................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__11 + vshr.U32 q6, q5, #32-((21+1)/2) // .............................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q4, [r5, #16] // ..............................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar3__10 + vsli.U32 q6, q5, #(21+1)/2 // ...............................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q5, [r5, #176] // ................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__12 + veor q1, q4, q1 // .................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q4, [r5, #256] // ..................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar3__13 + veor q5, q1, q5 // ...................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r5, #336] // ....................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__14 + veor q5, q5, q4 // .....................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q0, [r4, #192] // ......................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................ + veor q0, q5, q1 // .......................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q6, [r4, #48] // ........................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q5, q0, #31 // .........................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................... + vsli.32 q5, q0, #1 // ..........................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q4, [r2, #16] // ...........................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__10 + veor q3, q5, q3 // ............................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q6, [r2, #96] // .............................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__11 + veor q4, q4, q6 // ..............................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q1, [r2, #176] // ...............................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__12 + veor q5, q4, q1 // ................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q6, [r2, #256] // .................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__13 + veor q6, q5, q6 // ..................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q4, [r2, #336] // ...................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__14 + veor q5, q6, q4 // ....................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r5, #0] // .....................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__00 + veor q7, q5, q7 // ......................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q4, [r2, #0] // .......................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__00 + veor q1, q1, q7 // ........................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................... + veor q4, q4, q3 // .........................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q6, q1, #32-(0/2) // ..........................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q6, q1, #0/2 // ...........................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r2, #80] // ............................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__01 + veor q1, q1, q3 // .............................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................. + vstrw.32 q6, [r10, #0] // ..............................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................ + vshr.U32 q6, q4, #32-(0/2) // ...............................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q6, q4, #0/2 // ................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q4, [r5, #80] // .................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__01 + veor q4, q4, q7 // ..................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................ + vstrw.32 q6, [r4, #0] // ...................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q6, q1, #32-(36/2) // ....................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q6, q1, #36/2 // .....................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r2, #160] // ......................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar2__02 + veor q1, q1, q3 // .......................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q6, [r4, #256] // ........................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q6, q4, #32-(36/2) // .........................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q6, q4, #36/2 // ..........................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q4, [r2, #240] // ...........................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__03 + veor q4, q4, q3 // ............................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................. + vstrw.32 q6, [r10, #256] // .............................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................. + vshr.U32 q6, q1, #32-((3-1)/2) // ..............................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................ + vsli.U32 q6, q1, #(3-1)/2 // ...............................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r2, #320] // ................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__04 + veor q1, q1, q3 // .................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................. + vstrw.32 q6, [r10, #112] // ..................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................ + vshr.U32 q6, q4, #32-((41-1)/2) // ...................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q6, q4, #(41-1)/2 // ....................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r5, #240] // .....................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__03 + veor q3, q3, q7 // ......................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................ + vstrw.32 q6, [r10, #368] // .......................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q4, q3, #32-((41+1)/2) // ........................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q4, q3, #(41+1)/2 // .........................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r5, #160] // ..........................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__02 + veor q6, q3, q7 // ...........................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q4, [r4, #368] // ............................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................. + vshr.U32 q3, q6, #32-((3+1)/2) // .............................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................. + vsli.U32 q3, q6, #(3+1)/2 // ..............................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q6, [r5, #320] // ...............................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__04 + veor q7, q6, q7 // ................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q4, [r2, #368] // .................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__34 + vshr.U32 q6, q1, #32-(18/2) // ..................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................ + vstrw.32 q3, [r4, #112] // ...................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q6, q1, #18/2 // ....................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q1, q7, #32-(18/2) // .....................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r2, #48] // ......................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar2__30 + vsli.U32 q1, q7, #18/2 // .......................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q7, [r2, #128] // ........................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__31 + veor q3, q3, q7 // .........................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q7, [r2, #208] // ..........................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__32 + veor q7, q3, q7 // ...........................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r2, #288] // ............................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__33 + veor q3, q7, q3 // .............................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q7, [r5, #128] // ..............................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar3__31 + veor q3, q3, q4 // ...............................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q4, [r5, #48] // ................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__30 + veor q0, q3, q0 // .................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................. + veor q4, q4, q7 // ..................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q7, [r5, #208] // ...................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__32 + veor q4, q4, q7 // ....................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q7, [r5, #288] // .....................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__33 + veor q4, q4, q7 // ......................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q7, [r5, #368] // .......................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__34 + veor q7, q4, q7 // ........................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................... + vstrw.32 q6, [r4, #224] // .........................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................... + vshr.U32 q4, q7, #31 // ..........................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................... + vstrw.32 q1, [r10, #224] // ...........................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................... + vsli.32 q4, q7, #1 // ............................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................. + veor q5, q4, q5 // .............................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q6, [r2, #192] // ..............................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar2__22 + veor q1, q6, q5 // ...............................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................... + vldrw.U32 q4, [r5, #112] // ................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__21 + veor q7, q2, q7 // .................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................. + vldrw.U32 q6, [r5, #32] // ..................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar3__20 + vshr.U32 q2, q1, #32-((43-1)/2) // ...................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................... + vsli.U32 q2, q1, #(43-1)/2 // ....................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................... + veor q1, q6, q0 // .....................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................... + vstrw.32 q2, [r10, #32] // ......................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................ + vshr.U32 q6, q1, #32-(62/2) // .......................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................... + vsli.U32 q6, q1, #62/2 // ........................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................... + vldrw.U32 q2, [r2, #112] // .........................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__21 + veor q2, q2, q5 // ..........................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................... + vstrw.32 q6, [r10, #320] // ...........................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................... + vshr.U32 q1, q2, #32-(6/2) // ............................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................. + vsli.U32 q1, q2, #6/2 // .............................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................. + vldrw.U32 q6, [r2, #32] // ..............................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar2__20 + veor q4, q4, q0 // ...............................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................... + vstrw.32 q1, [r4, #176] // ................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................. + veor q2, q6, q5 // .................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................. + vshr.U32 q6, q2, #32-(62/2) // ..................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................ + vldrw.U32 q1, [r5, #352] // ...................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__24 + vsli.U32 q6, q2, #62/2 // ....................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................... + veor q1, q1, q0 // .....................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................... + vstrw.32 q6, [r4, #320] // ......................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................ + vshr.U32 q6, q1, #32-((61+1)/2) // .......................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................... + vsli.U32 q6, q1, #(61+1)/2 // ........................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................... + vldrw.U32 q2, [r5, #192] // .........................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__22 + vshr.U32 q1, q4, #32-(6/2) // ..........................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................... + vstrw.32 q6, [r4, #144] // ...........................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................... + vsli.U32 q1, q4, #6/2 // ............................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................. + veor q2, q2, q0 // .............................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................. + vldrw.U32 q6, [r5, #272] // ..............................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar3__23 + veor q0, q6, q0 // ...............................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................... + vldrw.U32 q4, [r2, #352] // ................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__24 + veor q6, q4, q5 // .................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................. + vldrw.U32 q4, [r2, #272] // ..................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................ // @slothy:reads=Ar2__23 + veor q4, q4, q5 // ...................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................... + vstrw.32 q1, [r10, #176] // ....................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................... + vshr.U32 q1, q2, #32-((43+1)/2) // .....................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................... + vsli.U32 q1, q2, #(43+1)/2 // ......................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................ + vldrw.32 q5, [r13, #0] // .......................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................... // @slothy:reads=stack0 + vshr.U32 q2, q0, #32-((15+1)/2) // ........................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................... + vstrw.32 q1, [r4, #32] // .........................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................... + vsli.U32 q2, q0, #(15+1)/2 // ..........................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................... + vshr.U32 q1, q6, #32-((61-1)/2) // ...........................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................... + vstrw.32 q2, [r4, #288] // ............................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................. + vsli.U32 q1, q6, #(61-1)/2 // .............................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................. + vshr.U32 q6, q4, #32-((15-1)/2) // ..............................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................ + vstrw.32 q1, [r10, #144] // ...............................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................... + vsli.U32 q6, q4, #(15-1)/2 // ................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................. + vshr.U32 q0, q5, #31 // .................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................. + vstrw.32 q6, [r10, #288] // ..................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................ + vsli.32 q0, q5, #1 // ...................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................... + veor q5, q0, q3 // ....................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................... + vldrw.U32 q6, [r2, #64] // .....................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__40 + veor q3, q6, q5 // ......................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................ + vldrw.U32 q1, [r5, #64] // .......................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__40 + vshr.U32 q4, q3, #32-((27-1)/2) // ........................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................... + vldrw.U32 q2, [r2, #384] // .........................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__44 + vsli.U32 q4, q3, #(27-1)/2 // ..........................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................... + vldrw.U32 q0, [r5, #224] // ...........................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__42 + veor q6, q1, q7 // ............................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................. + vstrw.32 q4, [r10, #240] // .............................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................. + veor q2, q2, q5 // ..............................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................ + veor q3, q0, q7 // ...............................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................... + vldrw.U32 q0, [r2, #224] // ................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................. // @slothy:reads=Ar2__42 + vshr.U32 q4, q6, #32-((27+1)/2) // .................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................. + vldrw.U32 q1, [r5, #384] // ..................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................ // @slothy:reads=Ar3__44 + vsli.U32 q4, q6, #(27+1)/2 // ...................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................... + vshr.U32 q6, q2, #32-(14/2) // ....................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................... + vstrw.32 q4, [r4, #240] // .....................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................... + vsli.U32 q6, q2, #14/2 // ......................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................ + vshr.U32 q2, q3, #32-((39+1)/2) // .......................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................... + vstrw.32 q6, [r4, #64] // ........................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................... + vsli.U32 q2, q3, #(39+1)/2 // .........................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................... + veor q0, q0, q5 // ..........................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................... + vldrw.U32 q6, [r2, #144] // ...........................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................... // @slothy:reads=Ar2__41 + veor q4, q1, q7 // ............................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................. + veor q6, q6, q5 // .............................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................. + vstrw.32 q2, [r4, #352] // ..............................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................ + vshr.U32 q2, q4, #32-(14/2) // ...............................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................... + vsli.U32 q2, q4, #14/2 // ................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................. + vldrw.U32 q1, [r2, #304] // .................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................. // @slothy:reads=Ar2__43 + veor q5, q1, q5 // ..................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................ + vldrw.U32 q1, [r5, #144] // ...................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................... // @slothy:reads=Ar3__41 + veor q4, q1, q7 // ....................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................... + vldrw.U32 q3, [r5, #304] // .....................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................... // @slothy:reads=Ar3__43 + veor q1, q3, q7 // ......................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................ + vstrw.32 q2, [r10, #64] // .......................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................... + vshr.U32 q3, q0, #32-((39-1)/2) // ........................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................... + vsli.U32 q3, q0, #(39-1)/2 // .........................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................... + vldrw.U32 q7, [r4, #80] // ..........................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................... // @slothy:reads=Ar4__01 + vshr.U32 q0, q6, #32-(20/2) // ...........................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................... + vstrw.32 q3, [r10, #352] // ............................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................. + vsli.U32 q0, q6, #20/2 // .............................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................. + vshr.U32 q2, q5, #32-(8/2) // ..............................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................ + vsli.U32 q2, q5, #8/2 // ...............................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................... + vldrw.U32 q5, [r4, #112] // ................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................. // @slothy:reads=Ar4__21 + vshr.U32 q3, q1, #32-(8/2) // .................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................. + vsli.U32 q3, q1, #8/2 // ..................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................ + vldrw.U32 q1, [r4, #128] // ...................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................... // @slothy:reads=Ar4__31 + vbic q6, q5, q0 // ....................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................... + vstrw.32 q3, [r10, #208] // .....................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................... + vbic q3, q1, q5 // ......................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................ + veor q3, q0, q3 // .......................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................... + vstrw.32 q3, [r2, #96] // ........................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................... // @slothy:writes=Ar2__11 + vbic q3, q0, q7 // .........................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................... + veor q0, q7, q6 // ..........................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................... + vldrw.U32 q6, [r4, #144] // ...........................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................... // @slothy:reads=Ar4__41 + vbic q7, q7, q6 // ............................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................. + vstrw.32 q0, [r2, #80] // .............................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................. // @slothy:writes=Ar2__01 + veor q3, q6, q3 // ..............................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................ + vstrw.32 q3, [r2, #144] // ...............................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................... // @slothy:writes=Ar2__41 + veor q0, q1, q7 // ................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................. + vstrw.32 q0, [r2, #128] // .................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................. // @slothy:writes=Ar2__31 + vbic q1, q6, q1 // ..................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................ + vshr.U32 q6, q4, #32-(20/2) // ...................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................... + vldrw.U32 q3, [r10, #112] // ....................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................... // @slothy:reads=Ar5__21 + vsli.U32 q6, q4, #20/2 // .....................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................... + vldrw.U32 q4, [r10, #80] // ......................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................ // @slothy:reads=Ar5__01 + veor q1, q5, q1 // .......................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................... + vldrw.U32 q0, [r10, #144] // ........................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................... // @slothy:reads=Ar5__41 + vbic q7, q4, q0 // .........................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................... + vldrw.U32 q5, [r10, #128] // ..........................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................... // @slothy:reads=Ar5__31 + veor q7, q5, q7 // ...........................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................... + vstrw.32 q1, [r2, #112] // ............................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................. // @slothy:writes=Ar2__21 + vbic q1, q0, q5 // .............................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................. + vstrw.32 q7, [r5, #128] // ..............................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................ // @slothy:writes=Ar3__31 + veor q7, q3, q1 // ...............................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................... + vstrw.32 q7, [r5, #112] // ................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................. // @slothy:writes=Ar3__21 + vbic q7, q5, q3 // .................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................. + vbic q1, q3, q6 // ..................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................ + vldrw.U32 q3, [r4, #176] // ...................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................... // @slothy:reads=Ar4__12 + veor q5, q4, q1 // ....................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................... + vbic q4, q6, q4 // .....................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................... + vldrw.U32 q1, [r4, #160] // ......................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................ // @slothy:reads=Ar4__02 + veor q0, q0, q4 // .......................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................... + vldrw.U32 q4, [r4, #224] // ........................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................... // @slothy:reads=Ar4__42 + veor q7, q6, q7 // .........................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................... + vstrw.32 q0, [r5, #144] // ..........................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................... // @slothy:writes=Ar3__41 + vbic q0, q1, q4 // ...........................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................... + vstrw.32 q7, [r5, #96] // ............................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................. // @slothy:writes=Ar3__11 + veor q0, q2, q0 // .............................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................. + vstrw.32 q0, [r2, #208] // ..............................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................ // @slothy:writes=Ar2__32 + vbic q6, q3, q1 // ...............................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................... + vstrw.32 q5, [r5, #80] // ................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................. // @slothy:writes=Ar3__01 + vbic q7, q4, q2 // .................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................. + vldrw.U32 q0, [r10, #160] // ..................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................ // @slothy:reads=Ar5__02 + veor q6, q4, q6 // ...................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................... + vldrw.U32 q5, [r4, #192] // ....................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................... // @slothy:reads=Ar4__22 + vbic q4, q2, q5 // .....................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................... + vldrw.U32 q2, [r10, #224] // ......................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................ // @slothy:reads=Ar5__42 + veor q4, q3, q4 // .......................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................... + vstrw.32 q4, [r2, #176] // ........................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................... // @slothy:writes=Ar2__12 + vbic q4, q5, q3 // .........................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................... + vstrw.32 q6, [r2, #224] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................... // @slothy:writes=Ar2__42 + veor q4, q1, q4 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................... + vldrw.U32 q1, [r10, #208] // ............................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................. // @slothy:reads=Ar5__32 + veor q3, q5, q7 // .............................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................. + vldrw.U32 q5, [r10, #192] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................ // @slothy:reads=Ar5__22 + vbic q6, q1, q5 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................... + vldrw.U32 q7, [r10, #176] // ................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................. // @slothy:reads=Ar5__12 + veor q6, q7, q6 // .................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................. + vstrw.32 q3, [r2, #192] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................ // @slothy:writes=Ar2__22 + vbic q3, q0, q2 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................... + vstrw.32 q6, [r5, #176] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................... // @slothy:writes=Ar3__12 + veor q3, q1, q3 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................... + vstrw.32 q3, [r5, #208] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................ // @slothy:writes=Ar3__32 + vbic q3, q5, q7 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................... + vstrw.32 q4, [r2, #160] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................... // @slothy:writes=Ar2__02 + veor q3, q0, q3 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................... + vstrw.32 q3, [r5, #160] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................... // @slothy:writes=Ar3__02 + vbic q6, q2, q1 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................... + vldrw.U32 q1, [r4, #288] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................. // @slothy:reads=Ar4__33 + vbic q7, q7, q0 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................. + vldrw.U32 q3, [r4, #272] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................ // @slothy:reads=Ar4__23 + veor q0, q5, q6 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................... + vldrw.U32 q4, [r4, #304] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................. // @slothy:reads=Ar4__43 + veor q6, q2, q7 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................. + vldrw.U32 q7, [r4, #256] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................ // @slothy:reads=Ar4__13 + vbic q5, q4, q1 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................... + vstrw.32 q0, [r5, #192] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................... // @slothy:writes=Ar3__22 + veor q5, q3, q5 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................... + vstrw.32 q6, [r5, #224] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................ // @slothy:writes=Ar3__42 + vbic q0, q3, q7 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................... + vstrw.32 q5, [r2, #272] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................... // @slothy:writes=Ar2__23 + vbic q6, q1, q3 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................... + veor q5, q7, q6 // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................... + vldrw.U32 q3, [r4, #240] // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................... // @slothy:reads=Ar4__03 + veor q6, q3, q0 // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................. + vldrw.U32 q2, [r10, #288] // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................. // @slothy:reads=Ar5__33 + vbic q0, q3, q4 // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................ + vstrw.32 q6, [r2, #240] // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................... // @slothy:writes=Ar2__03 + vbic q7, q7, q3 // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................. + vstrw.32 q5, [r2, #256] // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................. // @slothy:writes=Ar2__13 + veor q7, q4, q7 // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................ + vstrw.32 q7, [r2, #304] // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................... // @slothy:writes=Ar2__43 + veor q7, q1, q0 // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................... + vstrw.32 q7, [r2, #288] // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................... // @slothy:writes=Ar2__33 + vldrw.U32 q5, [r10, #304] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................ // @slothy:reads=Ar5__43 + vbic q7, q5, q2 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................... + vldrw.U32 q3, [r10, #272] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................... // @slothy:reads=Ar5__23 + veor q1, q3, q7 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................... + vldrw.U32 q7, [r4, #336] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................... // @slothy:reads=Ar4__14 + vbic q4, q2, q3 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................... + vldrw.U32 q6, [r10, #256] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................. // @slothy:reads=Ar5__13 + vbic q3, q3, q6 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................. + vldrw.U32 q0, [r10, #240] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................ // @slothy:reads=Ar5__03 + veor q3, q0, q3 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................... + vstrw.32 q1, [r5, #272] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................. // @slothy:writes=Ar3__23 + vbic q1, q0, q5 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................. + vstrw.32 q3, [r5, #240] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................ // @slothy:writes=Ar3__03 + veor q1, q2, q1 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................... + vldrw.U32 q3, [r4, #384] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................... // @slothy:reads=Ar4__44 + vbic q2, q6, q0 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................... + vldrw.U32 q0, [r4, #320] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................ // @slothy:reads=Ar4__04 + veor q2, q5, q2 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................... + vldrw.U32 q5, [r4, #352] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................... // @slothy:reads=Ar4__24 + veor q4, q6, q4 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................... + vstrw.32 q2, [r5, #304] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................... // @slothy:writes=Ar3__43 + vbic q2, q7, q0 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................... + vstrw.32 q1, [r5, #288] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................. // @slothy:writes=Ar3__33 + veor q1, q3, q2 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................. + vstrw.32 q1, [r2, #384] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................ // @slothy:writes=Ar2__44 + vbic q2, q5, q7 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................... + vstrw.32 q4, [r5, #256] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................. // @slothy:writes=Ar3__13 + veor q4, q0, q2 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................. + vstrw.32 q4, [r2, #320] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................ // @slothy:writes=Ar2__04 + vbic q2, q0, q3 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................... + vldrw.U32 q4, [r4, #368] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................... // @slothy:reads=Ar4__34 + vbic q3, q3, q4 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................... + vldrw.U32 q0, [r10, #320] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................ // @slothy:reads=Ar5__04 + veor q1, q5, q3 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................... + vldrw.U32 q6, [r10, #336] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................... // @slothy:reads=Ar5__14 + vbic q5, q4, q5 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................... + vstrw.32 q1, [r2, #352] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................... // @slothy:writes=Ar2__24 + veor q5, q7, q5 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................... + vstrw.32 q5, [r2, #336] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................. // @slothy:writes=Ar2__14 + veor q3, q4, q2 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................. + vstrw.32 q3, [r2, #368] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................ // @slothy:writes=Ar2__34 + vbic q7, q6, q0 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................... + vldrw.U32 q5, [r10, #352] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................. // @slothy:reads=Ar5__24 + vbic q3, q5, q6 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................. + vldrw.U32 q1, [r10, #368] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................ // @slothy:reads=Ar5__34 + vbic q4, q1, q5 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................... + vldrw.U32 q2, [r4, #16] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................... // @slothy:reads=Ar4__10 + veor q6, q6, q4 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................... + vldrw.U32 q4, [r10, #384] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................ // @slothy:reads=Ar5__44 + veor q3, q0, q3 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................... + vstrw.32 q3, [r5, #320] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................... // @slothy:writes=Ar3__04 + veor q3, q4, q7 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................... + vstrw.32 q3, [r5, #384] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................... // @slothy:writes=Ar3__44 + vbic q0, q0, q4 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................... + vstrw.32 q6, [r5, #336] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................. // @slothy:writes=Ar3__14 + veor q3, q1, q0 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................. + vstrw.32 q3, [r5, #368] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................ // @slothy:writes=Ar3__34 + vbic q7, q4, q1 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................... + veor q5, q5, q7 // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................. + vldrw.U32 q6, [r4, #32] // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................. // @slothy:reads=Ar4__20 + vbic q3, q6, q2 // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................ + vldrw.U32 q4, [r4, #48] // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................... // @slothy:reads=Ar4__30 + vbic q0, q4, q6 // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................... + vldrw.U32 q1, [r4, #0] // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................... // @slothy:reads=Ar4__00 + veor q0, q2, q0 // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................ + vldrw.U32 q7, [r4, #64] // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................... // @slothy:reads=Ar4__40 + veor q3, q1, q3 // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................... + vstrw.32 q5, [r5, #352] // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................... // @slothy:writes=Ar3__24 + vbic q5, q1, q7 // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................... + vstrw.32 q0, [r2, #16] // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................... // @slothy:writes=Ar2__10 + veor q0, q4, q5 // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................. + vstrw.32 q0, [r2, #48] // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................. // @slothy:writes=Ar2__30 + vbic q5, q2, q1 // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................ + veor q2, q7, q5 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................... + vldrw.U32 q0, [r10, #16] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................. // @slothy:reads=Ar5__10 + vbic q5, q7, q4 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................. + vldrw.U32 q4, [r10, #0] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................ // @slothy:reads=Ar5__00 + vbic q1, q0, q4 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................... + vldrw.U32 q7, [r10, #64] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................... // @slothy:reads=Ar5__40 + veor q1, q7, q1 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................... + vstrw.32 q2, [r2, #64] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................ // @slothy:writes=Ar2__40 + veor q2, q6, q5 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................... + vbic q6, q4, q7 // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................... + vldrw.U32 q5, [r10, #48] // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................... // @slothy:reads=Ar5__30 + veor q6, q5, q6 // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................... + ldrd r7, r8, [r6] // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................... + vbic q7, q7, q5 // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................. + vstrw.32 q1, [r5, #64] // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................. // @slothy:writes=Ar3__40 + vdup.32 q1, r7 // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................ + veor q1, q3, q1 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............... + vldrw.U32 q3, [r10, #32] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............. // @slothy:reads=Ar5__20 + veor q7, q3, q7 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............. + add r6, r6, #8 // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............ + vbic q5, q5, q3 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........... + vstrw.32 q6, [r5, #48] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......... // @slothy:writes=Ar3__30 + vbic q6, q3, q0 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......... + vstrw.32 q1, [r2, #0] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........ // @slothy:writes=Ar2__00 + veor q5, q0, q5 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....... + vstrw.32 q7, [r5, #32] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...... // @slothy:writes=Ar3__20 + veor q4, q4, q6 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..... + vstrw.32 q5, [r5, #16] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.... // @slothy:writes=Ar3__10 + vdup.32 q6, r8 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*... + vstrw.32 q2, [r2, #32] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.. // @slothy:writes=Ar2__20 + veor q0, q4, q6 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*. + vstrw.32 q0, [r5, #0] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................* // @slothy:writes=Ar3__00 + + // ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ cycle (expected) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------> + // 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 550 + // |------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|-------- + // add r5, r2, #400 // ....*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // add r10, r4, #400 // ...............................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #80] // .....*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q5, q6, q0 // ......*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q4, [r5, #160] // ...........*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #240] // .................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q4, q5, q4 // ............*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q4, q4, q6 // ..................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q6, [r5, #320] // .......................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q5, q4, q6 // ........................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r2, #112] // *.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q4, q6, q2 // .*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q6, [r2, #192] // .......*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q4, q6 // ........*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r2, #272] // .............*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q4, q4, q6 // ..............*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q6, [r2, #352] // ...................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q4, q6 // ....................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q0, q3, q5 // ..........................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r13, #0] // .............................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q6, [r2, #80] // ..*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // veor q4, q6, q1 // ...*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r2, #160] // .........*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q4, q6 // ..........*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r2, #240] // ...............*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q4, q6 // ................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q6, [r2, #320] // .....................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q2, q4, q6 // ......................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q4, [r5, #32] // .........................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #112] // .................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q4, q4, q6 // ..................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q6, [r5, #192] // ...................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q4, q6 // ....................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #272] // .....................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q4, q6 // ......................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q6, [r5, #352] // .......................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q5, q4, q6 // ........................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q1, q5, #31 // ..........................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.32 q1, q5, #1 // ...........................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q7, q1, q2 // .............................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q4, [r2, #16] // ............................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q6, [r5, #16] // ...........................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q4, q7 // ..............................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // veor q6, q6, q0 // ............................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vstrw.32 q4, [r10, #160] // .................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vshr.U32 q1, q6, #32-((1+1)/2) // ..............................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vsli.U32 q1, q6, #(1+1)/2 // ................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vstrw.32 q1, [r4, #160] // .........................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q4, [r2, #96] // ....................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #96] // ...............................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q4, q7 // .....................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q6, q6, q0 // ................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vshr.U32 q1, q4, #32-(44/2) // .......................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q1, q4, #44/2 // ........................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q1, [r4, #16] // .............................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vshr.U32 q4, q6, #32-(44/2) // ..................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vsli.U32 q4, q6, #44/2 // ...................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q4, [r10, #16] // ......................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q1, [r2, #176] // ...........................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #176] // ..........................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q6, q0 // ...........................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q1, q1, q7 // ............................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vshr.U32 q6, q1, #32-(10/2) // ..............................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vsli.U32 q6, q1, #10/2 // ...............................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r4, #272] // ..................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vshr.U32 q6, q4, #32-(10/2) // .............................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vsli.U32 q6, q4, #10/2 // ..............................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vstrw.32 q6, [r10, #272] // .................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q4, [r2, #256] // ................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q6, [r5, #256] // ...............................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q1, q4, q7 // .................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q4, q6, q0 // ................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vshr.U32 q6, q1, #32-((45-1)/2) // ...................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q1, #(45-1)/2 // ....................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r10, #128] // .......................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q4, #32-((45+1)/2) // ......................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vsli.U32 q6, q4, #(45+1)/2 // ........................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r4, #128] // ................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q4, [r2, #336] // .....................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #336] // .........................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q1, q4, q7 // ......................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // veor q4, q6, q0 // ..........................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q1, #32-(2/2) // ........................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q1, #2/2 // .........................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r4, #384] // ............................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vshr.U32 q6, q4, #32-(2/2) // ..................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vsli.U32 q6, q4, #2/2 // ....................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r10, #384] // .......................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q4, [r5, #64] // ...................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #144] // .....................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q4, q6 // .........................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #224] // ..........................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q4, q6 // ...........................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #304] // ............................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q4, q4, q6 // .............................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q6, [r5, #384] // ..............................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // veor q7, q4, q6 // ...............................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q7, #31 // .................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vsli.32 q6, q7, #1 // ..................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // veor q0, q6, q3 // ....................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q4, [r2, #64] // .....................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r2, #144] // ...................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q4, q6 // ......................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q6, [r2, #224] // .......................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q4, q6 // ........................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r2, #304] // .........................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q4, q6 // ..........................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r2, #384] // ...........................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q4, q6 // ............................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q5, q3, q5 // ..............................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q4, [r2, #48] // .............................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q6, [r5, #48] // ...............................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q1, q4, q0 // .............................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q4, q6, q5 // ................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vshr.U32 q6, q1, #32-(28/2) // ...............................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q1, #28/2 // ................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vstrw.32 q6, [r4, #80] // ...................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q4, #32-(28/2) // .................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vsli.U32 q6, q4, #28/2 // ..................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vstrw.32 q6, [r10, #80] // .....................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r2, #128] // ...................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q1, q6, q0 // ....................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #128] // ........................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q6, q5 // .........................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q1, #32-((55-1)/2) // ......................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vsli.U32 q6, q1, #(55-1)/2 // .......................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r10, #336] // ..........................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q4, #32-((55+1)/2) // ...........................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q4, #(55+1)/2 // ............................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vstrw.32 q6, [r4, #336] // ..............................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q4, [r2, #208] // .................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q6, [r5, #208] // .....................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q1, q4, q0 // ..................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................ + // veor q4, q6, q5 // ......................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................ + // vshr.U32 q6, q1, #32-((25-1)/2) // ....................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q1, #(25-1)/2 // .....................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r10, #192] // ...........................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q4, #32-((25+1)/2) // ..........................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q4, #(25+1)/2 // ...........................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r4, #192] // ......................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q4, [r2, #288] // ......................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q6, [r5, #288] // .......................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q1, q4, q0 // .......................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q6, q5 // ........................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q1, #32-((21-1)/2) // .............................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vsli.U32 q6, q1, #(21-1)/2 // ...............................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r10, #48] // ..................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................ + // vshr.U32 q6, q4, #32-((21+1)/2) // .............................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................. + // vsli.U32 q6, q4, #(21+1)/2 // ...............................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r4, #48] // ........................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q4, [r2, #368] // ........................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #368] // ..............................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................ + // veor q1, q4, q0 // .........................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q6, q5 // .................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................. + // vshr.U32 q6, q1, #32-(56/2) // ..........................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q1, #56/2 // ............................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vstrw.32 q6, [r4, #304] // ................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................. + // vshr.U32 q6, q4, #32-(56/2) // ...................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q4, #56/2 // ....................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r10, #304] // .........................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q4, [r5, #16] // ..............................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q6, [r5, #96] // ............................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q4, q4, q6 // .................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q6, [r5, #176] // ................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q4, q4, q6 // ...................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #256] // ..................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................ + // veor q4, q4, q6 // .....................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #336] // ....................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q0, q4, q6 // .......................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q0, #31 // .........................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.32 q6, q0, #1 // ..........................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q6, q3 // ............................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q6, [r2, #96] // .............................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q4, [r2, #16] // ...........................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q4, q6 // ..............................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q6, [r2, #176] // ...............................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q4, q6 // ................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q6, [r2, #256] // .................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................. + // veor q4, q4, q6 // ..................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q6, [r2, #336] // ...................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................... + // veor q5, q4, q6 // ....................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................... + // veor q7, q5, q7 // ......................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q4, [r2, #0] // .......................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #0] // .....................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................... + // veor q1, q4, q3 // .........................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q6, q7 // ........................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q1, #32-(0/2) // ...............................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q1, #0/2 // ................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................. + // vstrw.32 q6, [r4, #0] // ...................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q4, #32-(0/2) // ..........................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q4, #0/2 // ...........................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r10, #0] // ..............................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q4, [r2, #80] // ............................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q6, [r5, #80] // .................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................. + // veor q1, q4, q3 // .............................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................. + // veor q4, q6, q7 // ..................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................ + // vshr.U32 q6, q1, #32-(36/2) // ....................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q1, #36/2 // .....................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r4, #256] // ........................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q4, #32-(36/2) // .........................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q4, #36/2 // ..........................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r10, #256] // .............................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q4, [r2, #160] // ......................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q6, [r5, #160] // ..........................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................... + // veor q1, q4, q3 // .......................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q6, q7 // ...........................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q1, #32-((3-1)/2) // ..............................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................ + // vsli.U32 q6, q1, #(3-1)/2 // ...............................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r10, #112] // ..................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................ + // vshr.U32 q6, q4, #32-((3+1)/2) // .............................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................. + // vsli.U32 q6, q4, #(3+1)/2 // ..............................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................ + // vstrw.32 q6, [r4, #112] // ...................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q4, [r2, #240] // ...........................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #240] // .....................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................... + // veor q1, q4, q3 // ............................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................. + // veor q4, q6, q7 // ......................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................ + // vshr.U32 q6, q1, #32-((41-1)/2) // ...................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q1, #(41-1)/2 // ....................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r10, #368] // .......................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q4, #32-((41+1)/2) // ........................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q4, #(41+1)/2 // .........................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r4, #368] // ............................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q4, [r2, #320] // ................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q6, [r5, #320] // ...............................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................... + // veor q1, q4, q3 // .................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................. + // veor q4, q6, q7 // ................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................. + // vshr.U32 q6, q1, #32-(18/2) // ..................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................ + // vsli.U32 q6, q1, #18/2 // ....................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r4, #224] // .........................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q4, #32-(18/2) // .....................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q4, #18/2 // .......................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r10, #224] // ...........................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q4, [r2, #48] // ......................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q6, [r2, #128] // ........................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................... + // veor q4, q4, q6 // .........................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r2, #208] // ..........................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................... + // veor q4, q4, q6 // ...........................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r2, #288] // ............................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................. + // veor q4, q4, q6 // .............................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q6, [r2, #368] // .................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................. + // veor q3, q4, q6 // ...............................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................... + // veor q0, q3, q0 // .................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q4, [r5, #48] // ................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q6, [r5, #128] // ..............................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................ + // veor q4, q4, q6 // ..................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q6, [r5, #208] // ...................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................... + // veor q4, q4, q6 // ....................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #288] // .....................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................... + // veor q4, q4, q6 // ......................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q6, [r5, #368] // .......................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................... + // veor q7, q4, q6 // ........................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q7, #31 // ..........................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................... + // vsli.32 q6, q7, #1 // ............................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................. + // veor q5, q6, q5 // .............................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q4, [r2, #32] // ..............................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q6, [r5, #32] // ..................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................ + // veor q1, q4, q5 // .................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................. + // veor q4, q6, q0 // .....................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q1, #32-(62/2) // ..................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................ + // vsli.U32 q6, q1, #62/2 // ....................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r4, #320] // ......................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................ + // vshr.U32 q6, q4, #32-(62/2) // .......................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q4, #62/2 // ........................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r10, #320] // ...........................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q4, [r2, #112] // .........................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #112] // ................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................. + // veor q1, q4, q5 // ..........................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................... + // veor q4, q6, q0 // ...............................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q1, #32-(6/2) // ............................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................. + // vsli.U32 q6, q1, #6/2 // .............................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................. + // vstrw.32 q6, [r4, #176] // ................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................. + // vshr.U32 q6, q4, #32-(6/2) // ..........................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q4, #6/2 // ............................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................. + // vstrw.32 q6, [r10, #176] // ....................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................... + // vldrw.U32 q4, [r2, #192] // ..............................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q6, [r5, #192] // .........................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................... + // veor q1, q4, q5 // ...............................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................... + // veor q4, q6, q0 // .............................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................. + // vshr.U32 q6, q1, #32-((43-1)/2) // ...................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q1, #(43-1)/2 // ....................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r10, #32] // ......................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................ + // vshr.U32 q6, q4, #32-((43+1)/2) // .....................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q4, #(43+1)/2 // ......................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................ + // vstrw.32 q6, [r4, #32] // .........................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................... + // vldrw.U32 q4, [r2, #272] // ..................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................ + // vldrw.U32 q6, [r5, #272] // ..............................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................ + // veor q1, q4, q5 // ...................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................... + // veor q4, q6, q0 // ...............................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q1, #32-((15-1)/2) // ..............................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................ + // vsli.U32 q6, q1, #(15-1)/2 // ................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................. + // vstrw.32 q6, [r10, #288] // ..................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................ + // vshr.U32 q6, q4, #32-((15+1)/2) // ........................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q4, #(15+1)/2 // ..........................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r4, #288] // ............................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................. + // vldrw.U32 q4, [r2, #352] // ................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................. + // vldrw.U32 q6, [r5, #352] // ...................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................... + // veor q1, q4, q5 // .................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................. + // veor q4, q6, q0 // .....................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q1, #32-((61-1)/2) // ...........................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q1, #(61-1)/2 // .............................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................. + // vstrw.32 q6, [r10, #144] // ...............................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................... + // vshr.U32 q6, q4, #32-((61+1)/2) // .......................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................... + // vsli.U32 q6, q4, #(61+1)/2 // ........................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r4, #144] // ...........................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................... + // veor q7, q2, q7 // .................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................. + // vldrw.32 q4, [r13, #0] // .......................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................... + // vshr.U32 q6, q4, #31 // .................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................. + // vsli.32 q6, q4, #1 // ...................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................... + // veor q5, q6, q3 // ....................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................... + // vldrw.U32 q4, [r2, #64] // .....................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #64] // .......................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................... + // veor q1, q4, q5 // ......................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................ + // veor q4, q6, q7 // ............................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................. + // vshr.U32 q6, q1, #32-((27-1)/2) // ........................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................... + // vsli.U32 q6, q1, #(27-1)/2 // ..........................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................... + // vstrw.32 q6, [r10, #240] // .............................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................. + // vshr.U32 q6, q4, #32-((27+1)/2) // .................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................. + // vsli.U32 q6, q4, #(27+1)/2 // ...................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................... + // vstrw.32 q6, [r4, #240] // .....................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................... + // vldrw.U32 q4, [r2, #224] // ................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................. + // vldrw.U32 q6, [r5, #224] // ...........................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................... + // veor q1, q4, q5 // ..........................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................... + // veor q4, q6, q7 // ...............................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................... + // vshr.U32 q6, q1, #32-((39-1)/2) // ........................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................... + // vsli.U32 q6, q1, #(39-1)/2 // .........................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................... + // vstrw.32 q6, [r10, #352] // ............................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................. + // vshr.U32 q6, q4, #32-((39+1)/2) // .......................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................... + // vsli.U32 q6, q4, #(39+1)/2 // .........................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................... + // vstrw.32 q6, [r4, #352] // ..............................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................ + // vldrw.U32 q4, [r2, #384] // .........................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #384] // ..................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................ + // veor q1, q4, q5 // ..............................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................ + // veor q4, q6, q7 // ............................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................. + // vshr.U32 q6, q1, #32-(14/2) // ....................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................... + // vsli.U32 q6, q1, #14/2 // ......................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................ + // vstrw.32 q6, [r4, #64] // ........................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................... + // vshr.U32 q6, q4, #32-(14/2) // ...............................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................... + // vsli.U32 q6, q4, #14/2 // ................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................. + // vstrw.32 q6, [r10, #64] // .......................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................... + // vldrw.U32 q6, [r2, #304] // .................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................. + // vldrw.U32 q4, [r5, #304] // .....................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................... + // veor q6, q6, q5 // ..................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................ + // veor q4, q4, q7 // ......................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................ + // vshr.U32 q2, q6, #32-(8/2) // ..............................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................ + // vsli.U32 q2, q6, #8/2 // ...............................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................... + // vshr.U32 q6, q4, #32-(8/2) // .................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................. + // vsli.U32 q6, q4, #8/2 // ..................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................ + // vstrw.32 q6, [r10, #208] // .....................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................... + // vldrw.U32 q4, [r2, #144] // ...........................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................... + // vldrw.U32 q6, [r5, #144] // ...................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................... + // veor q4, q4, q5 // .............................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................. + // veor q6, q6, q7 // ....................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................... + // vshr.U32 q3, q4, #32-(20/2) // ...........................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................... + // vsli.U32 q3, q4, #20/2 // .............................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................. + // vshr.U32 q0, q6, #32-(20/2) // ...................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................... + // vsli.U32 q0, q6, #20/2 // .....................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................... + // vldrw.U32 q7, [r4, #80] // ..........................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................... + // vldrw.U32 q5, [r4, #112] // ................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................. + // vbic q6, q5, q3 // ....................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................... + // veor q6, q7, q6 // ..........................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................... + // vstrw.32 q6, [r2, #80] // .............................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................. + // vldrw.U32 q1, [r4, #128] // ...................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................... + // vbic q6, q1, q5 // ......................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................ + // veor q6, q3, q6 // .......................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................... + // vstrw.32 q6, [r2, #96] // ........................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................... + // vldrw.U32 q4, [r4, #144] // ...........................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................... + // vbic q6, q4, q1 // ..................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................ + // veor q6, q5, q6 // .......................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................... + // vstrw.32 q6, [r2, #112] // ............................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................. + // vbic q6, q7, q4 // ............................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................. + // veor q6, q1, q6 // ................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................. + // vstrw.32 q6, [r2, #128] // .................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................. + // vbic q6, q3, q7 // .........................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................... + // veor q6, q4, q6 // ..............................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................ + // vstrw.32 q6, [r2, #144] // ...............................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................... + // vldrw.U32 q7, [r10, #80] // ......................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................ + // vldrw.U32 q5, [r10, #112] // ....................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................... + // vbic q6, q5, q0 // ..................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................ + // veor q6, q7, q6 // ....................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................... + // vstrw.32 q6, [r5, #80] // ................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................. + // vldrw.U32 q1, [r10, #128] // ..........................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................... + // vbic q6, q1, q5 // .................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................. + // veor q6, q0, q6 // .........................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................... + // vstrw.32 q6, [r5, #96] // ............................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................. + // vldrw.U32 q4, [r10, #144] // ........................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................... + // vbic q6, q4, q1 // .............................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................. + // veor q6, q5, q6 // ...............................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................... + // vstrw.32 q6, [r5, #112] // ................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................. + // vbic q6, q7, q4 // .........................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................... + // veor q6, q1, q6 // ...........................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................... + // vstrw.32 q6, [r5, #128] // ..............................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................ + // vbic q6, q0, q7 // .....................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................... + // veor q6, q4, q6 // .......................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................... + // vstrw.32 q6, [r5, #144] // ..........................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................... + // vldrw.U32 q7, [r4, #160] // ......................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................ + // vldrw.U32 q5, [r4, #176] // ...................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................... + // vldrw.U32 q1, [r4, #192] // ....................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................... + // vbic q6, q1, q5 // .........................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................... + // veor q6, q7, q6 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................... + // vstrw.32 q6, [r2, #160] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................... + // vbic q6, q2, q1 // .....................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................... + // veor q6, q5, q6 // .......................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................... + // vstrw.32 q6, [r2, #176] // ........................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................... + // vldrw.U32 q4, [r4, #224] // ........................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................... + // vbic q6, q4, q2 // .................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................. + // veor q6, q1, q6 // .............................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................. + // vstrw.32 q6, [r2, #192] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................ + // vbic q6, q7, q4 // ...........................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................... + // veor q6, q2, q6 // .............................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................. + // vstrw.32 q6, [r2, #208] // ..............................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................ + // vbic q6, q5, q7 // ...............................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................... + // veor q6, q4, q6 // ...................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................... + // vstrw.32 q6, [r2, #224] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................... + // vldrw.U32 q0, [r10, #160] // ..................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................ + // vldrw.U32 q7, [r10, #176] // ................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................. + // vldrw.U32 q5, [r10, #192] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................ + // vbic q6, q5, q7 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................... + // veor q6, q0, q6 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................... + // vstrw.32 q6, [r5, #160] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................... + // vldrw.U32 q1, [r10, #208] // ............................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................. + // vbic q6, q1, q5 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................... + // veor q6, q7, q6 // .................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................. + // vstrw.32 q6, [r5, #176] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................... + // vldrw.U32 q4, [r10, #224] // ......................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................ + // vbic q6, q4, q1 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................... + // veor q6, q5, q6 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................... + // vstrw.32 q6, [r5, #192] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................... + // vbic q6, q0, q4 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................... + // veor q6, q1, q6 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................... + // vstrw.32 q6, [r5, #208] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................ + // vbic q6, q7, q0 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................. + // veor q6, q4, q6 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................. + // vstrw.32 q6, [r5, #224] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................ + // vldrw.U32 q0, [r4, #240] // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................... + // vldrw.U32 q7, [r4, #256] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................ + // vldrw.U32 q5, [r4, #272] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................ + // vbic q6, q5, q7 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................... + // veor q6, q0, q6 // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................. + // vstrw.32 q6, [r2, #240] // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................... + // vldrw.U32 q1, [r4, #288] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................. + // vbic q6, q1, q5 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................... + // veor q6, q7, q6 // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................... + // vstrw.32 q6, [r2, #256] // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................. + // vldrw.U32 q4, [r4, #304] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................. + // vbic q6, q4, q1 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................... + // veor q6, q5, q6 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................... + // vstrw.32 q6, [r2, #272] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................... + // vbic q6, q0, q4 // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................ + // veor q6, q1, q6 // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................... + // vstrw.32 q6, [r2, #288] // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................... + // vbic q6, q7, q0 // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................. + // veor q6, q4, q6 // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................ + // vstrw.32 q6, [r2, #304] // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................... + // vldrw.U32 q0, [r10, #240] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................ + // vldrw.U32 q7, [r10, #256] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................. + // vldrw.U32 q5, [r10, #272] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................... + // vbic q6, q5, q7 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................. + // veor q6, q0, q6 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................... + // vstrw.32 q6, [r5, #240] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................ + // vldrw.U32 q1, [r10, #288] // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................. + // vbic q6, q1, q5 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................... + // veor q6, q7, q6 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................... + // vstrw.32 q6, [r5, #256] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................. + // vldrw.U32 q4, [r10, #304] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................ + // vbic q6, q4, q1 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................... + // veor q6, q5, q6 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................... + // vstrw.32 q6, [r5, #272] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................. + // vbic q6, q0, q4 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................. + // veor q6, q1, q6 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................... + // vstrw.32 q6, [r5, #288] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................. + // vbic q6, q7, q0 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................... + // veor q6, q4, q6 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................... + // vstrw.32 q6, [r5, #304] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................... + // vldrw.U32 q0, [r4, #320] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................ + // vldrw.U32 q7, [r4, #336] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................... + // vldrw.U32 q5, [r4, #352] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................... + // vbic q6, q5, q7 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................... + // veor q6, q0, q6 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................. + // vstrw.32 q6, [r2, #320] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................ + // vldrw.U32 q1, [r4, #368] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................... + // vbic q6, q1, q5 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................... + // veor q6, q7, q6 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................... + // vstrw.32 q6, [r2, #336] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................. + // vldrw.U32 q4, [r4, #384] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................... + // vbic q6, q4, q1 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................... + // veor q6, q5, q6 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................... + // vstrw.32 q6, [r2, #352] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................... + // vbic q6, q0, q4 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................... + // veor q6, q1, q6 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................. + // vstrw.32 q6, [r2, #368] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................ + // vbic q6, q7, q0 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................... + // veor q6, q4, q6 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................. + // vstrw.32 q6, [r2, #384] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................ + // vldrw.U32 q0, [r10, #320] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................ + // vldrw.U32 q7, [r10, #336] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................... + // vldrw.U32 q5, [r10, #352] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................. + // vbic q6, q5, q7 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................. + // veor q6, q0, q6 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................... + // vstrw.32 q6, [r5, #320] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................... + // vldrw.U32 q1, [r10, #368] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................ + // vbic q6, q1, q5 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................... + // veor q6, q7, q6 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................... + // vstrw.32 q6, [r5, #336] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................. + // vldrw.U32 q4, [r10, #384] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................ + // vbic q6, q4, q1 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................... + // veor q6, q5, q6 // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................. + // vstrw.32 q6, [r5, #352] // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................... + // vbic q6, q0, q4 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................... + // veor q6, q1, q6 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................. + // vstrw.32 q6, [r5, #368] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................ + // vbic q6, q7, q0 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................... + // veor q6, q4, q6 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................... + // vstrw.32 q6, [r5, #384] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................... + // vldrw.U32 q0, [r4, #16] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................... + // vldrw.U32 q7, [r4, #32] // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................. + // vldrw.U32 q5, [r4, #48] // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................... + // vbic q6, q5, q7 // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................... + // veor q6, q0, q6 // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................ + // vstrw.32 q6, [r2, #16] // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................... + // vldrw.U32 q1, [r4, #64] // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................... + // vbic q6, q1, q5 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................. + // veor q2, q7, q6 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................... + // vstrw.32 q2, [r2, #32] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.. + // vldrw.U32 q4, [r4, #0] // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................... + // vbic q6, q4, q1 // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................... + // veor q6, q5, q6 // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................. + // vstrw.32 q6, [r2, #48] // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................. + // vbic q6, q0, q4 // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................ + // veor q6, q1, q6 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................... + // vstrw.32 q6, [r2, #64] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................ + // vbic q6, q7, q0 // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................ + // veor q3, q4, q6 // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................... + // vldrw.U32 q0, [r10, #16] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................. + // vldrw.U32 q7, [r10, #32] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............. + // vldrw.U32 q5, [r10, #48] // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................... + // vbic q6, q5, q7 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........... + // veor q6, q0, q6 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....... + // vstrw.32 q6, [r5, #16] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.... + // vldrw.U32 q1, [r10, #64] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................... + // vbic q6, q1, q5 // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................. + // veor q6, q7, q6 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............. + // vstrw.32 q6, [r5, #32] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...... + // vldrw.U32 q4, [r10, #0] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................ + // vbic q6, q4, q1 // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................... + // veor q6, q5, q6 // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................... + // vstrw.32 q6, [r5, #48] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......... + // vbic q6, q0, q4 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................... + // veor q6, q1, q6 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................... + // vstrw.32 q6, [r5, #64] // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................. + // vbic q6, q7, q0 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......... + // veor q4, q4, q6 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..... + // ldrd r10, r8, [r6] // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................... + // vdup.32 q6, r10 // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................ + // veor q1, q3, q6 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............... + // vstrw.32 q1, [r2, #0] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........ + // vdup.32 q6, r8 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*... + // veor q0, q4, q6 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*. + // vstrw.32 q0, [r5, #0] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................* + // add r6, r6, #8 // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............ + + roundend_pre: + + + le lr, roundstart +roundend: + add sp, #8*16 + + vpop {d8-d15} + ldmia.w sp!, {r3,r4,r5,r6,r7,r8,r9,r10,r11,r12, pc} \ No newline at end of file diff --git a/examples/opt/armv8m/keccak/mve-keccak-4x_opt_m85.s b/examples/opt/armv8m/keccak/mve-keccak-4x_opt_m85.s new file mode 100644 index 000000000..b268c4d92 --- /dev/null +++ b/examples/opt/armv8m/keccak/mve-keccak-4x_opt_m85.s @@ -0,0 +1,1646 @@ + +/// +/// Copyright (c) 2025 Arm Limited +/// SPDX-License-Identifier: Apache-2.0 OR MIT OR ISC +/// + +.thumb +.syntax unified +.text +.equ QSTACK0, 0 +.equ A__00, 0 +.equ A__01, 80 +.equ A__02, 160 +.equ A__03, 240 +.equ A__04, 320 +.equ A__10, 16 +.equ A__11, 96 +.equ A__12, 176 +.equ A__13, 256 +.equ A__14, 336 +.equ A__20, 32 +.equ A__21, 112 +.equ A__22, 192 +.equ A__23, 272 +.equ A__24, 352 +.equ A__30, 48 +.equ A__31, 128 +.equ A__32, 208 +.equ A__33, 288 +.equ A__34, 368 +.equ A__40, 64 +.equ A__41, 144 +.equ A__42, 224 +.equ A__43, 304 +.equ A__44, 384 +.equ B__00, 0 +.equ B__01, 256 +.equ B__02, 112 +.equ B__03, 368 +.equ B__04, 224 +.equ B__10, 160 +.equ B__11, 16 +.equ B__12, 272 +.equ B__13, 128 +.equ B__14, 384 +.equ B__20, 320 +.equ B__21, 176 +.equ B__22, 32 +.equ B__23, 288 +.equ B__24, 144 +.equ B__30, 80 +.equ B__31, 336 +.equ B__32, 192 +.equ B__33, 48 +.equ B__34, 304 +.equ B__40, 240 +.equ B__41, 96 +.equ B__42, 352 +.equ B__43, 208 +.equ B__44, 64 +.equ RCxy_00, 0 +.equ RCxy_01, 36 +.equ RCxy_02, 3 +.equ RCxy_03, 41 +.equ RCxy_04, 18 +.equ RCxy_10, 1 +.equ RCxy_11, 44 +.equ RCxy_12, 10 +.equ RCxy_13, 45 +.equ RCxy_14, 2 +.equ RCxy_20, 62 +.equ RCxy_21, 6 +.equ RCxy_22, 43 +.equ RCxy_23, 15 +.equ RCxy_24, 61 +.equ RCxy_30, 28 +.equ RCxy_31, 55 +.equ RCxy_32, 25 +.equ RCxy_33, 21 +.equ RCxy_34, 56 +.equ RCxy_40, 27 +.equ RCxy_41, 20 +.equ RCxy_42, 39 +.equ RCxy_43, 8 +.equ RCxy_44, 14 +.equ RC0_l, 0x1 +.equ RC0_h, 0x0 +.equ RC1_l, 0x0 +.equ RC1_h, 0x89 +.equ RC2_l, 0x0 +.equ RC2_h, 0x8000008b +.equ RC3_l, 0x0 +.equ RC3_h, 0x80008080 +.equ RC4_l, 0x1 +.equ RC4_h, 0x8b +.equ RC5_l, 0x1 +.equ RC5_h, 0x8000 +.equ RC6_l, 0x1 +.equ RC6_h, 0x80008088 +.equ RC7_l, 0x1 +.equ RC7_h, 0x80000082 +.equ RC8_l, 0x0 +.equ RC8_h, 0xb +.equ RC9_l, 0x0 +.equ RC9_h, 0xa +.equ RC10_l, 0x1 +.equ RC10_h, 0x8082 +.equ RC11_l, 0x0 +.equ RC11_h, 0x8003 +.equ RC12_l, 0x1 +.equ RC12_h, 0x808b +.equ RC13_l, 0x1 +.equ RC13_h, 0x8000000b +.equ RC14_l, 0x1 +.equ RC14_h, 0x8000008a +.equ RC15_l, 0x1 +.equ RC15_h, 0x80000081 +.equ RC16_l, 0x0 +.equ RC16_h, 0x80000081 +.equ RC17_l, 0x0 +.equ RC17_h, 0x80000008 +.equ RC18_l, 0x0 +.equ RC18_h, 0x83 +.equ RC19_l, 0x0 +.equ RC19_h, 0x80008003 +.equ RC20_l, 0x1 +.equ RC20_h, 0x80008088 +.equ RC21_l, 0x0 +.equ RC21_h, 0x80000088 +.equ RC22_l, 0x1 +.equ RC22_h, 0x8000 +.equ RC23_l, 0x0 +.equ RC23_h, 0x80008082 + +qA00_h .req q0 +qA00_l .req q1 +qA20_l .req q2 + +.macro ld_xor5 state, round, x, C, A + vldrw.u32 q<\C>, [\state, #A__\x\()0] // @slothy:reads=A\state\()__\x\()0 + vldrw.u32 q<\A>, [\state, #A__\x\()1] // @slothy:reads=A\state\()__\x\()1 + veor q<\C>, q<\C>, q<\A> + vldrw.u32 q<\A>, [\state, #A__\x\()2] // @slothy:reads=A\state\()__\x\()2 + veor q<\C>, q<\C>, q<\A> + vldrw.u32 q<\A>, [\state, #A__\x\()3] // @slothy:reads=A\state\()__\x\()3 + veor q<\C>, q<\C>, q<\A> + vldrw.u32 q<\A>, [\state, #A__\x\()4] // @slothy:reads=A\state\()__\x\()4 + veor q<\C>, q<\C>, q<\A> + .endm + +.macro ld_xor5_0 state, round, x, C, A, A0 + vldrw.u32 q<\C>, [\state, #A__\x\()1] // @slothy:reads=A\state\()__\x\()1 + veor q<\C>, q<\C>, q<\A0> + vldrw.u32 q<\A>, [\state, #A__\x\()2] // @slothy:reads=A\state\()__\x\()2 + veor q<\C>, q<\C>, q<\A> + vldrw.u32 q<\A>, [\state, #A__\x\()3] // @slothy:reads=A\state\()__\x\()3 + veor q<\C>, q<\C>, q<\A> + vldrw.u32 q<\A>, [\state, #A__\x\()4] // @slothy:reads=A\state\()__\x\()4 + veor q<\C>, q<\C>, q<\A> + .endm + + +.macro rot1_xor_l D1_l, C0_l, C2_h + vshr.u32 q<\D1_l>, q<\C2_h>, #31 + vsli.32 q<\D1_l>, q<\C2_h>, #1 + veor q<\D1_l>, q<\D1_l>, q<\C0_l> + .endm + +.macro rot1_xor_h D1_h, C0_h, C2_l + veor q<\D1_h>, q<\C2_l>, q<\C0_h> + .endm + +.macro rot_str_e s_l, s_h, A_l, A_h, RC, x, y + vshr.u32 q, q, #32-(\RC/2) + vsli.u32 q, q, #\RC/2 + vstrw.32 q, [\s_l, #B__\x\()\y] + vshr.u32 q, q, #32-(\RC/2) + vsli.u32 q, q, #\RC/2 + vstrw.32 q, [\s_h, #B__\x\()\y] +.endm + +.macro rot_str_o s_l, s_h, A_l, A_h, RC, x, y + .if (\RC-1)/2 == 0 + vstrw.32 q, [\s_h, #B__\x\()\y] + .else + vshr.u32 q, q, #32-((\RC-1)/2) + vsli.u32 q, q, #(\RC-1)/2 + vstrw.32 q, [\s_h, #B__\x\()\y] + .endif + + .if (\RC+1)/2 == 0 + // should never happen + vstrw.32 q, [\s_l, #B__\x\()\y] + .else + vshr.u32 q, q, #32-((\RC+1)/2) + vsli.u32 q, q, #(\RC+1)/2 + vstrw.32 q, [\s_l, #B__\x\()\y] + .endif +.endm + +.macro ld_xorD_rot_str_e state_l, state_h, state_nl, state_nh, x, y, Dx_l, Dx_h + vldrw.u32 q, [\state_l, #A__\x\()\y] // @slothy:reads=A\state_l\()__\x\()\y + vldrw.u32 q, [\state_h, #A__\x\()\y] // @slothy:reads=A\state_h\()__\x\()\y + veor q, q, q<\Dx_l> + veor q, q, q<\Dx_h> + rot_str_e \state_nl, \state_nh, A_l, A_h, RCxy_\x\()\y, \x, \y +.endm + +.macro rot_str_e_0 s_l, s_h, A_l, A_h, RC, x, y, regl, regh + vshr.u32 q<\regl>, q, #32-(\RC/2) + vsli.u32 q<\regl>, q, #\RC/2 + // vstrw.32 q, [\s_l, #B__\x\()\y] + vshr.u32 q<\regh>, q, #32-(\RC/2) + vsli.u32 q<\regh>, q, #\RC/2 + // vstrw.32 q, [\s_h, #B__\x\()\y] +.endm + +.macro ld_xorD_rot_str_e_0 state_l, state_h, state_nl, state_nh, x, y, Dx_l, Dx_h, regl, regh + vldrw.u32 q, [\state_l, #A__\x\()\y] // @slothy:reads=A\state_l\()__\x\()\y + vldrw.u32 q, [\state_h, #A__\x\()\y] // @slothy:reads=A\state_h\()__\x\()\y + veor q, q, q<\Dx_l> + veor q, q, q<\Dx_h> + rot_str_e_0 \state_nl, \state_nh, A_l, A_h, RCxy_\x\()\y, \x, \y, \regl, \regh +.endm + +.macro ld_xorD_rot_str_o state_l, state_h, state_nl, state_nh, x, y, Dx_l, Dx_h + vldrw.u32 q, [\state_l, #A__\x\()\y] // @slothy:reads=A\state_l\()__\x\()\y + vldrw.u32 q, [\state_h, #A__\x\()\y] // @slothy:reads=A\state_h\()__\x\()\y + veor q, q, q<\Dx_l> + veor q, q, q<\Dx_h> + rot_str_o \state_nl, \state_nh, A_l, A_h, RCxy_\x\()\y, \x, \y +.endm + +.macro ld_bic_str state, round, y + vldrw.u32 q, [\state, #A__0\y] // @slothy:reads=A\state\()__0\y + vldrw.u32 q, [\state, #A__1\y] // @slothy:reads=A\state\()__1\y + vldrw.u32 q, [\state, #A__2\y] // @slothy:reads=A\state\()__2\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__0\y] // @slothy:writes=A\state\()__0\y + vldrw.u32 q, [\state, #A__3\y] // @slothy:reads=A\state\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__1\y] // @slothy:writes=A\state\()__1\y + vldrw.u32 q, [\state, #A__4\y] // @slothy:reads=A\state\()__4\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__2\y] // @slothy:writes=A\state\()__2\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__3\y] // @slothy:writes=A\state\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__4\y] // @slothy:writes=A\state\()__4\y +.endm + +.macro ld_bic_str_0 state, round, y, A0 + vldrw.u32 q, [\state, #A__1\y] // @slothy:reads=A\state\()__1\y + vldrw.u32 q, [\state, #A__2\y] // @slothy:reads=A\state\()__2\y + vldrw.u32 q, [\state, #A__3\y] // @slothy:reads=A\state\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__1\y] // @slothy:writes=A\state\()__1\y + vldrw.u32 q, [\state, #A__4\y] // @slothy:reads=A\state\()__4\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__2\y] // @slothy:writes=A\state\()__2\y + vldrw.u32 q, [\state, #A__0\y] // @slothy:reads=A\state\()__0\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__3\y] // @slothy:writes=A\state\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__4\y] // @slothy:writes=A\state\()__4\y + vbic q, q, q + veor q<\A0>, q, q + // A0 is stored later after the round-constant is added +.endm + +.macro ld_bic_str_1 state, round, y, A0, A2 + vldrw.u32 q, [\state, #A__1\y] // @slothy:reads=A\state\()__1\y + vldrw.u32 q, [\state, #A__2\y] // @slothy:reads=A\state\()__2\y + vldrw.u32 q, [\state, #A__3\y] // @slothy:reads=A\state\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__1\y] // @slothy:writes=A\state\()__1\y + vldrw.u32 q, [\state, #A__4\y] // @slothy:reads=A\state\()__4\y + vbic q, q, q + veor q<\A2>, q, q + vstrw.32 q<\A2>, [\state, #A__2\y] // @slothy:writes=A\state\()__2\y + vldrw.u32 q, [\state, #A__0\y] // @slothy:reads=A\state\()__0\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__3\y] // @slothy:writes=A\state\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__4\y] // @slothy:writes=A\state\()__4\y + vbic q, q, q + veor q<\A0>, q, q + // A0 is stored later after the round-constant is added +.endm + +.macro ld_1_bic_str state, round, y, B1 + vldrw.u32 q, [\state, #A__0\y] // @slothy:reads=A\state\()__0\y + // vldrw.u32 q, [\state, #A__1\y] // @slothy:reads=A\state\()__1\y + vldrw.u32 q, [\state, #A__2\y] // @slothy:reads=A\state\()__2\y + vbic q, q, q<\B1> + veor q, q, q + vstrw.32 q, [\state, #A__0\y] // @slothy:writes=A\state\()__0\y + vldrw.u32 q, [\state, #A__3\y] // @slothy:reads=A\state\()__3\y + vbic q, q, q + veor q, q<\B1>, q + vstrw.32 q, [\state, #A__1\y] // @slothy:writes=A\state\()__1\y + vldrw.u32 q, [\state, #A__4\y] // @slothy:reads=A\state\()__4\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__2\y] // @slothy:writes=A\state\()__2\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__3\y] // @slothy:writes=A\state\()__3\y + vbic q, q<\B1>, q + veor q, q, q + vstrw.32 q, [\state, #A__4\y] // @slothy:writes=A\state\()__4\y +.endm + +.macro ld_3_bic_str state, round, y, B3 + vldrw.u32 q, [\state, #A__0\y] // @slothy:reads=A\state\()__0\y + vldrw.u32 q, [\state, #A__1\y] // @slothy:reads=A\state\()__1\y + vldrw.u32 q, [\state, #A__2\y] // @slothy:reads=A\state\()__2\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__0\y] // @slothy:writes=A\state\()__0\y + // vldrw.u32 q, [\state, #A__3\y] // @slothy:reads=A\state\()__3\y + vbic q, q<\B3>, q + veor q, q, q + vstrw.32 q, [\state, #A__1\y] // @slothy:writes=A\state\()__1\y + vldrw.u32 q, [\state, #A__4\y] // @slothy:reads=A\state\()__4\y + vbic q, q, q<\B3> + veor q, q, q + vstrw.32 q, [\state, #A__2\y] // @slothy:writes=A\state\()__2\y + vbic q, q, q + veor q, q<\B3>, q + vstrw.32 q, [\state, #A__3\y] // @slothy:writes=A\state\()__3\y + vbic q, q, q + veor q, q, q + vstrw.32 q, [\state, #A__4\y] // @slothy:writes=A\state\()__4\y +.endm + + + +.macro keccak_4fold_round_theta_rho_pi state_l, state_h, state_nl, state_nh, rc + ld_xor5_0 \state_h, 0, 0, C0_h, A0_h, qA00_h + ld_xor5_0 \state_l, 0, 2, C2_l, A2_l, qA20_l + rot1_xor_h D1_h, C0_h, C2_l + vstrw.32 q, [r13, #QSTACK0] // @slothy:writes=stack0 + + ld_xor5_0 \state_l, 0, 0, C0_l, A0_l, qA00_l + ld_xor5 \state_h, 0, 2, C2_h, A2_h + rot1_xor_l D1_l, C0_l, C2_h + + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 1, 0, D1_l, D1_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 1, 1, D1_l, D1_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 1, 2, D1_l, D1_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 1, 3, D1_l, D1_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 1, 4, D1_l, D1_h + + ld_xor5 \state_h, 0, 4, C4_h, A4_h + rot1_xor_l D3_l, C2_l, C4_h + + ld_xor5 \state_l, 0, 4, C4_l, A4_l + rot1_xor_h D3_h, C2_h, C4_l + + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 3, 0, D3_l, D3_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 3, 1, D3_l, D3_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 3, 2, D3_l, D3_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 3, 3, D3_l, D3_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 3, 4, D3_l, D3_h + + ld_xor5 \state_h, 0, 1, C1_h, A1_h + rot1_xor_l D0_l, C4_l, C1_h + ld_xor5 \state_l, 0, 1, C1_l, A1_l + rot1_xor_h D0_h, C4_h, C1_l + + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 0, 0, D0_l, D0_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 0, 1, D0_l, D0_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 0, 2, D0_l, D0_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 0, 3, D0_l, D0_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 0, 4, D0_l, D0_h + + ld_xor5 \state_l, 0, 3, C3_l, A3_l + rot1_xor_h D2_h, C1_h, C3_l + ld_xor5 \state_h, 0, 3, C3_h, A3_h + rot1_xor_l D2_l, C1_l, C3_h + + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 2, 0, D2_l, D2_h + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 2, 1, D2_l, D2_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 2, 2, D2_l, D2_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 2, 3, D2_l, D2_h + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 2, 4, D2_l, D2_h + + rot1_xor_h D4_h, C3_h, C0_l + vldrw.32 q, [r13, #QSTACK0] // @slothy:reads=stack0 + rot1_xor_l D4_l, C3_l, C0_h + + + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 4, 0, D4_l, D4_h // B40 = A03 + ld_xorD_rot_str_o \state_l, \state_h, \state_nl, \state_nh, 4, 2, D4_l, D4_h // B42 = A24 + ld_xorD_rot_str_e \state_l, \state_h, \state_nl, \state_nh, 4, 4, D4_l, D4_h // B44 = A40 + // A11_l, A11_h, A32_l are held in registers from the next step + ld_xorD_rot_str_e_0 \state_l, \state_h, \state_nl, \state_nh, 4, 3, D4_l, D4_h, A32_l, A32_h // B43 = A32 + vstrw.32 q, [\state_nh, #B__43] + ld_xorD_rot_str_e_0 \state_l, \state_h, \state_nl, \state_nh, 4, 1, D4_l, D4_h, A11_l, A11_h // B41 = A11 +.endm + +.macro keccak_4fold_round_chi_iota state_l, state_h, state_nl, state_nh, rc // now BIC + // A11_l, A11_h, A32_l are held in registers from the previous step + ld_1_bic_str \state_nl, 0, 1, A11_l + ld_1_bic_str \state_nh, 0, 1, A11_h + + ld_3_bic_str \state_nl, 0, 2, A32_l + ld_bic_str \state_nh, 0, 2 + + ld_bic_str \state_nl, 0, 3 + ld_bic_str \state_nh, 0, 3 + + ld_bic_str \state_nl, 0, 4 + ld_bic_str \state_nh, 0, 4 + + ld_bic_str_1 \state_nl, 0, 0, A00_l, qA20_l + ld_bic_str_0 \state_nh, 0, 0, A00_h + + + ldrd r, r, [\rc] + vdup.32 q, r + veor qA00_l, q, q + vstrw.32 qA00_l, [\state_nl, #A__00] // @slothy:writes=A\state_nl\()__00 + vdup.32 q, r + veor qA00_h, q, q + vstrw.32 qA00_h, [\state_nh, #A__00] // @slothy:writes=A\state_nh\()__00 +.endm + +.text +RC_table: + .word RC0_l, RC0_h + .word RC1_l, RC1_h + .word RC2_l, RC2_h + .word RC3_l, RC3_h + .word RC4_l, RC4_h + .word RC5_l, RC5_h + .word RC6_l, RC6_h + .word RC7_l, RC7_h + .word RC8_l, RC8_h + .word RC9_l, RC9_h + .word RC10_l, RC10_h + .word RC11_l, RC11_h + .word RC12_l, RC12_h + .word RC13_l, RC13_h + .word RC14_l, RC14_h + .word RC15_l, RC15_h + .word RC16_l, RC16_h + .word RC17_l, RC17_h + .word RC18_l, RC18_h + .word RC19_l, RC19_h + .word RC20_l, RC20_h + .word RC21_l, RC21_h + .word RC22_l, RC22_h + .word RC23_l, RC23_h + +.align 8 +.type mve_keccak_state_permute_4fold_opt_m85, %function +.global mve_keccak_state_permute_4fold_opt_m85 +mve_keccak_state_permute_4fold_opt_m85: + + push {r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} + vpush {d8-d15} + sub sp, #8*16 + + adr r6, RC_table + + // r0: state 0 + // r1: state 1 + // r2: this state low + // r3: this state high + // r4: next state low + // r5: next state high + // r6: rc table + + + mov lr, #24 + + mov r2, r0 + mov r4, r1 + + // pre-fetch so we can keep in registers between rounds + add r3, r2, #400 + vldrw.u32 qA00_h, [r3, #A__00] + vldrw.u32 qA00_l, [r2, #A__00] + vldrw.u32 qA20_l, [r2, #A__20] + + wls lr, lr, roundend + roundstart: + // Instructions: 562 + // Expected cycles: 562 + // Expected IPC: 1.00 + // + // ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- cycle (expected) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------> + // 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 550 + // |------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|----------- + vldrw.U32 q7, [r2, #112] // *................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__21 + veor q7, q7, q2 // .*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q4, [r2, #80] // ..*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__01 + veor q4, q4, q1 // ...*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + add r11, r2, #400 // ....*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q6, [r11, #80] // .....*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar3__01 + veor q6, q6, q0 // ......*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r2, #192] // .......*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__22 + veor q7, q7, q1 // ........*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r2, #160] // .........*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar2__02 + veor q4, q4, q1 // ..........*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r11, #160] // ...........*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__02 + veor q6, q6, q1 // ............*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r2, #272] // .............*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__23 + veor q7, q7, q1 // ..............*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r2, #240] // ...............*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__03 + veor q1, q4, q1 // ................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q4, [r11, #240] // .................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar3__03 + veor q6, q6, q4 // ..................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q4, [r2, #352] // ...................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__24 + veor q4, q7, q4 // ....................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q7, [r2, #320] // .....................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar2__04 + veor q7, q1, q7 // ......................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r11, #320] // .......................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__04 + veor q6, q6, q1 // ........................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q6, [r13, #0] // .........................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ // @slothy:writes=stack0 + veor q6, q4, q6 // ..........................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r11, #16] // ...........................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__10 + veor q1, q1, q6 // ............................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q2, [r11, #32] // .............................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__20 + vshr.U32 q0, q1, #32-((1+1)/2) // ..............................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r11, #112] // ...............................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__21 + vsli.U32 q0, q1, #(1+1)/2 // ................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + veor q1, q2, q3 // .................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vstrw.32 q0, [r4, #160] // ..................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q2, [r11, #192] // ...................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__22 + veor q1, q1, q2 // ....................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q2, [r11, #272] // .....................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar3__23 + veor q1, q1, q2 // ......................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q2, [r11, #352] // .......................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__24 + veor q2, q1, q2 // ........................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r11, #96] // .........................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar3__11 + veor q0, q1, q6 // ..........................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q1, q2, #31 // ...........................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r2, #96] // ............................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__11 + vsli.32 q1, q2, #1 // .............................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + add r5, r4, #400 // ..............................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q5, q0, #32-(44/2) // ...............................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + veor q1, q1, q7 // ................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vsli.U32 q5, q0, #44/2 // .................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + veor q0, q3, q1 // ..................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q3, q0, #32-(44/2) // ...................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vstrw.32 q5, [r5, #16] // ....................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vsli.U32 q3, q0, #44/2 // .....................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q0, [r2, #16] // ......................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__10 + veor q5, q0, q1 // .......................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q5, [r5, #160] // ........................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q5, [r2, #336] // .........................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar2__14 + veor q5, q5, q1 // ..........................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q0, q5, #32-(2/2) // ...........................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q3, [r4, #16] // ............................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q0, q5, #2/2 // .............................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r2, #256] // ..............................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__13 + veor q5, q3, q1 // ...............................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vshr.U32 q3, q5, #32-((45-1)/2) // ................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vstrw.32 q0, [r4, #384] // .................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vsli.U32 q3, q5, #(45-1)/2 // ..................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q5, [r11, #176] // ...................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__12 + veor q5, q5, q6 // ....................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vshr.U32 q0, q5, #32-(10/2) // .....................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vstrw.32 q3, [r5, #128] // ......................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q0, q5, #10/2 // .......................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q5, [r2, #176] // ........................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__12 + vstrw.32 q0, [r5, #272] // .........................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + veor q0, q5, q1 // ..........................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q5, q0, #32-(10/2) // ...........................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r11, #256] // ............................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__13 + vsli.U32 q5, q0, #10/2 // .............................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q0, [r11, #336] // ..............................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__14 + vstrw.32 q5, [r4, #272] // ...............................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + veor q5, q3, q6 // ................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vshr.U32 q1, q5, #32-((45+1)/2) // .................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + veor q3, q0, q6 // ..................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q1, q5, #(45+1)/2 // ...................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q6, [r11, #64] // ....................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__40 + vstrw.32 q1, [r4, #128] // .....................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q1, [r11, #144] // ......................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__41 + veor q6, q6, q1 // .......................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r11, #224] // ........................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__42 + veor q6, q6, q1 // .........................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q1, [r11, #304] // ..........................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__43 + veor q6, q6, q1 // ...........................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r11, #384] // ............................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__44 + veor q1, q6, q1 // .............................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q6, q1, #31 // ..............................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q0, [r2, #64] // ...............................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__40 + vsli.32 q6, q1, #1 // ................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q5, [r2, #144] // .................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar2__41 + veor q6, q6, q4 // ..................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + veor q4, q0, q5 // ...................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q0, [r2, #224] // ....................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__42 + veor q4, q4, q0 // .....................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q0, [r2, #304] // ......................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__43 + veor q4, q4, q0 // .......................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q0, [r2, #384] // ........................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__44 + veor q4, q4, q0 // .........................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + veor q2, q4, q2 // ..........................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q0, q3, #32-(2/2) // ...........................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q5, [r2, #48] // ............................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__30 + vsli.U32 q0, q3, #2/2 // .............................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r11, #48] // ..............................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__30 + veor q5, q5, q6 // ...............................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vstrw.32 q0, [r5, #384] // ................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vshr.U32 q0, q5, #32-(28/2) // .................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + veor q3, q3, q2 // ..................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q0, q5, #28/2 // ...................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vstrw.32 q0, [r4, #80] // ....................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vshr.U32 q0, q3, #32-(28/2) // .....................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q5, [r11, #128] // ......................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__31 + vsli.U32 q0, q3, #28/2 // .......................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................... + veor q5, q5, q2 // ........................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q0, [r5, #80] // .........................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................ + vshr.U32 q3, q5, #32-((55+1)/2) // ..........................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q0, [r2, #208] // ...........................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__32 + vsli.U32 q3, q5, #(55+1)/2 // ............................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................... + veor q5, q0, q6 // .............................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q0, q5, #32-((25-1)/2) // ..............................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q3, [r4, #336] // ...............................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vsli.U32 q0, q5, #(25-1)/2 // ................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q3, [r2, #128] // .................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar2__31 + vstrw.32 q0, [r5, #192] // ..................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................... + veor q5, q3, q6 // ...................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................. + vshr.U32 q0, q5, #32-((55-1)/2) // ....................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q3, [r11, #208] // .....................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar3__32 + vsli.U32 q0, q5, #(55-1)/2 // ......................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................... + veor q3, q3, q2 // .......................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q0, [r5, #336] // ........................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q0, q3, #32-((25+1)/2) // .........................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q5, [r2, #368] // ..........................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__34 + vsli.U32 q0, q3, #(25+1)/2 // ...........................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r2, #288] // ............................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__33 + veor q3, q3, q6 // .............................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................... + veor q6, q5, q6 // ..............................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q5, q6, #32-(56/2) // ...............................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................. + vstrw.32 q0, [r4, #192] // ................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................. + vsli.U32 q5, q6, #56/2 // .................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q6, [r11, #368] // ..................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__34 + veor q6, q6, q2 // ...................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q0, [r11, #288] // ....................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__33 + veor q2, q0, q2 // .....................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................ + vshr.U32 q0, q3, #32-((21-1)/2) // ......................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q5, [r4, #304] // .......................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q0, q3, #(21-1)/2 // ........................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r11, #16] // .........................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar3__10 + vshr.U32 q5, q6, #32-(56/2) // ..........................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q0, [r5, #48] // ...........................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q5, q6, #56/2 // ............................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q6, [r11, #96] // .............................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__11 + vshr.U32 q0, q2, #32-((21+1)/2) // ..............................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................... + veor q6, q3, q6 // ...............................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................. + vsli.U32 q0, q2, #(21+1)/2 // ................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................. + vstrw.32 q5, [r5, #304] // .................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q2, [r11, #176] // ..................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__12 + veor q6, q6, q2 // ...................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q2, [r11, #256] // ....................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__13 + veor q5, q6, q2 // .....................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q2, [r11, #336] // ......................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__14 + veor q6, q5, q2 // .......................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q5, q6, #31 // ........................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q0, [r4, #48] // .........................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................ + vsli.32 q5, q6, #1 // ..........................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r2, #0] // ...........................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__00 + veor q4, q5, q4 // ............................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q5, [r2, #80] // .............................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__01 + veor q3, q3, q4 // ..............................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q2, q3, #32-(0/2) // ...............................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q0, [r2, #96] // ................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__11 + vsli.U32 q2, q3, #0/2 // .................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................ + veor q3, q5, q4 // ..................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q5, q3, #32-(36/2) // ...................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................. + vstrw.32 q2, [r4, #0] // ....................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................. + vsli.U32 q5, q3, #36/2 // .....................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q3, [r2, #176] // ......................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__12 + vstrw.32 q5, [r4, #256] // .......................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q5, [r2, #16] // ........................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__10 + veor q2, q5, q0 // .........................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q5, [r2, #256] // ..........................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__13 + veor q3, q2, q3 // ...........................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q2, [r2, #336] // ............................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__14 + veor q3, q3, q5 // .............................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q5, [r11, #0] // ..............................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__00 + veor q2, q3, q2 // ...............................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................. + veor q1, q2, q1 // ................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................. + veor q3, q5, q1 // .................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................ + vshr.U32 q0, q3, #32-(0/2) // ..................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q5, [r11, #80] // ...................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__01 + vsli.U32 q0, q3, #0/2 // ....................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................. + veor q3, q5, q1 // .....................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................ + vstrw.32 q0, [r5, #0] // ......................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q0, q3, #32-(36/2) // .......................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q5, [r2, #240] // ........................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__03 + vsli.U32 q0, q3, #36/2 // .........................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................ + veor q3, q5, q4 // ..........................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................... + vstrw.32 q0, [r5, #256] // ...........................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q0, q3, #32-((41-1)/2) // ............................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q5, [r2, #160] // .............................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__02 + vsli.U32 q0, q3, #(41-1)/2 // ..............................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................... + veor q3, q5, q4 // ...............................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................. + vshr.U32 q5, q3, #32-((3-1)/2) // ................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................. + vstrw.32 q0, [r5, #368] // .................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................ + vsli.U32 q5, q3, #(3-1)/2 // ..................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r11, #160] // ...................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__02 + veor q0, q3, q1 // ....................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................. + vshr.U32 q3, q0, #32-((3+1)/2) // .....................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................ + vstrw.32 q5, [r5, #112] // ......................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q3, q0, #(3+1)/2 // .......................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q0, [r2, #320] // ........................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__04 + vstrw.32 q3, [r4, #112] // .........................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q3, [r11, #240] // ..........................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__03 + veor q3, q3, q1 // ...........................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q5, q3, #32-((41+1)/2) // ............................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................... + veor q0, q0, q4 // .............................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................... + vsli.U32 q5, q3, #(41+1)/2 // ..............................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r11, #320] // ...............................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__04 + veor q3, q3, q1 // ................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................. + vstrw.32 q5, [r4, #368] // .................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................ + vshr.U32 q5, q3, #32-(18/2) // ..................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r2, #48] // ...................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__30 + vsli.U32 q5, q3, #18/2 // ....................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q3, [r2, #128] // .....................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar2__31 + veor q1, q1, q3 // ......................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r2, #208] // .......................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__32 + veor q1, q1, q3 // ........................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r2, #288] // .........................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar2__33 + veor q1, q1, q3 // ..........................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r2, #368] // ...........................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__34 + veor q4, q1, q3 // ............................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................... + vshr.U32 q3, q0, #32-(18/2) // .............................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q1, [r11, #48] // ..............................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__30 + vsli.U32 q3, q0, #18/2 // ...............................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q0, [r11, #128] // ................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__31 + veor q1, q1, q0 // .................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q0, [r11, #208] // ..................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__32 + veor q1, q1, q0 // ...................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q0, [r11, #288] // ....................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__33 + veor q1, q1, q0 // .....................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................ + vldrw.U32 q0, [r11, #368] // ......................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__34 + veor q1, q1, q0 // .......................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................... + vshr.U32 q0, q1, #31 // ........................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................... + veor q6, q4, q6 // .........................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................ + vsli.32 q0, q1, #1 // ..........................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................... + vstrw.32 q3, [r4, #224] // ...........................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................... + veor q2, q0, q2 // ............................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................... + vstrw.32 q5, [r5, #224] // .............................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................... + veor q1, q7, q1 // ..............................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................... + vldrw.U32 q7, [r2, #32] // ...............................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__20 + veor q7, q7, q2 // ................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................. + vldrw.U32 q0, [r11, #32] // .................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar3__20 + vshr.U32 q3, q7, #32-(62/2) // ..................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................... + veor q0, q0, q6 // ...................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................. + vsli.U32 q3, q7, #62/2 // ....................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................. + vldrw.U32 q7, [r11, #112] // .....................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar3__21 + vshr.U32 q5, q0, #32-(62/2) // ......................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................... + vstrw.32 q3, [r4, #320] // .......................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................... + vsli.U32 q5, q0, #62/2 // ........................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................... + veor q7, q7, q6 // .........................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................ + vstrw.32 q5, [r5, #320] // ..........................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................... + vshr.U32 q0, q7, #32-(6/2) // ...........................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................... + vldrw.U32 q3, [r2, #112] // ............................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__21 + vsli.U32 q0, q7, #6/2 // .............................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................... + veor q7, q3, q2 // ..............................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................... + vstrw.32 q0, [r5, #176] // ...............................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................. + vshr.U32 q0, q7, #32-(6/2) // ................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................. + vldrw.U32 q3, [r2, #192] // .................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................ // @slothy:reads=Ar2__22 + vsli.U32 q0, q7, #6/2 // ..................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................... + veor q7, q3, q2 // ...................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................. + vstrw.32 q0, [r4, #176] // ....................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................. + vshr.U32 q0, q7, #32-((43-1)/2) // .....................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................ + vldrw.U32 q5, [r11, #192] // ......................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__22 + vsli.U32 q0, q7, #(43-1)/2 // .......................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................... + veor q5, q5, q6 // ........................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................... + vshr.U32 q7, q5, #32-((43+1)/2) // .........................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................ + vstrw.32 q0, [r5, #32] // ..........................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................... + vsli.U32 q7, q5, #(43+1)/2 // ...........................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................... + vldrw.U32 q5, [r2, #272] // ............................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__23 + vstrw.32 q7, [r4, #32] // .............................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................... + veor q0, q5, q2 // ..............................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................... + vldrw.U32 q7, [r2, #352] // ...............................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................. // @slothy:reads=Ar2__24 + veor q5, q7, q2 // ................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................. + vshr.U32 q7, q0, #32-((15-1)/2) // .................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................ + vldrw.U32 q2, [r11, #352] // ..................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__24 + vsli.U32 q7, q0, #(15-1)/2 // ...................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................. + vldrw.U32 q0, [r11, #272] // ....................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................. // @slothy:reads=Ar3__23 + vshr.U32 q3, q5, #32-((61-1)/2) // .....................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................ + vstrw.32 q7, [r5, #288] // ......................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................... + vsli.U32 q3, q5, #(61-1)/2 // .......................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................... + veor q7, q2, q6 // ........................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................... + vshr.U32 q5, q7, #32-((61+1)/2) // .........................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................ + vldrw.32 q2, [r13, #0] // ..........................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................... // @slothy:reads=stack0 + vsli.U32 q5, q7, #(61+1)/2 // ...........................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................... + veor q7, q0, q6 // ............................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................... + vshr.U32 q0, q7, #32-((15+1)/2) // .............................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................... + vstrw.32 q5, [r4, #144] // ..............................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................... + vshr.U32 q5, q2, #31 // ...............................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................. + vstrw.32 q3, [r5, #144] // ................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................. + vsli.32 q5, q2, #1 // .................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................ + vldrw.U32 q6, [r2, #64] // ..................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__40 + veor q2, q5, q4 // ...................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................. + vsli.U32 q0, q7, #(15+1)/2 // ....................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................. + veor q7, q6, q2 // .....................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................ + vstrw.32 q0, [r4, #288] // ......................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................... + vshr.U32 q4, q7, #32-((27-1)/2) // .......................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................... + vldrw.U32 q6, [r11, #64] // ........................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................... // @slothy:reads=Ar3__40 + vsli.U32 q4, q7, #(27-1)/2 // .........................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................ + veor q7, q6, q1 // ..........................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................... + vstrw.32 q4, [r5, #240] // ...........................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................... + vshr.U32 q4, q7, #32-((27+1)/2) // ............................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................... + vldrw.U32 q6, [r2, #224] // .............................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................... // @slothy:reads=Ar2__42 + vsli.U32 q4, q7, #(27+1)/2 // ..............................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................... + veor q7, q6, q2 // ...............................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................. + vstrw.32 q4, [r4, #240] // ................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................. + vshr.U32 q4, q7, #32-((39-1)/2) // .................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................ + vldrw.U32 q6, [r11, #224] // ..................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................... // @slothy:reads=Ar3__42 + vsli.U32 q4, q7, #(39-1)/2 // ...................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................. + veor q7, q6, q1 // ....................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................. + vstrw.32 q4, [r5, #352] // .....................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................ + vshr.U32 q4, q7, #32-((39+1)/2) // ......................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................... + vldrw.U32 q6, [r2, #384] // .......................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................... // @slothy:reads=Ar2__44 + vsli.U32 q4, q7, #(39+1)/2 // ........................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................... + veor q7, q6, q2 // .........................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................ + vstrw.32 q4, [r4, #352] // ..........................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................... + vshr.U32 q4, q7, #32-(14/2) // ...........................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................... + vldrw.U32 q6, [r11, #384] // ............................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................... // @slothy:reads=Ar3__44 + vsli.U32 q4, q7, #14/2 // .............................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................... + veor q7, q6, q1 // ..............................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................... + vshr.U32 q6, q7, #32-(14/2) // ...............................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................. + vldrw.U32 q3, [r11, #144] // ................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................. // @slothy:reads=Ar3__41 + vsli.U32 q6, q7, #14/2 // .................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................ + veor q3, q3, q1 // ..................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................... + vstrw.32 q6, [r5, #64] // ...................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................. + vldrw.U32 q6, [r2, #304] // ....................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................. // @slothy:reads=Ar2__43 + veor q0, q6, q2 // .....................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................ + vshr.U32 q6, q3, #32-(20/2) // ......................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................... + vldrw.U32 q7, [r11, #304] // .......................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................... // @slothy:reads=Ar3__43 + veor q5, q7, q1 // ........................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................... + vldrw.U32 q1, [r2, #144] // .........................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................ // @slothy:reads=Ar2__41 + vsli.U32 q6, q3, #20/2 // ..........................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................... + veor q2, q1, q2 // ...........................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................... + vldrw.U32 q1, [r4, #80] // ............................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................... // @slothy:reads=Ar4__01 + vshr.U32 q7, q5, #32-(8/2) // .............................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................... + vstrw.32 q4, [r4, #64] // ..............................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................... + vsli.U32 q7, q5, #8/2 // ...............................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................. + vldrw.U32 q3, [r4, #144] // ................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................. // @slothy:reads=Ar4__41 + vshr.U32 q4, q2, #32-(20/2) // .................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................ + vstrw.32 q7, [r5, #208] // ..................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................... + vsli.U32 q4, q2, #20/2 // ...................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................. + vldrw.U32 q2, [r4, #112] // ....................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................. // @slothy:reads=Ar4__21 + vshr.U32 q7, q0, #32-(8/2) // .....................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................ + vbic q5, q2, q4 // ......................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................... + vsli.U32 q7, q0, #8/2 // .......................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................... + veor q0, q1, q5 // ........................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................... + vstrw.32 q0, [r4, #80] // .........................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................ // @slothy:writes=Ar4__01 + vldrw.U32 q0, [r4, #128] // ..........................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................... // @slothy:reads=Ar4__31 + vbic q5, q1, q3 // ...........................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................... + veor q5, q0, q5 // ............................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................... + vstrw.32 q5, [r4, #128] // .............................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................... // @slothy:writes=Ar4__31 + vbic q5, q0, q2 // ..............................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................... + vbic q0, q3, q0 // ...............................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................. + vbic q1, q4, q1 // ................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................. + veor q3, q3, q1 // .................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................ + vldrw.U32 q1, [r4, #160] // ..................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................... // @slothy:reads=Ar4__02 + veor q0, q2, q0 // ...................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................. + vldrw.U32 q2, [r5, #112] // ....................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................. // @slothy:reads=Ar5__21 + vstrw.32 q3, [r4, #144] // .....................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................ // @slothy:writes=Ar4__41 + vldrw.U32 q3, [r5, #128] // ......................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................... // @slothy:reads=Ar5__31 + vstrw.32 q0, [r4, #112] // .......................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................... // @slothy:writes=Ar4__21 + vldrw.U32 q0, [r5, #144] // ........................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................... // @slothy:reads=Ar5__41 + veor q5, q4, q5 // .........................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................ + vldrw.U32 q4, [r5, #80] // ..........................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................... // @slothy:reads=Ar5__01 + vstrw.32 q5, [r4, #96] // ...........................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................... // @slothy:writes=Ar4__11 + vbic q5, q6, q4 // ............................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................... + veor q5, q0, q5 // .............................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................... + vstrw.32 q5, [r5, #144] // ..............................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................... // @slothy:writes=Ar5__41 + vbic q5, q4, q0 // ...............................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................. + vbic q0, q0, q3 // ................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................. + veor q5, q3, q5 // .................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................ + vbic q3, q3, q2 // ..................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................... + veor q3, q6, q3 // ...................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................. + vstrw.32 q3, [r5, #96] // ....................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................. // @slothy:writes=Ar5__11 + vbic q3, q2, q6 // .....................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................ + veor q4, q4, q3 // ......................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................... + vstrw.32 q5, [r5, #128] // .......................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................... // @slothy:writes=Ar5__31 + veor q0, q2, q0 // ........................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................... + vstrw.32 q4, [r5, #80] // .........................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................ // @slothy:writes=Ar5__01 + vldrw.U32 q3, [r4, #192] // ..........................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................... // @slothy:reads=Ar4__22 + vbic q2, q7, q3 // ...........................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................... + vldrw.U32 q5, [r4, #224] // ............................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................... // @slothy:reads=Ar4__42 + vbic q4, q1, q5 // .............................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................... + vbic q6, q5, q7 // ..............................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................... + veor q7, q7, q4 // ...............................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................. + vstrw.32 q7, [r4, #208] // ................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................. // @slothy:writes=Ar4__32 + vldrw.U32 q4, [r4, #176] // .................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................ // @slothy:reads=Ar4__12 + vbic q7, q3, q4 // ..................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................... + veor q7, q1, q7 // ...................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................. + vstrw.32 q7, [r4, #160] // ....................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................. // @slothy:writes=Ar4__02 + vbic q7, q4, q1 // .....................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................ + vldrw.U32 q1, [r5, #176] // ......................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................... // @slothy:reads=Ar5__12 + veor q7, q5, q7 // .......................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................... + vstrw.32 q7, [r4, #224] // ........................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................... // @slothy:writes=Ar4__42 + veor q7, q3, q6 // .........................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................ + vstrw.32 q0, [r5, #112] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................... // @slothy:writes=Ar5__21 + veor q0, q4, q2 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................... + vstrw.32 q0, [r4, #176] // ............................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................... // @slothy:writes=Ar4__12 + vldrw.U32 q2, [r5, #192] // .............................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................... // @slothy:reads=Ar5__22 + vbic q4, q2, q1 // ..............................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................... + vldrw.U32 q0, [r5, #208] // ...............................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................. // @slothy:reads=Ar5__32 + vbic q6, q0, q2 // ................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................. + vstrw.32 q7, [r4, #192] // .................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................ // @slothy:writes=Ar4__22 + veor q7, q1, q6 // ..................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................... + vstrw.32 q7, [r5, #176] // ...................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................. // @slothy:writes=Ar5__12 + vldrw.U32 q6, [r5, #160] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................. // @slothy:reads=Ar5__02 + veor q7, q6, q4 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................ + vldrw.U32 q4, [r5, #224] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................... // @slothy:reads=Ar5__42 + vbic q3, q6, q4 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................... + vstrw.32 q7, [r5, #160] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................... // @slothy:writes=Ar5__02 + vbic q5, q1, q6 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................ + vldrw.U32 q6, [r4, #240] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................... // @slothy:reads=Ar4__03 + veor q3, q0, q3 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................... + vstrw.32 q3, [r5, #208] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................... // @slothy:writes=Ar5__32 + vbic q3, q4, q0 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................... + vldrw.U32 q1, [r4, #288] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................... // @slothy:reads=Ar4__33 + veor q3, q2, q3 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................. + vstrw.32 q3, [r5, #192] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................. // @slothy:writes=Ar5__22 + veor q3, q4, q5 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................ + vldrw.U32 q4, [r4, #272] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................... // @slothy:reads=Ar4__23 + vbic q2, q1, q4 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................. + vldrw.U32 q5, [r4, #256] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................. // @slothy:reads=Ar4__13 + vbic q7, q4, q5 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................ + veor q0, q5, q2 // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................... + vbic q2, q5, q6 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................... + vldrw.U32 q5, [r4, #304] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................... // @slothy:reads=Ar4__43 + veor q2, q5, q2 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................ + vstrw.32 q3, [r5, #224] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................... // @slothy:writes=Ar5__42 + veor q3, q6, q7 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................... + vstrw.32 q3, [r4, #240] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................... // @slothy:writes=Ar4__03 + vbic q6, q6, q5 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................... + vldrw.U32 q7, [r5, #304] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................... // @slothy:reads=Ar5__43 + veor q6, q1, q6 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................. + vstrw.32 q6, [r4, #288] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................. // @slothy:writes=Ar4__33 + vbic q1, q5, q1 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................ + veor q4, q4, q1 // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................... + vldrw.U32 q1, [r5, #272] // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................. // @slothy:reads=Ar5__23 + vstrw.32 q0, [r4, #256] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................. // @slothy:writes=Ar4__13 + vldrw.U32 q3, [r5, #240] // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................ // @slothy:reads=Ar5__03 + vstrw.32 q2, [r4, #304] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................... // @slothy:writes=Ar4__43 + vldrw.U32 q5, [r5, #256] // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................... // @slothy:reads=Ar5__13 + vbic q0, q1, q5 // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................... + vstrw.32 q4, [r4, #272] // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................ // @slothy:writes=Ar4__23 + veor q4, q3, q0 // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................... + vldrw.U32 q2, [r4, #352] // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................... // @slothy:reads=Ar4__24 + vbic q0, q3, q7 // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................... + vldrw.U32 q6, [r4, #320] // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................... // @slothy:reads=Ar4__04 + vbic q3, q5, q3 // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................... + veor q3, q7, q3 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................. + vstrw.32 q3, [r5, #304] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................. // @slothy:writes=Ar5__43 + vldrw.U32 q3, [r5, #288] // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................ // @slothy:reads=Ar5__33 + vbic q7, q7, q3 // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................... + veor q0, q3, q0 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................. + vstrw.32 q0, [r5, #288] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................. // @slothy:writes=Ar5__33 + veor q0, q1, q7 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................ + vstrw.32 q0, [r5, #272] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................... // @slothy:writes=Ar5__23 + vbic q3, q3, q1 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................... + veor q5, q5, q3 // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................... + vstrw.32 q4, [r5, #240] // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................ // @slothy:writes=Ar5__03 + vldrw.U32 q1, [r4, #336] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................... // @slothy:reads=Ar4__14 + vbic q3, q2, q1 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................... + vstrw.32 q5, [r5, #256] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................... // @slothy:writes=Ar5__13 + veor q7, q6, q3 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................... + vstrw.32 q7, [r4, #320] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................... // @slothy:writes=Ar4__04 + vbic q0, q1, q6 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................. + vldrw.U32 q5, [r4, #384] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................. // @slothy:reads=Ar4__44 + veor q4, q5, q0 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................ + vldrw.U32 q0, [r4, #368] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................... // @slothy:reads=Ar4__34 + vbic q7, q5, q0 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................. + vldrw.U32 q3, [r5, #384] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................. // @slothy:reads=Ar5__44 + veor q7, q2, q7 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................ + vstrw.32 q7, [r4, #352] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................... // @slothy:writes=Ar4__24 + vbic q7, q0, q2 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................... + vldrw.U32 q2, [r5, #320] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................... // @slothy:reads=Ar5__04 + vbic q5, q6, q5 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................ + vldrw.U32 q6, [r5, #352] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................... // @slothy:reads=Ar5__24 + veor q0, q0, q5 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................... + vstrw.32 q0, [r4, #368] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................... // @slothy:writes=Ar4__34 + veor q0, q1, q7 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................... + vldrw.U32 q1, [r5, #336] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................... // @slothy:reads=Ar5__14 + vstrw.32 q0, [r4, #336] // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................. // @slothy:writes=Ar4__14 + vbic q0, q6, q1 // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................. + veor q7, q2, q0 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................ + vldrw.U32 q0, [r5, #368] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................... // @slothy:reads=Ar5__34 + vbic q5, q3, q0 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................. + vstrw.32 q4, [r4, #384] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................. // @slothy:writes=Ar4__44 + veor q4, q6, q5 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................ + vstrw.32 q4, [r5, #352] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................... // @slothy:writes=Ar5__24 + vbic q6, q0, q6 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................... + vldrw.U32 q5, [r4, #16] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................... // @slothy:reads=Ar4__10 + vbic q4, q1, q2 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................ + vbic q2, q2, q3 // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................... + veor q6, q1, q6 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................... + veor q4, q3, q4 // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................... + veor q1, q0, q2 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................... + vstrw.32 q7, [r5, #320] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................... // @slothy:writes=Ar5__04 + vldrw.U32 q7, [r4, #48] // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................. // @slothy:reads=Ar4__30 + vstrw.32 q6, [r5, #336] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................. // @slothy:writes=Ar5__14 + vldrw.U32 q6, [r4, #64] // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................ // @slothy:reads=Ar4__40 + vstrw.32 q4, [r5, #384] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................... // @slothy:writes=Ar5__44 + vldrw.U32 q4, [r4, #32] // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................. // @slothy:reads=Ar4__20 + vbic q2, q7, q4 // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................. + veor q0, q5, q2 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................ + vldrw.U32 q3, [r4, #0] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................... // @slothy:reads=Ar4__00 + vbic q2, q5, q3 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................... + vbic q5, q4, q5 // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................... + vstrw.32 q1, [r5, #368] // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................ // @slothy:writes=Ar5__34 + vbic q1, q3, q6 // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................... + veor q1, q7, q1 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................... + vbic q7, q6, q7 // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................... + veor q6, q6, q2 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................... + veor q2, q4, q7 // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................... + vstrw.32 q0, [r4, #16] // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................. // @slothy:writes=Ar4__10 + veor q7, q3, q5 // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................. + vstrw.32 q1, [r4, #48] // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................ // @slothy:writes=Ar4__30 + vldrw.U32 q4, [r5, #16] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................... // @slothy:reads=Ar5__10 + vstrw.32 q6, [r4, #64] // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................. // @slothy:writes=Ar4__40 + ldrd r11, r0, [r6] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................. + vldrw.U32 q3, [r5, #48] // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................ // @slothy:reads=Ar5__30 + vdup.32 q1, r11 // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................... + veor q1, q7, q1 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................... + vldrw.U32 q7, [r5, #0] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................... // @slothy:reads=Ar5__00 + add r6, r6, #8 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................ + vldrw.U32 q6, [r5, #64] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................... // @slothy:reads=Ar5__40 + vbic q5, q6, q3 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................... + add r11, r2, #0 // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................... + vbic q0, q4, q7 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................... + veor q0, q6, q0 // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................... + vstrw.32 q0, [r5, #64] // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................. // @slothy:writes=Ar5__40 + vbic q0, q7, q6 // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................. + vldrw.U32 q6, [r5, #32] // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................ // @slothy:reads=Ar5__20 + veor q0, q3, q0 // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............... + vstrw.32 q0, [r5, #48] // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............. // @slothy:writes=Ar5__30 + vbic q0, q6, q4 // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............. + add r2, r4, #0 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............ + veor q0, q7, q0 // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........... + vdup.32 q7, r0 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......... + veor q0, q0, q7 // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......... + vstrw.32 q0, [r5, #0] // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........ // @slothy:writes=Ar5__00 + vbic q7, q3, q6 // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....... + vstrw.32 q2, [r4, #32] // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...... // @slothy:writes=Ar4__20 + veor q3, q6, q5 // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..... + vstrw.32 q3, [r5, #32] // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.... // @slothy:writes=Ar5__20 + veor q7, q4, q7 // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*... + vstrw.32 q1, [r4, #0] // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.. // @slothy:writes=Ar4__00 + add r4, r11, #0 // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*. + vstrw.32 q7, [r5, #16] // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................* // @slothy:writes=Ar5__10 + + // ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- cycle (expected) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------> + // 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 550 + // |------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|------------------------|----------- + // add r11, r2, #400 // ....*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q7, [r11, #80] // .....*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // veor q3, q7, q0 // ......*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // add r5, r4, #400 // ..............................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #160] // ...........*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q3, q5 // ............*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #240] // .................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // veor q3, q3, q5 // ..................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #320] // .......................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q0, q3, q5 // ........................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r2, #112] // *................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q3, q5, q2 // .*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q5, [r2, #192] // .......*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q3, q5 // ........*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r2, #272] // .............*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q3, q5 // ..............*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r2, #352] // ...................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q4, q3, q5 // ....................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q6, q4, q0 // ..........................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r2, #80] // ..*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q0, [r13, #0] // .........................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // veor q3, q5, q1 // ...*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q5, [r2, #160] // .........*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // veor q3, q3, q5 // ..........*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r2, #240] // ...............*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q3, q3, q5 // ................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q5, [r2, #320] // .....................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // veor q7, q3, q5 // ......................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q3, [r11, #32] // .............................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #112] // ...............................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q3, q3, q5 // .................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q5, [r11, #192] // ...................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q3, q3, q5 // ....................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q5, [r11, #272] // .....................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // veor q3, q3, q5 // ......................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #352] // .......................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q2, q3, q5 // ........................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q2, #31 // ...........................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.32 q5, q2, #1 // .............................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q1, q5, q7 // ................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q5, [r2, #16] // ......................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q3, [r11, #16] // ...........................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q5, q5, q1 // .......................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q3, q6 // ............................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r5, #160] // ........................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q3, #32-((1+1)/2) // ..............................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q5, q3, #(1+1)/2 // ................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vstrw.32 q5, [r4, #160] // ..................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q3, [r2, #96] // ............................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #96] // .........................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // veor q0, q3, q1 // ..................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q5, q6 // ..........................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q0, #32-(44/2) // ...................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vsli.U32 q5, q0, #44/2 // .....................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vstrw.32 q5, [r4, #16] // ............................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q3, #32-(44/2) // ...............................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vsli.U32 q5, q3, #44/2 // .................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vstrw.32 q5, [r5, #16] // ....................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q3, [r2, #176] // ........................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #176] // ...................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q0, q3, q1 // ..........................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q5, q6 // ....................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vshr.U32 q5, q0, #32-(10/2) // ...........................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q5, q0, #10/2 // .............................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r4, #272] // ...............................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vshr.U32 q5, q3, #32-(10/2) // .....................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vsli.U32 q5, q3, #10/2 // .......................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r5, #272] // .........................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q3, [r2, #256] // ..............................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #256] // ............................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q0, q3, q1 // ...............................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q3, q5, q6 // ................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vshr.U32 q5, q0, #32-((45-1)/2) // ................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vsli.U32 q5, q0, #(45-1)/2 // ..................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r5, #128] // ......................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q3, #32-((45+1)/2) // .................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vsli.U32 q5, q3, #(45+1)/2 // ...................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vstrw.32 q5, [r4, #128] // .....................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q3, [r2, #336] // .........................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q5, [r11, #336] // ..............................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q0, q3, q1 // ..........................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q5, q6 // ..................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q0, #32-(2/2) // ...........................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q5, q0, #2/2 // .............................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r4, #384] // .................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vshr.U32 q5, q3, #32-(2/2) // ...........................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q5, q3, #2/2 // .............................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r5, #384] // ................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q3, [r11, #64] // ....................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q5, [r11, #144] // ......................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q3, q5 // .......................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #224] // ........................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q3, q5 // .........................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q5, [r11, #304] // ..........................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q3, q5 // ...........................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #384] // ............................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q1, q3, q5 // .............................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q1, #31 // ..............................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.32 q5, q1, #1 // ................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q6, q5, q4 // ..................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q3, [r2, #64] // ...............................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q5, [r2, #144] // .................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // veor q3, q3, q5 // ...................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q5, [r2, #224] // ....................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q3, q3, q5 // .....................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q5, [r2, #304] // ......................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q3, q5 // .......................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r2, #384] // ........................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q3, q5 // .........................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // veor q2, q4, q2 // ..........................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q3, [r2, #48] // ............................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #48] // ..............................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q0, q3, q6 // ...............................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q3, q5, q2 // ..................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q0, #32-(28/2) // .................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vsli.U32 q5, q0, #28/2 // ...................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vstrw.32 q5, [r4, #80] // ....................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vshr.U32 q5, q3, #32-(28/2) // .....................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vsli.U32 q5, q3, #28/2 // .......................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r5, #80] // .........................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q3, [r2, #128] // .................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q5, [r11, #128] // ......................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q0, q3, q6 // ...................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q3, q5, q2 // ........................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q0, #32-((55-1)/2) // ....................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vsli.U32 q5, q0, #(55-1)/2 // ......................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r5, #336] // ........................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q3, #32-((55+1)/2) // ..........................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q5, q3, #(55+1)/2 // ............................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r4, #336] // ...............................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q3, [r2, #208] // ...........................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #208] // .....................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................ + // veor q0, q3, q6 // .............................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q5, q2 // .......................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q0, #32-((25-1)/2) // ..............................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q5, q0, #(25-1)/2 // ................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vstrw.32 q5, [r5, #192] // ..................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q3, #32-((25+1)/2) // .........................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vsli.U32 q5, q3, #(25+1)/2 // ...........................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r4, #192] // ................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q3, [r2, #288] // ............................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #288] // ....................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q0, q3, q6 // .............................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q5, q2 // .....................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................ + // vshr.U32 q5, q0, #32-((21-1)/2) // ......................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q5, q0, #(21-1)/2 // ........................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r5, #48] // ...........................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q3, #32-((21+1)/2) // ..............................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q5, q3, #(21+1)/2 // ................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................. + // vstrw.32 q5, [r4, #48] // .........................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q3, [r2, #368] // ..........................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #368] // ..................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q0, q3, q6 // ..............................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q5, q2 // ...................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................................. + // vshr.U32 q5, q0, #32-(56/2) // ...............................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................................. + // vsli.U32 q5, q0, #56/2 // .................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................................ + // vstrw.32 q5, [r4, #304] // .......................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q3, #32-(56/2) // ..........................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q5, q3, #56/2 // ............................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r5, #304] // .................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q3, [r11, #16] // .........................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q5, [r11, #96] // .............................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q3, q5 // ...............................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q5, [r11, #176] // ..................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q3, q5 // ...................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q5, [r11, #256] // ....................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q3, q3, q5 // .....................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q5, [r11, #336] // ......................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q6, q3, q5 // .......................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q6, #31 // ........................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................................... + // vsli.32 q5, q6, #1 // ..........................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q4, q5, q4 // ............................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q3, [r2, #16] // ........................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r2, #96] // ................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................. + // veor q3, q3, q5 // .........................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q5, [r2, #176] // ......................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q3, q5 // ...........................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r2, #256] // ..........................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q3, q5 // .............................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r2, #336] // ............................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................................... + // veor q2, q3, q5 // ...............................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................. + // veor q1, q2, q1 // ................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q3, [r2, #0] // ...........................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #0] // ..............................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................... + // veor q0, q3, q4 // ..............................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q5, q1 // .................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................ + // vshr.U32 q5, q0, #32-(0/2) // ...............................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................. + // vsli.U32 q5, q0, #0/2 // .................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................................................ + // vstrw.32 q5, [r4, #0] // ....................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................. + // vshr.U32 q5, q3, #32-(0/2) // ..................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q5, q3, #0/2 // ....................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................. + // vstrw.32 q5, [r5, #0] // ......................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q3, [r2, #80] // .............................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #80] // ...................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................. + // veor q0, q3, q4 // ..................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q5, q1 // .....................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................ + // vshr.U32 q5, q0, #32-(36/2) // ...................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................................................. + // vsli.U32 q5, q0, #36/2 // .....................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................................................ + // vstrw.32 q5, [r4, #256] // .......................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q3, #32-(36/2) // .......................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q5, q3, #36/2 // .........................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................................ + // vstrw.32 q5, [r5, #256] // ...........................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q3, [r2, #160] // .............................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #160] // ...................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................................. + // veor q0, q3, q4 // ...............................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................................. + // veor q3, q5, q1 // ....................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................. + // vshr.U32 q5, q0, #32-((3-1)/2) // ................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................. + // vsli.U32 q5, q0, #(3-1)/2 // ..................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r5, #112] // ......................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q3, #32-((3+1)/2) // .....................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................................ + // vsli.U32 q5, q3, #(3+1)/2 // .......................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r4, #112] // .........................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q3, [r2, #240] // ........................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #240] // ..........................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................... + // veor q0, q3, q4 // ..........................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q5, q1 // ...........................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q0, #32-((41-1)/2) // ............................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q5, q0, #(41-1)/2 // ..............................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r5, #368] // .................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................................ + // vshr.U32 q5, q3, #32-((41+1)/2) // ............................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q5, q3, #(41+1)/2 // ..............................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r4, #368] // .................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q3, [r2, #320] // ........................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #320] // ...............................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................. + // veor q0, q3, q4 // .............................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................................... + // veor q3, q5, q1 // ................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................................. + // vshr.U32 q5, q0, #32-(18/2) // .............................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q5, q0, #18/2 // ...............................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................................. + // vstrw.32 q5, [r4, #224] // ...........................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q3, #32-(18/2) // ..................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................... + // vsli.U32 q5, q3, #18/2 // ....................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................. + // vstrw.32 q5, [r5, #224] // .............................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q3, [r2, #48] // ...................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q5, [r2, #128] // .....................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................................ + // veor q3, q3, q5 // ......................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r2, #208] // .......................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................................... + // veor q3, q3, q5 // ........................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r2, #288] // .........................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................................ + // veor q3, q3, q5 // ..........................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r2, #368] // ...........................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................................................... + // veor q4, q3, q5 // ............................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................................... + // veor q6, q4, q6 // .........................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q3, [r11, #48] // ..............................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #128] // ................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................. + // veor q3, q3, q5 // .................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q5, [r11, #208] // ..................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................... + // veor q3, q3, q5 // ...................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q5, [r11, #288] // ....................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................. + // veor q3, q3, q5 // .....................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q5, [r11, #368] // ......................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................................... + // veor q1, q3, q5 // .......................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q1, #31 // ........................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................................... + // vsli.32 q5, q1, #1 // ..........................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................................... + // veor q2, q5, q2 // ............................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q3, [r2, #32] // ...............................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q5, [r11, #32] // .................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................ + // veor q0, q3, q2 // ................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................. + // veor q3, q5, q6 // ...................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................................. + // vshr.U32 q5, q0, #32-(62/2) // ..................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................... + // vsli.U32 q5, q0, #62/2 // ....................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................. + // vstrw.32 q5, [r4, #320] // .......................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q3, #32-(62/2) // ......................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................... + // vsli.U32 q5, q3, #62/2 // ........................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r5, #320] // ..........................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q3, [r2, #112] // ............................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #112] // .....................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................................ + // veor q0, q3, q2 // ..............................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................... + // veor q3, q5, q6 // .........................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................................ + // vshr.U32 q5, q0, #32-(6/2) // ................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................. + // vsli.U32 q5, q0, #6/2 // ..................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r4, #176] // ....................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................. + // vshr.U32 q5, q3, #32-(6/2) // ...........................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................................... + // vsli.U32 q5, q3, #6/2 // .............................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r5, #176] // ...............................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................................. + // vldrw.U32 q3, [r2, #192] // .................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................ + // vldrw.U32 q5, [r11, #192] // ......................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................... + // veor q0, q3, q2 // ...................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................................. + // veor q3, q5, q6 // ........................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q0, #32-((43-1)/2) // .....................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................................ + // vsli.U32 q5, q0, #(43-1)/2 // .......................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r5, #32] // ..........................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q3, #32-((43+1)/2) // .........................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................................ + // vsli.U32 q5, q3, #(43+1)/2 // ...........................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r4, #32] // .............................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................... + // vldrw.U32 q0, [r2, #272] // ............................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #272] // ....................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................. + // veor q0, q0, q2 // ..............................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................... + // veor q3, q5, q6 // ............................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q0, #32-((15-1)/2) // .................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................ + // vsli.U32 q5, q0, #(15-1)/2 // ...................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................................. + // vstrw.32 q5, [r5, #288] // ......................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q3, #32-((15+1)/2) // .............................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................... + // vsli.U32 q5, q3, #(15+1)/2 // ....................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................. + // vstrw.32 q5, [r4, #288] // ......................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................... + // vldrw.U32 q3, [r2, #352] // ...............................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................................. + // vldrw.U32 q5, [r11, #352] // ..................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................... + // veor q0, q3, q2 // ................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................. + // veor q3, q5, q6 // ........................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q0, #32-((61-1)/2) // .....................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................................ + // vsli.U32 q5, q0, #(61-1)/2 // .......................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r5, #144] // ................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................. + // vshr.U32 q5, q3, #32-((61+1)/2) // .........................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................................ + // vsli.U32 q5, q3, #(61+1)/2 // ...........................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r4, #144] // ..............................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................... + // veor q1, q7, q1 // ..............................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................................................................... + // vldrw.32 q3, [r13, #0] // ..........................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................................... + // vshr.U32 q5, q3, #31 // ...............................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................................. + // vsli.32 q5, q3, #1 // .................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................................ + // veor q2, q5, q4 // ...................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................................. + // vldrw.U32 q3, [r2, #64] // ..................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #64] // ........................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................................... + // veor q0, q3, q2 // .....................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................................ + // veor q3, q5, q1 // ..........................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................................... + // vshr.U32 q5, q0, #32-((27-1)/2) // .......................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................................... + // vsli.U32 q5, q0, #(27-1)/2 // .........................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................................ + // vstrw.32 q5, [r5, #240] // ...........................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................................... + // vshr.U32 q5, q3, #32-((27+1)/2) // ............................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................................... + // vsli.U32 q5, q3, #(27+1)/2 // ..............................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................... + // vstrw.32 q5, [r4, #240] // ................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................. + // vldrw.U32 q3, [r2, #224] // .............................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #224] // ..................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................... + // veor q0, q3, q2 // ...............................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................................. + // veor q3, q5, q1 // ....................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................. + // vshr.U32 q5, q0, #32-((39-1)/2) // .................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................................ + // vsli.U32 q5, q0, #(39-1)/2 // ...................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................................. + // vstrw.32 q5, [r5, #352] // .....................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................................ + // vshr.U32 q5, q3, #32-((39+1)/2) // ......................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................... + // vsli.U32 q5, q3, #(39+1)/2 // ........................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................................... + // vstrw.32 q5, [r4, #352] // ..........................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................................... + // vldrw.U32 q0, [r2, #384] // .......................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................................... + // vldrw.U32 q5, [r11, #384] // ............................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................................... + // veor q0, q0, q2 // .........................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................................ + // veor q3, q5, q1 // ..............................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................... + // vshr.U32 q5, q0, #32-(14/2) // ...........................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................................... + // vsli.U32 q5, q0, #14/2 // .............................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................... + // vstrw.32 q5, [r4, #64] // ..............................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................... + // vshr.U32 q5, q3, #32-(14/2) // ...............................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................................. + // vsli.U32 q5, q3, #14/2 // .................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................ + // vstrw.32 q5, [r5, #64] // ...................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................................. + // vldrw.U32 q5, [r2, #304] // ....................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................. + // vldrw.U32 q3, [r11, #304] // .......................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................................... + // veor q5, q5, q2 // .....................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................ + // veor q3, q3, q1 // ........................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................................... + // vshr.U32 q7, q5, #32-(8/2) // .....................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................ + // vsli.U32 q7, q5, #8/2 // .......................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................................... + // vshr.U32 q5, q3, #32-(8/2) // .............................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................... + // vsli.U32 q5, q3, #8/2 // ...............................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................................. + // vstrw.32 q5, [r5, #208] // ..................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................... + // vldrw.U32 q3, [r2, #144] // .........................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................ + // vldrw.U32 q5, [r11, #144] // ................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................................. + // veor q3, q3, q2 // ...........................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................................... + // veor q5, q5, q1 // ..................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................................... + // vshr.U32 q4, q3, #32-(20/2) // .................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................ + // vsli.U32 q4, q3, #20/2 // ...................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................................. + // vshr.U32 q6, q5, #32-(20/2) // ......................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................................... + // vsli.U32 q6, q5, #20/2 // ..........................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................................... + // vldrw.U32 q1, [r4, #80] // ............................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................................... + // vldrw.U32 q2, [r4, #112] // ....................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................................. + // vbic q5, q2, q4 // ......................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................... + // veor q5, q1, q5 // ........................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................................... + // vstrw.32 q5, [r4, #80] // .........................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................................ + // vldrw.U32 q0, [r4, #128] // ..........................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................................... + // vbic q5, q0, q2 // ..............................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................... + // veor q5, q4, q5 // .........................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................ + // vstrw.32 q5, [r4, #96] // ...........................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................... + // vldrw.U32 q3, [r4, #144] // ................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................................. + // vbic q5, q3, q0 // ...............................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................. + // veor q5, q2, q5 // ...................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................................. + // vstrw.32 q5, [r4, #112] // .......................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................................... + // vbic q5, q1, q3 // ...........................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................................................... + // veor q5, q0, q5 // ............................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................................... + // vstrw.32 q5, [r4, #128] // .............................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................................... + // vbic q5, q4, q1 // ................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................. + // veor q5, q3, q5 // .................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................................ + // vstrw.32 q5, [r4, #144] // .....................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................ + // vldrw.U32 q1, [r5, #80] // ..........................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................................... + // vldrw.U32 q2, [r5, #112] // ....................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................. + // vbic q5, q2, q6 // .....................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................ + // veor q5, q1, q5 // ......................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................... + // vstrw.32 q5, [r5, #80] // .........................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................ + // vldrw.U32 q0, [r5, #128] // ......................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................................................... + // vbic q5, q0, q2 // ..................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................... + // veor q5, q6, q5 // ...................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................................. + // vstrw.32 q5, [r5, #96] // ....................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................. + // vldrw.U32 q3, [r5, #144] // ........................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................................... + // vbic q5, q3, q0 // ................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................. + // veor q5, q2, q5 // ........................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................................... + // vstrw.32 q5, [r5, #112] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................... + // vbic q5, q1, q3 // ...............................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................. + // veor q5, q0, q5 // .................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................ + // vstrw.32 q5, [r5, #128] // .......................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................................... + // vbic q5, q6, q1 // ............................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................................... + // veor q5, q3, q5 // .............................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................................... + // vstrw.32 q5, [r5, #144] // ..............................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................................... + // vldrw.U32 q1, [r4, #160] // ..................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................................................... + // vldrw.U32 q2, [r4, #176] // .................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................ + // vldrw.U32 q0, [r4, #192] // ..........................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................................................... + // vbic q5, q0, q2 // ..................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................... + // veor q5, q1, q5 // ...................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................................. + // vstrw.32 q5, [r4, #160] // ....................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................. + // vbic q5, q7, q0 // ...........................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................................... + // veor q5, q2, q5 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................................... + // vstrw.32 q5, [r4, #176] // ............................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................... + // vldrw.U32 q3, [r4, #224] // ............................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................................................... + // vbic q5, q3, q7 // ..............................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................... + // veor q5, q0, q5 // .........................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................ + // vstrw.32 q5, [r4, #192] // .................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................ + // vbic q5, q1, q3 // .............................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................... + // veor q5, q7, q5 // ...............................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................................. + // vstrw.32 q5, [r4, #208] // ................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................................. + // vbic q5, q2, q1 // .....................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................................ + // veor q5, q3, q5 // .......................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................................... + // vstrw.32 q5, [r4, #224] // ........................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................................... + // vldrw.U32 q6, [r5, #160] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................. + // vldrw.U32 q1, [r5, #176] // ......................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................................... + // vldrw.U32 q2, [r5, #192] // .............................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................... + // vbic q5, q2, q1 // ..............................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................... + // veor q5, q6, q5 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................ + // vstrw.32 q5, [r5, #160] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................................... + // vldrw.U32 q0, [r5, #208] // ...............................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................................. + // vbic q5, q0, q2 // ................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................................. + // veor q5, q1, q5 // ..................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................................... + // vstrw.32 q5, [r5, #176] // ...................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................................. + // vldrw.U32 q3, [r5, #224] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................... + // vbic q5, q3, q0 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................... + // veor q5, q2, q5 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................................. + // vstrw.32 q5, [r5, #192] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................. + // vbic q5, q6, q3 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................................... + // veor q5, q0, q5 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................................... + // vstrw.32 q5, [r5, #208] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................................... + // vbic q5, q1, q6 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................................ + // veor q5, q3, q5 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................ + // vstrw.32 q5, [r5, #224] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................... + // vldrw.U32 q6, [r4, #240] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................................................... + // vldrw.U32 q1, [r4, #256] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................. + // vldrw.U32 q2, [r4, #272] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................... + // vbic q5, q2, q1 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................................ + // veor q5, q6, q5 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................................... + // vstrw.32 q5, [r4, #240] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................................... + // vldrw.U32 q3, [r4, #288] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................................... + // vbic q5, q3, q2 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................................. + // veor q5, q1, q5 // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................... + // vstrw.32 q5, [r4, #256] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................. + // vldrw.U32 q0, [r4, #304] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................................... + // vbic q5, q0, q3 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................ + // veor q5, q2, q5 // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................... + // vstrw.32 q5, [r4, #272] // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................ + // vbic q5, q6, q0 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................... + // veor q5, q3, q5 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................................. + // vstrw.32 q5, [r4, #288] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................. + // vbic q3, q1, q6 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................................... + // veor q3, q0, q3 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................................ + // vstrw.32 q3, [r4, #304] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................................... + // vldrw.U32 q6, [r5, #240] // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................................ + // vldrw.U32 q1, [r5, #256] // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................................... + // vldrw.U32 q2, [r5, #272] // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................................. + // vbic q5, q2, q1 // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................................... + // veor q5, q6, q5 // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................................... + // vstrw.32 q5, [r5, #240] // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................ + // vldrw.U32 q0, [r5, #288] // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................ + // vbic q5, q0, q2 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................................... + // veor q5, q1, q5 // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................................... + // vstrw.32 q5, [r5, #256] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................... + // vldrw.U32 q3, [r5, #304] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................................... + // vbic q5, q3, q0 // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................... + // veor q5, q2, q5 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................ + // vstrw.32 q5, [r5, #272] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................................... + // vbic q5, q6, q3 // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................................................... + // veor q5, q0, q5 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................................. + // vstrw.32 q5, [r5, #288] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................................. + // vbic q5, q1, q6 // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................... + // veor q5, q3, q5 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................. + // vstrw.32 q5, [r5, #304] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................................. + // vldrw.U32 q6, [r4, #320] // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................................... + // vldrw.U32 q1, [r4, #336] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................................... + // vldrw.U32 q2, [r4, #352] // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................................... + // vbic q5, q2, q1 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................................... + // veor q5, q6, q5 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................... + // vstrw.32 q5, [r4, #320] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................... + // vldrw.U32 q0, [r4, #368] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................... + // vbic q5, q0, q2 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................................... + // veor q5, q1, q5 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................... + // vstrw.32 q5, [r4, #336] // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................. + // vldrw.U32 q3, [r4, #384] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................. + // vbic q5, q3, q0 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................................. + // veor q5, q2, q5 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................ + // vstrw.32 q5, [r4, #352] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................... + // vbic q5, q6, q3 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................................ + // veor q5, q0, q5 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................................... + // vstrw.32 q5, [r4, #368] // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................................... + // vbic q5, q1, q6 // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................................................. + // veor q5, q3, q5 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................................ + // vstrw.32 q5, [r4, #384] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................. + // vldrw.U32 q6, [r5, #320] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................................... + // vldrw.U32 q1, [r5, #336] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................... + // vldrw.U32 q2, [r5, #352] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................................... + // vbic q5, q2, q1 // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................. + // veor q5, q6, q5 // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................................ + // vstrw.32 q5, [r5, #320] // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................... + // vldrw.U32 q0, [r5, #368] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................... + // vbic q5, q0, q2 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................................... + // veor q5, q1, q5 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................................... + // vstrw.32 q5, [r5, #336] // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................. + // vldrw.U32 q3, [r5, #384] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................................. + // vbic q5, q3, q0 // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................................. + // veor q5, q2, q5 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................................ + // vstrw.32 q5, [r5, #352] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................... + // vbic q5, q6, q3 // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................................... + // veor q5, q0, q5 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................... + // vstrw.32 q5, [r5, #368] // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................ + // vbic q5, q1, q6 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................................ + // veor q5, q3, q5 // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................................... + // vstrw.32 q5, [r5, #384] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................... + // vldrw.U32 q4, [r4, #16] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................................... + // vldrw.U32 q6, [r4, #32] // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................................. + // vldrw.U32 q1, [r4, #48] // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................................. + // vbic q5, q1, q6 // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................. + // veor q5, q4, q5 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................................ + // vstrw.32 q5, [r4, #16] // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................. + // vldrw.U32 q0, [r4, #64] // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................................ + // vbic q5, q0, q1 // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................................... + // veor q2, q6, q5 // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................... + // vstrw.32 q2, [r4, #32] // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...... + // vldrw.U32 q3, [r4, #0] // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................................... + // vbic q5, q3, q0 // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................................... + // veor q5, q1, q5 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................................... + // vstrw.32 q5, [r4, #48] // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................ + // vbic q5, q4, q3 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................................... + // veor q5, q0, q5 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................................... + // vstrw.32 q5, [r4, #64] // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............................. + // vbic q5, q6, q4 // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................................... + // veor q7, q3, q5 // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................................. + // vldrw.U32 q4, [r5, #16] // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................... + // vldrw.U32 q6, [r5, #32] // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................ + // vldrw.U32 q1, [r5, #48] // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................ + // vbic q5, q1, q6 // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....... + // veor q5, q4, q5 // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*... + // vstrw.32 q5, [r5, #16] // .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................* + // vldrw.U32 q0, [r5, #64] // ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*....................... + // vbic q5, q0, q1 // ...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*...................... + // veor q3, q6, q5 // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..... + // vstrw.32 q3, [r5, #32] // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.... + // vldrw.U32 q3, [r5, #0] // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......................... + // vbic q5, q3, q0 // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................. + // veor q5, q1, q5 // ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............... + // vstrw.32 q5, [r5, #48] // ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.............. + // vbic q5, q4, q3 // .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................... + // veor q5, q0, q5 // ..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*................... + // vstrw.32 q5, [r5, #64] // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.................. + // vbic q5, q6, q4 // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............. + // veor q3, q3, q5 // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........... + // ldrd r0, r11, [r6] // ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............................. + // vdup.32 q5, r0 // ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................... + // veor q1, q7, q5 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......................... + // vstrw.32 q1, [r4, #0] // ...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.. + // vdup.32 q5, r11 // .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*.......... + // veor q0, q3, q5 // ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*......... + // vstrw.32 q0, [r5, #0] // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........ + // add r6, r6, #8 // .........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*........................ + // add r11, r2, #0 // ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*..................... + // add r2, r4, #0 // .....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*............ + // add r4, r11, #0 // ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................*. + + roundend_pre: + + + le lr, roundstart +roundend: + add sp, #8*16 + + vpop {d8-d15} + ldmia.w sp!, {r3,r4,r5,r6,r7,r8,r9,r10,r11,r12, pc} \ No newline at end of file