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Merge pull request #116 from ryanneve/main
Disable Serial1 pins when sleeping
2 parents c5c2947 + 12dc722 commit ff69c89

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+9
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Firmware/OpenLog_Artemis/lowerPower.ino

+9-3
Original file line numberDiff line numberDiff line change
@@ -318,11 +318,16 @@ void goToSleep(uint32_t sysTicksToSleep)
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am_hal_gpio_pinconfig(PIN_QWIIC_SCL , g_AM_HAL_GPIO_DISABLE);
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//If requested, disable pins 48 and 49 (UART0) to stop them back-feeding the CH340
321-
if (settings.serialTxRxDuringSleep == false)
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{
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if (settings.serialTxRxDuringSleep == false)
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{
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am_hal_gpio_pinconfig(48 , g_AM_HAL_GPIO_DISABLE); //TX0
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am_hal_gpio_pinconfig(49 , g_AM_HAL_GPIO_DISABLE); //RX0
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}
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if (settings.useTxRxPinsForTerminal == true)
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{
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am_hal_gpio_pinconfig(12 , g_AM_HAL_GPIO_DISABLE); //TX1
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am_hal_gpio_pinconfig(13 , g_AM_HAL_GPIO_DISABLE); //RX1
329+
}
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}
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//Make sure PIN_POWER_LOSS is configured as an input for the WDT
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pinMode(PIN_POWER_LOSS, INPUT); // BD49K30G-TL has CMOS output and does not need a pull-up
@@ -470,6 +475,7 @@ void wakeFromSleep()
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pin_config(PinName(48), g_AM_BSP_GPIO_COM_UART_TX);
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pin_config(PinName(49), g_AM_BSP_GPIO_COM_UART_RX);
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}
478+
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//Re-enable CIPO, COPI, SCK and the chip selects but may as well leave ICM_INT disabled
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pin_config(PinName(PIN_SPI_CIPO), g_AM_BSP_GPIO_IOM0_MISO);

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