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ICM_20948_C.c
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#include "ICM_20948_C.h"
#include "ICM_20948_REGISTERS.h"
#include "AK09916_REGISTERS.h"
/*
* Icm20948 device require a DMP image to be loaded on init
* Provide such images by mean of a byte array
*/
#if defined(ICM_20948_USE_DMP) // Only include the 14301 Bytes of DMP if ICM_20948_USE_DMP is defined
#if defined(ARDUINO_ARCH_MBED) // ARDUINO_ARCH_MBED (APOLLO3 v2) does not support or require pgmspace.h / PROGMEM
const uint8_t dmp3_image[] = {
#elif (defined(__AVR__) || defined(__arm__) || defined(__ARDUINO_ARC__)) && !defined(__linux__) // Store the DMP firmware in PROGMEM on older AVR (ATmega) platforms
#define ICM_20948_USE_PROGMEM_FOR_DMP
#include <avr/pgmspace.h>
const uint8_t dmp3_image[] PROGMEM = {
#else
const uint8_t dmp3_image[] = {
#endif
#include "icm20948_img.dmp3a.h"
};
#endif
// ICM-20948 data is big-endian. We need to make it little-endian when writing into icm_20948_DMP_data_t
const int DMP_Quat9_Byte_Ordering[icm_20948_DMP_Quat9_Bytes] =
{
3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 13, 12 // Also used for Geomag
};
const int DMP_Quat6_Byte_Ordering[icm_20948_DMP_Quat6_Bytes] =
{
3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8 // Also used for Gyro_Calibr, Compass_Calibr
};
const int DMP_PQuat6_Byte_Ordering[icm_20948_DMP_PQuat6_Bytes] =
{
1, 0, 3, 2, 5, 4 // Also used for Raw_Accel, Compass
};
const int DMP_Raw_Gyro_Byte_Ordering[icm_20948_DMP_Raw_Gyro_Bytes + icm_20948_DMP_Gyro_Bias_Bytes] =
{
1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10};
const int DMP_Activity_Recognition_Byte_Ordering[icm_20948_DMP_Activity_Recognition_Bytes] =
{
0, 1, 5, 4, 3, 2};
const int DMP_Secondary_On_Off_Byte_Ordering[icm_20948_DMP_Secondary_On_Off_Bytes] =
{
1, 0};
const uint16_t inv_androidSensor_to_control_bits[ANDROID_SENSOR_NUM_MAX] =
{
// Data output control 1 register bit definition
// 16-bit accel 0x8000
// 16-bit gyro 0x4000
// 16-bit compass 0x2000
// 16-bit ALS 0x1000
// 32-bit 6-axis quaternion 0x0800
// 32-bit 9-axis quaternion + heading accuracy 0x0400
// 16-bit pedometer quaternion 0x0200
// 32-bit Geomag rv + heading accuracy 0x0100
// 16-bit Pressure 0x0080
// 32-bit calibrated gyro 0x0040
// 32-bit calibrated compass 0x0020
// Pedometer Step Detector 0x0010
// Header 2 0x0008
// Pedometer Step Indicator Bit 2 0x0004
// Pedometer Step Indicator Bit 1 0x0002
// Pedometer Step Indicator Bit 0 0x0001
// Unsupported Sensors are 0xFFFF
0xFFFF, // 0 Meta Data
0x8008, // 1 Accelerometer
0x0028, // 2 Magnetic Field
0x0408, // 3 Orientation
0x4048, // 4 Gyroscope
0x1008, // 5 Light
0x0088, // 6 Pressure
0xFFFF, // 7 Temperature
0xFFFF, // 8 Proximity <----------- fixme
0x0808, // 9 Gravity
0x8808, // 10 Linear Acceleration
0x0408, // 11 Rotation Vector
0xFFFF, // 12 Humidity
0xFFFF, // 13 Ambient Temperature
0x2008, // 14 Magnetic Field Uncalibrated
0x0808, // 15 Game Rotation Vector
0x4008, // 16 Gyroscope Uncalibrated
0x0000, // 17 Significant Motion
0x0018, // 18 Step Detector
0x0010, // 19 Step Counter <----------- fixme
0x0108, // 20 Geomagnetic Rotation Vector
0xFFFF, // 21 ANDROID_SENSOR_HEART_RATE,
0xFFFF, // 22 ANDROID_SENSOR_PROXIMITY,
0x8008, // 23 ANDROID_SENSOR_WAKEUP_ACCELEROMETER,
0x0028, // 24 ANDROID_SENSOR_WAKEUP_MAGNETIC_FIELD,
0x0408, // 25 ANDROID_SENSOR_WAKEUP_ORIENTATION,
0x4048, // 26 ANDROID_SENSOR_WAKEUP_GYROSCOPE,
0x1008, // 27 ANDROID_SENSOR_WAKEUP_LIGHT,
0x0088, // 28 ANDROID_SENSOR_WAKEUP_PRESSURE,
0x0808, // 29 ANDROID_SENSOR_WAKEUP_GRAVITY,
0x8808, // 30 ANDROID_SENSOR_WAKEUP_LINEAR_ACCELERATION,
0x0408, // 31 ANDROID_SENSOR_WAKEUP_ROTATION_VECTOR,
0xFFFF, // 32 ANDROID_SENSOR_WAKEUP_RELATIVE_HUMIDITY,
0xFFFF, // 33 ANDROID_SENSOR_WAKEUP_AMBIENT_TEMPERATURE,
0x2008, // 34 ANDROID_SENSOR_WAKEUP_MAGNETIC_FIELD_UNCALIBRATED,
0x0808, // 35 ANDROID_SENSOR_WAKEUP_GAME_ROTATION_VECTOR,
0x4008, // 36 ANDROID_SENSOR_WAKEUP_GYROSCOPE_UNCALIBRATED,
0x0018, // 37 ANDROID_SENSOR_WAKEUP_STEP_DETECTOR,
0x0010, // 38 ANDROID_SENSOR_WAKEUP_STEP_COUNTER,
0x0108, // 39 ANDROID_SENSOR_WAKEUP_GEOMAGNETIC_ROTATION_VECTOR
0xFFFF, // 40 ANDROID_SENSOR_WAKEUP_HEART_RATE,
0x0000, // 41 ANDROID_SENSOR_WAKEUP_TILT_DETECTOR,
0x8008, // 42 Raw Acc
0x4048, // 43 Raw Gyr
};
const ICM_20948_Serif_t NullSerif = {
NULL, // write
NULL, // read
NULL, // user
};
// Private function prototypes
// Function definitions
ICM_20948_Status_e ICM_20948_init_struct(ICM_20948_Device_t *pdev)
{
// Initialize all elements by 0 except for _last_bank
// Initialize _last_bank to 4 (invalid bank number)
// so ICM_20948_set_bank function does not skip issuing bank change operation
static const ICM_20948_Device_t init_device = { ._last_bank = 4 };
*pdev = init_device;
return ICM_20948_Stat_Ok;
}
ICM_20948_Status_e ICM_20948_link_serif(ICM_20948_Device_t *pdev, const ICM_20948_Serif_t *s)
{
if (s == NULL)
{
return ICM_20948_Stat_ParamErr;
}
if (pdev == NULL)
{
return ICM_20948_Stat_ParamErr;
}
pdev->_serif = s;
return ICM_20948_Stat_Ok;
}
ICM_20948_Status_e ICM_20948_execute_w(ICM_20948_Device_t *pdev, uint8_t regaddr, uint8_t *pdata, uint32_t len)
{
if (pdev->_serif->write == NULL)
{
return ICM_20948_Stat_NotImpl;
}
return (*pdev->_serif->write)(regaddr, pdata, len, pdev->_serif->user);
}
ICM_20948_Status_e ICM_20948_execute_r(ICM_20948_Device_t *pdev, uint8_t regaddr, uint8_t *pdata, uint32_t len)
{
if (pdev->_serif->read == NULL)
{
return ICM_20948_Stat_NotImpl;
}
return (*pdev->_serif->read)(regaddr, pdata, len, pdev->_serif->user);
}
//Transact directly with an I2C device, one byte at a time
//Used to configure a device before it is setup into a normal 0-3 peripheral slot
ICM_20948_Status_e ICM_20948_i2c_controller_periph4_txn(ICM_20948_Device_t *pdev, uint8_t addr, uint8_t reg, uint8_t *data, uint8_t len, bool Rw, bool send_reg_addr)
{
// Thanks MikeFair! // https://github.com/kriswiner/MPU9250/issues/86
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
addr = (((Rw) ? 0x80 : 0x00) | addr);
retval = ICM_20948_set_bank(pdev, 3);
retval = ICM_20948_execute_w(pdev, AGB3_REG_I2C_PERIPH4_ADDR, (uint8_t *)&addr, 1);
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
retval = ICM_20948_set_bank(pdev, 3);
retval = ICM_20948_execute_w(pdev, AGB3_REG_I2C_PERIPH4_REG, (uint8_t *)®, 1);
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
ICM_20948_I2C_PERIPH4_CTRL_t ctrl;
ctrl.EN = 1;
ctrl.INT_EN = false;
ctrl.DLY = 0;
ctrl.REG_DIS = !send_reg_addr;
ICM_20948_I2C_MST_STATUS_t i2c_mst_status;
bool txn_failed = false;
uint16_t nByte = 0;
while (nByte < len)
{
if (!Rw)
{
retval = ICM_20948_set_bank(pdev, 3);
retval = ICM_20948_execute_w(pdev, AGB3_REG_I2C_PERIPH4_DO, (uint8_t *)&(data[nByte]), 1);
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
}
// Kick off txn
retval = ICM_20948_set_bank(pdev, 3);
retval = ICM_20948_execute_w(pdev, AGB3_REG_I2C_PERIPH4_CTRL, (uint8_t *)&ctrl, sizeof(ICM_20948_I2C_PERIPH4_CTRL_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
// long tsTimeout = millis() + 3000; // Emergency timeout for txn (hard coded to 3 secs)
uint32_t max_cycles = 1000;
uint32_t count = 0;
bool peripheral4Done = false;
while (!peripheral4Done)
{
retval = ICM_20948_set_bank(pdev, 0);
retval = ICM_20948_execute_r(pdev, AGB0_REG_I2C_MST_STATUS, (uint8_t *)&i2c_mst_status, 1);
peripheral4Done = (i2c_mst_status.I2C_PERIPH4_DONE /*| (millis() > tsTimeout) */); //Avoid forever-loops
peripheral4Done |= (count >= max_cycles);
count++;
}
txn_failed = (i2c_mst_status.I2C_PERIPH4_NACK /*| (millis() > tsTimeout) */);
txn_failed |= (count >= max_cycles);
if (txn_failed)
break;
if (Rw)
{
retval = ICM_20948_set_bank(pdev, 3);
retval = ICM_20948_execute_r(pdev, AGB3_REG_I2C_PERIPH4_DI, &data[nByte], 1);
}
nByte++;
}
if (txn_failed)
{
//We often fail here if mag is stuck
return ICM_20948_Stat_Err;
}
return retval;
}
ICM_20948_Status_e ICM_20948_i2c_master_single_w(ICM_20948_Device_t *pdev, uint8_t addr, uint8_t reg, uint8_t *data)
{
return ICM_20948_i2c_controller_periph4_txn(pdev, addr, reg, data, 1, false, true);
}
ICM_20948_Status_e ICM_20948_i2c_master_single_r(ICM_20948_Device_t *pdev, uint8_t addr, uint8_t reg, uint8_t *data)
{
return ICM_20948_i2c_controller_periph4_txn(pdev, addr, reg, data, 1, true, true);
}
ICM_20948_Status_e ICM_20948_set_bank(ICM_20948_Device_t *pdev, uint8_t bank)
{
if (bank > 3)
{
return ICM_20948_Stat_ParamErr;
} // Only 4 possible banks
if (bank == pdev->_last_bank) // Do we need to change bank?
return ICM_20948_Stat_Ok; // Bail if we don't need to change bank to avoid unnecessary bus traffic
pdev->_last_bank = bank; // Store the requested bank (before we bit-shift)
bank = (bank << 4) & 0x30; // bits 5:4 of REG_BANK_SEL
return ICM_20948_execute_w(pdev, REG_BANK_SEL, &bank, 1);
}
ICM_20948_Status_e ICM_20948_sw_reset(ICM_20948_Device_t *pdev)
{
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
ICM_20948_PWR_MGMT_1_t reg;
ICM_20948_set_bank(pdev, 0); // Must be in the right bank
retval = ICM_20948_execute_r(pdev, AGB0_REG_PWR_MGMT_1, (uint8_t *)®, sizeof(ICM_20948_PWR_MGMT_1_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
reg.DEVICE_RESET = 1;
retval = ICM_20948_execute_w(pdev, AGB0_REG_PWR_MGMT_1, (uint8_t *)®, sizeof(ICM_20948_PWR_MGMT_1_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
return retval;
}
ICM_20948_Status_e ICM_20948_sleep(ICM_20948_Device_t *pdev, bool on)
{
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
ICM_20948_PWR_MGMT_1_t reg;
ICM_20948_set_bank(pdev, 0); // Must be in the right bank
retval = ICM_20948_execute_r(pdev, AGB0_REG_PWR_MGMT_1, (uint8_t *)®, sizeof(ICM_20948_PWR_MGMT_1_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
if (on)
{
reg.SLEEP = 1;
}
else
{
reg.SLEEP = 0;
}
retval = ICM_20948_execute_w(pdev, AGB0_REG_PWR_MGMT_1, (uint8_t *)®, sizeof(ICM_20948_PWR_MGMT_1_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
return retval;
}
ICM_20948_Status_e ICM_20948_low_power(ICM_20948_Device_t *pdev, bool on)
{
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
ICM_20948_PWR_MGMT_1_t reg;
ICM_20948_set_bank(pdev, 0); // Must be in the right bank
retval = ICM_20948_execute_r(pdev, AGB0_REG_PWR_MGMT_1, (uint8_t *)®, sizeof(ICM_20948_PWR_MGMT_1_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
if (on)
{
reg.LP_EN = 1;
}
else
{
reg.LP_EN = 0;
}
retval = ICM_20948_execute_w(pdev, AGB0_REG_PWR_MGMT_1, (uint8_t *)®, sizeof(ICM_20948_PWR_MGMT_1_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
return retval;
}
ICM_20948_Status_e ICM_20948_set_clock_source(ICM_20948_Device_t *pdev, ICM_20948_PWR_MGMT_1_CLKSEL_e source)
{
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
ICM_20948_PWR_MGMT_1_t reg;
ICM_20948_set_bank(pdev, 0); // Must be in the right bank
retval = ICM_20948_execute_r(pdev, AGB0_REG_PWR_MGMT_1, (uint8_t *)®, sizeof(ICM_20948_PWR_MGMT_1_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
reg.CLKSEL = source;
retval = ICM_20948_execute_w(pdev, AGB0_REG_PWR_MGMT_1, (uint8_t *)®, sizeof(ICM_20948_PWR_MGMT_1_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
return retval;
}
ICM_20948_Status_e ICM_20948_get_who_am_i(ICM_20948_Device_t *pdev, uint8_t *whoami)
{
if (whoami == NULL)
{
return ICM_20948_Stat_ParamErr;
}
ICM_20948_set_bank(pdev, 0); // Must be in the right bank
return ICM_20948_execute_r(pdev, AGB0_REG_WHO_AM_I, whoami, 1);
}
ICM_20948_Status_e ICM_20948_check_id(ICM_20948_Device_t *pdev)
{
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
uint8_t whoami = 0x00;
retval = ICM_20948_get_who_am_i(pdev, &whoami);
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
if (whoami != ICM_20948_WHOAMI)
{
return ICM_20948_Stat_WrongID;
}
return retval;
}
ICM_20948_Status_e ICM_20948_data_ready(ICM_20948_Device_t *pdev)
{
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
ICM_20948_INT_STATUS_1_t reg;
retval = ICM_20948_set_bank(pdev, 0); // Must be in the right bank
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
retval = ICM_20948_execute_r(pdev, AGB0_REG_INT_STATUS_1, (uint8_t *)®, sizeof(ICM_20948_INT_STATUS_1_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
if (!reg.RAW_DATA_0_RDY_INT)
{
retval = ICM_20948_Stat_NoData;
}
return retval;
}
// Interrupt Configuration
ICM_20948_Status_e ICM_20948_int_pin_cfg(ICM_20948_Device_t *pdev, ICM_20948_INT_PIN_CFG_t *write, ICM_20948_INT_PIN_CFG_t *read)
{
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
retval = ICM_20948_set_bank(pdev, 0); // Must be in the right bank
if (write != NULL)
{ // write first, if available
retval = ICM_20948_execute_w(pdev, AGB0_REG_INT_PIN_CONFIG, (uint8_t *)write, sizeof(ICM_20948_INT_PIN_CFG_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
}
if (read != NULL)
{ // then read, to allow for verification
retval = ICM_20948_execute_r(pdev, AGB0_REG_INT_PIN_CONFIG, (uint8_t *)read, sizeof(ICM_20948_INT_PIN_CFG_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
}
return retval;
}
ICM_20948_Status_e ICM_20948_int_enable(ICM_20948_Device_t *pdev, ICM_20948_INT_enable_t *write, ICM_20948_INT_enable_t *read)
{
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
ICM_20948_INT_ENABLE_t en_0;
ICM_20948_INT_ENABLE_1_t en_1;
ICM_20948_INT_ENABLE_2_t en_2;
ICM_20948_INT_ENABLE_3_t en_3;
retval = ICM_20948_set_bank(pdev, 0); // Must be in the right bank
if (write != NULL)
{ // If the write pointer is not NULL then write to the registers BEFORE reading
en_0.I2C_MST_INT_EN = write->I2C_MST_INT_EN;
en_0.DMP_INT1_EN = write->DMP_INT1_EN;
en_0.PLL_READY_EN = write->PLL_RDY_EN;
en_0.WOM_INT_EN = write->WOM_INT_EN;
en_0.reserved_0 = 0; // Clear RAM garbage
en_0.REG_WOF_EN = write->REG_WOF_EN;
en_1.RAW_DATA_0_RDY_EN = write->RAW_DATA_0_RDY_EN;
en_1.reserved_0 = 0; // Clear RAM garbage
en_2.individual.FIFO_OVERFLOW_EN_4 = write->FIFO_OVERFLOW_EN_4;
en_2.individual.FIFO_OVERFLOW_EN_3 = write->FIFO_OVERFLOW_EN_3;
en_2.individual.FIFO_OVERFLOW_EN_2 = write->FIFO_OVERFLOW_EN_2;
en_2.individual.FIFO_OVERFLOW_EN_1 = write->FIFO_OVERFLOW_EN_1;
en_2.individual.FIFO_OVERFLOW_EN_0 = write->FIFO_OVERFLOW_EN_0;
en_2.individual.reserved_0 = 0; // Clear RAM garbage
en_3.individual.FIFO_WM_EN_4 = write->FIFO_WM_EN_4;
en_3.individual.FIFO_WM_EN_3 = write->FIFO_WM_EN_3;
en_3.individual.FIFO_WM_EN_2 = write->FIFO_WM_EN_2;
en_3.individual.FIFO_WM_EN_1 = write->FIFO_WM_EN_1;
en_3.individual.FIFO_WM_EN_0 = write->FIFO_WM_EN_0;
en_3.individual.reserved_0 = 0; // Clear RAM garbage
retval = ICM_20948_execute_w(pdev, AGB0_REG_INT_ENABLE, (uint8_t *)&en_0, sizeof(ICM_20948_INT_ENABLE_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
retval = ICM_20948_execute_w(pdev, AGB0_REG_INT_ENABLE_1, (uint8_t *)&en_1, sizeof(ICM_20948_INT_ENABLE_1_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
retval = ICM_20948_execute_w(pdev, AGB0_REG_INT_ENABLE_2, (uint8_t *)&en_2, sizeof(ICM_20948_INT_ENABLE_2_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
retval = ICM_20948_execute_w(pdev, AGB0_REG_INT_ENABLE_3, (uint8_t *)&en_3, sizeof(ICM_20948_INT_ENABLE_3_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
}
if (read != NULL)
{ // If read pointer is not NULL then read the registers (if write is not NULL then this should read back the results of write into read)
retval = ICM_20948_execute_r(pdev, AGB0_REG_INT_ENABLE, (uint8_t *)&en_0, sizeof(ICM_20948_INT_ENABLE_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
retval = ICM_20948_execute_r(pdev, AGB0_REG_INT_ENABLE_1, (uint8_t *)&en_1, sizeof(ICM_20948_INT_ENABLE_1_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
retval = ICM_20948_execute_r(pdev, AGB0_REG_INT_ENABLE_2, (uint8_t *)&en_2, sizeof(ICM_20948_INT_ENABLE_2_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
retval = ICM_20948_execute_r(pdev, AGB0_REG_INT_ENABLE_3, (uint8_t *)&en_3, sizeof(ICM_20948_INT_ENABLE_3_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
read->I2C_MST_INT_EN = en_0.I2C_MST_INT_EN;
read->DMP_INT1_EN = en_0.DMP_INT1_EN;
read->PLL_RDY_EN = en_0.PLL_READY_EN;
read->WOM_INT_EN = en_0.WOM_INT_EN;
read->REG_WOF_EN = en_0.REG_WOF_EN;
read->RAW_DATA_0_RDY_EN = en_1.RAW_DATA_0_RDY_EN;
read->FIFO_OVERFLOW_EN_4 = en_2.individual.FIFO_OVERFLOW_EN_4;
read->FIFO_OVERFLOW_EN_3 = en_2.individual.FIFO_OVERFLOW_EN_3;
read->FIFO_OVERFLOW_EN_2 = en_2.individual.FIFO_OVERFLOW_EN_2;
read->FIFO_OVERFLOW_EN_1 = en_2.individual.FIFO_OVERFLOW_EN_1;
read->FIFO_OVERFLOW_EN_0 = en_2.individual.FIFO_OVERFLOW_EN_0;
read->FIFO_WM_EN_4 = en_3.individual.FIFO_WM_EN_4;
read->FIFO_WM_EN_3 = en_3.individual.FIFO_WM_EN_3;
read->FIFO_WM_EN_2 = en_3.individual.FIFO_WM_EN_2;
read->FIFO_WM_EN_1 = en_3.individual.FIFO_WM_EN_1;
read->FIFO_WM_EN_0 = en_3.individual.FIFO_WM_EN_0;
}
return retval;
}
ICM_20948_Status_e ICM_20948_wom_threshold(ICM_20948_Device_t *pdev, ICM_20948_ACCEL_WOM_THR_t *write, ICM_20948_ACCEL_WOM_THR_t *read)
{
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
ICM_20948_ACCEL_WOM_THR_t thr;
retval = ICM_20948_set_bank(pdev, 2); // Must be in the right bank
if (write != NULL)
{ // If the write pointer is not NULL then write to the registers BEFORE reading
thr.WOM_THRESHOLD = write->WOM_THRESHOLD;
retval = ICM_20948_execute_w(pdev, AGB2_REG_ACCEL_WOM_THR, (uint8_t *)&thr, sizeof(ICM_20948_ACCEL_WOM_THR_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
}
if (read != NULL)
{ // If read pointer is not NULL then read the registers (if write is not NULL then this should read back the results of write into read)
retval = ICM_20948_execute_r(pdev, AGB2_REG_ACCEL_WOM_THR, (uint8_t *)&thr, sizeof(ICM_20948_ACCEL_WOM_THR_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
read->WOM_THRESHOLD = thr.WOM_THRESHOLD;
}
return retval;
}
ICM_20948_Status_e ICM_20948_set_sample_mode(ICM_20948_Device_t *pdev, ICM_20948_InternalSensorID_bm sensors, ICM_20948_LP_CONFIG_CYCLE_e mode)
{
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
ICM_20948_LP_CONFIG_t reg;
if (!(sensors & (ICM_20948_Internal_Acc | ICM_20948_Internal_Gyr | ICM_20948_Internal_Mst)))
{
return ICM_20948_Stat_SensorNotSupported;
}
retval = ICM_20948_set_bank(pdev, 0); // Must be in the right bank
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
retval = ICM_20948_execute_r(pdev, AGB0_REG_LP_CONFIG, (uint8_t *)®, sizeof(ICM_20948_LP_CONFIG_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
if (sensors & ICM_20948_Internal_Acc)
{
reg.ACCEL_CYCLE = mode;
} // Set all desired sensors to this setting
if (sensors & ICM_20948_Internal_Gyr)
{
reg.GYRO_CYCLE = mode;
}
if (sensors & ICM_20948_Internal_Mst)
{
reg.I2C_MST_CYCLE = mode;
}
retval = ICM_20948_execute_w(pdev, AGB0_REG_LP_CONFIG, (uint8_t *)®, sizeof(ICM_20948_LP_CONFIG_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
return retval;
}
ICM_20948_Status_e ICM_20948_set_full_scale(ICM_20948_Device_t *pdev, ICM_20948_InternalSensorID_bm sensors, ICM_20948_fss_t fss)
{
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
if (!(sensors & (ICM_20948_Internal_Acc | ICM_20948_Internal_Gyr)))
{
return ICM_20948_Stat_SensorNotSupported;
}
if (sensors & ICM_20948_Internal_Acc)
{
ICM_20948_ACCEL_CONFIG_t reg;
retval |= ICM_20948_set_bank(pdev, 2); // Must be in the right bank
retval |= ICM_20948_execute_r(pdev, AGB2_REG_ACCEL_CONFIG, (uint8_t *)®, sizeof(ICM_20948_ACCEL_CONFIG_t));
reg.ACCEL_FS_SEL = fss.a;
retval |= ICM_20948_execute_w(pdev, AGB2_REG_ACCEL_CONFIG, (uint8_t *)®, sizeof(ICM_20948_ACCEL_CONFIG_t));
}
if (sensors & ICM_20948_Internal_Gyr)
{
ICM_20948_GYRO_CONFIG_1_t reg;
retval |= ICM_20948_set_bank(pdev, 2); // Must be in the right bank
retval |= ICM_20948_execute_r(pdev, AGB2_REG_GYRO_CONFIG_1, (uint8_t *)®, sizeof(ICM_20948_GYRO_CONFIG_1_t));
reg.GYRO_FS_SEL = fss.g;
retval |= ICM_20948_execute_w(pdev, AGB2_REG_GYRO_CONFIG_1, (uint8_t *)®, sizeof(ICM_20948_GYRO_CONFIG_1_t));
}
return retval;
}
ICM_20948_Status_e ICM_20948_set_dlpf_cfg(ICM_20948_Device_t *pdev, ICM_20948_InternalSensorID_bm sensors, ICM_20948_dlpcfg_t cfg)
{
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
if (!(sensors & (ICM_20948_Internal_Acc | ICM_20948_Internal_Gyr)))
{
return ICM_20948_Stat_SensorNotSupported;
}
if (sensors & ICM_20948_Internal_Acc)
{
ICM_20948_ACCEL_CONFIG_t reg;
retval |= ICM_20948_set_bank(pdev, 2); // Must be in the right bank
retval |= ICM_20948_execute_r(pdev, AGB2_REG_ACCEL_CONFIG, (uint8_t *)®, sizeof(ICM_20948_ACCEL_CONFIG_t));
reg.ACCEL_DLPFCFG = cfg.a;
retval |= ICM_20948_execute_w(pdev, AGB2_REG_ACCEL_CONFIG, (uint8_t *)®, sizeof(ICM_20948_ACCEL_CONFIG_t));
}
if (sensors & ICM_20948_Internal_Gyr)
{
ICM_20948_GYRO_CONFIG_1_t reg;
retval |= ICM_20948_set_bank(pdev, 2); // Must be in the right bank
retval |= ICM_20948_execute_r(pdev, AGB2_REG_GYRO_CONFIG_1, (uint8_t *)®, sizeof(ICM_20948_GYRO_CONFIG_1_t));
reg.GYRO_DLPFCFG = cfg.g;
retval |= ICM_20948_execute_w(pdev, AGB2_REG_GYRO_CONFIG_1, (uint8_t *)®, sizeof(ICM_20948_GYRO_CONFIG_1_t));
}
return retval;
}
ICM_20948_Status_e ICM_20948_enable_dlpf(ICM_20948_Device_t *pdev, ICM_20948_InternalSensorID_bm sensors, bool enable)
{
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
if (!(sensors & (ICM_20948_Internal_Acc | ICM_20948_Internal_Gyr)))
{
return ICM_20948_Stat_SensorNotSupported;
}
if (sensors & ICM_20948_Internal_Acc)
{
ICM_20948_ACCEL_CONFIG_t reg;
retval |= ICM_20948_set_bank(pdev, 2); // Must be in the right bank
retval |= ICM_20948_execute_r(pdev, AGB2_REG_ACCEL_CONFIG, (uint8_t *)®, sizeof(ICM_20948_ACCEL_CONFIG_t));
if (enable)
{
reg.ACCEL_FCHOICE = 1;
}
else
{
reg.ACCEL_FCHOICE = 0;
}
retval |= ICM_20948_execute_w(pdev, AGB2_REG_ACCEL_CONFIG, (uint8_t *)®, sizeof(ICM_20948_ACCEL_CONFIG_t));
}
if (sensors & ICM_20948_Internal_Gyr)
{
ICM_20948_GYRO_CONFIG_1_t reg;
retval |= ICM_20948_set_bank(pdev, 2); // Must be in the right bank
retval |= ICM_20948_execute_r(pdev, AGB2_REG_GYRO_CONFIG_1, (uint8_t *)®, sizeof(ICM_20948_GYRO_CONFIG_1_t));
if (enable)
{
reg.GYRO_FCHOICE = 1;
}
else
{
reg.GYRO_FCHOICE = 0;
}
retval |= ICM_20948_execute_w(pdev, AGB2_REG_GYRO_CONFIG_1, (uint8_t *)®, sizeof(ICM_20948_GYRO_CONFIG_1_t));
}
return retval;
}
ICM_20948_Status_e ICM_20948_set_sample_rate(ICM_20948_Device_t *pdev, ICM_20948_InternalSensorID_bm sensors, ICM_20948_smplrt_t smplrt)
{
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
if (!(sensors & (ICM_20948_Internal_Acc | ICM_20948_Internal_Gyr)))
{
return ICM_20948_Stat_SensorNotSupported;
}
if (sensors & ICM_20948_Internal_Acc)
{
retval |= ICM_20948_set_bank(pdev, 2); // Must be in the right bank
uint8_t div1 = (smplrt.a << 8);
uint8_t div2 = (smplrt.a & 0xFF);
retval |= ICM_20948_execute_w(pdev, AGB2_REG_ACCEL_SMPLRT_DIV_1, &div1, 1);
retval |= ICM_20948_execute_w(pdev, AGB2_REG_ACCEL_SMPLRT_DIV_2, &div2, 1);
}
if (sensors & ICM_20948_Internal_Gyr)
{
retval |= ICM_20948_set_bank(pdev, 2); // Must be in the right bank
uint8_t div = (smplrt.g);
retval |= ICM_20948_execute_w(pdev, AGB2_REG_GYRO_SMPLRT_DIV, &div, 1);
}
return retval;
}
// Interface Things
ICM_20948_Status_e ICM_20948_i2c_master_passthrough(ICM_20948_Device_t *pdev, bool passthrough)
{
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
ICM_20948_INT_PIN_CFG_t reg;
retval = ICM_20948_set_bank(pdev, 0);
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
retval = ICM_20948_execute_r(pdev, AGB0_REG_INT_PIN_CONFIG, (uint8_t *)®, sizeof(ICM_20948_INT_PIN_CFG_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
reg.BYPASS_EN = passthrough;
retval = ICM_20948_execute_w(pdev, AGB0_REG_INT_PIN_CONFIG, (uint8_t *)®, sizeof(ICM_20948_INT_PIN_CFG_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
return retval;
}
ICM_20948_Status_e ICM_20948_i2c_master_enable(ICM_20948_Device_t *pdev, bool enable)
{
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
// Disable BYPASS_EN
retval = ICM_20948_i2c_master_passthrough(pdev, false);
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
ICM_20948_I2C_MST_CTRL_t ctrl;
retval = ICM_20948_set_bank(pdev, 3);
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
retval = ICM_20948_execute_r(pdev, AGB3_REG_I2C_MST_CTRL, (uint8_t *)&ctrl, sizeof(ICM_20948_I2C_MST_CTRL_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
ctrl.I2C_MST_CLK = 0x07; // corresponds to 345.6 kHz, good for up to 400 kHz
ctrl.I2C_MST_P_NSR = 1;
retval = ICM_20948_execute_w(pdev, AGB3_REG_I2C_MST_CTRL, (uint8_t *)&ctrl, sizeof(ICM_20948_I2C_MST_CTRL_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
ICM_20948_USER_CTRL_t reg;
retval = ICM_20948_set_bank(pdev, 0);
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
retval = ICM_20948_execute_r(pdev, AGB0_REG_USER_CTRL, (uint8_t *)®, sizeof(ICM_20948_USER_CTRL_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
if (enable)
{
reg.I2C_MST_EN = 1;
}
else
{
reg.I2C_MST_EN = 0;
}
retval = ICM_20948_execute_w(pdev, AGB0_REG_USER_CTRL, (uint8_t *)®, sizeof(ICM_20948_USER_CTRL_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
return retval;
}
ICM_20948_Status_e ICM_20948_i2c_master_reset(ICM_20948_Device_t *pdev)
{
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
ICM_20948_USER_CTRL_t ctrl;
retval = ICM_20948_set_bank(pdev, 0);
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
retval = ICM_20948_execute_r(pdev, AGB0_REG_USER_CTRL, (uint8_t *)&ctrl, sizeof(ICM_20948_USER_CTRL_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
ctrl.I2C_MST_RST = 1; //Reset!
retval = ICM_20948_execute_w(pdev, AGB0_REG_USER_CTRL, (uint8_t *)&ctrl, sizeof(ICM_20948_USER_CTRL_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
return retval;
}
ICM_20948_Status_e ICM_20948_i2c_controller_configure_peripheral(ICM_20948_Device_t *pdev, uint8_t peripheral, uint8_t addr, uint8_t reg, uint8_t len, bool Rw, bool enable, bool data_only, bool grp, bool swap, uint8_t dataOut)
{
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
uint8_t periph_addr_reg;
uint8_t periph_reg_reg;
uint8_t periph_ctrl_reg;
uint8_t periph_do_reg;
switch (peripheral)
{
case 0:
periph_addr_reg = AGB3_REG_I2C_PERIPH0_ADDR;
periph_reg_reg = AGB3_REG_I2C_PERIPH0_REG;
periph_ctrl_reg = AGB3_REG_I2C_PERIPH0_CTRL;
periph_do_reg = AGB3_REG_I2C_PERIPH0_DO;
break;
case 1:
periph_addr_reg = AGB3_REG_I2C_PERIPH1_ADDR;
periph_reg_reg = AGB3_REG_I2C_PERIPH1_REG;
periph_ctrl_reg = AGB3_REG_I2C_PERIPH1_CTRL;
periph_do_reg = AGB3_REG_I2C_PERIPH1_DO;
break;
case 2:
periph_addr_reg = AGB3_REG_I2C_PERIPH2_ADDR;
periph_reg_reg = AGB3_REG_I2C_PERIPH2_REG;
periph_ctrl_reg = AGB3_REG_I2C_PERIPH2_CTRL;
periph_do_reg = AGB3_REG_I2C_PERIPH2_DO;
break;
case 3:
periph_addr_reg = AGB3_REG_I2C_PERIPH3_ADDR;
periph_reg_reg = AGB3_REG_I2C_PERIPH3_REG;
periph_ctrl_reg = AGB3_REG_I2C_PERIPH3_CTRL;
periph_do_reg = AGB3_REG_I2C_PERIPH3_DO;
break;
default:
return ICM_20948_Stat_ParamErr;
}
retval = ICM_20948_set_bank(pdev, 3);
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
// Set the peripheral address and the Rw flag
ICM_20948_I2C_PERIPHX_ADDR_t address;
address.ID = addr;
if (Rw)
{
address.RNW = 1;
}
else
{
address.RNW = 0; // Make sure bit is clear (just in case there is any garbage in that RAM location)
}
retval = ICM_20948_execute_w(pdev, periph_addr_reg, (uint8_t *)&address, sizeof(ICM_20948_I2C_PERIPHX_ADDR_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
// If we are setting up a write, configure the Data Out register too
if (!Rw)
{
ICM_20948_I2C_PERIPHX_DO_t dataOutByte;
dataOutByte.DO = dataOut;
retval = ICM_20948_execute_w(pdev, periph_do_reg, (uint8_t *)&dataOutByte, sizeof(ICM_20948_I2C_PERIPHX_DO_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
}
// Set the peripheral sub-address (register address)
ICM_20948_I2C_PERIPHX_REG_t subaddress;
subaddress.REG = reg;
retval = ICM_20948_execute_w(pdev, periph_reg_reg, (uint8_t *)&subaddress, sizeof(ICM_20948_I2C_PERIPHX_REG_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
// Set up the control info
ICM_20948_I2C_PERIPHX_CTRL_t ctrl;
ctrl.LENG = len;
ctrl.EN = enable;
ctrl.REG_DIS = data_only;
ctrl.GRP = grp;
ctrl.BYTE_SW = swap;
retval = ICM_20948_execute_w(pdev, periph_ctrl_reg, (uint8_t *)&ctrl, sizeof(ICM_20948_I2C_PERIPHX_CTRL_t));
if (retval != ICM_20948_Stat_Ok)
{
return retval;
}
return retval;
}
// Higher Level
ICM_20948_Status_e ICM_20948_get_agmt(ICM_20948_Device_t *pdev, ICM_20948_AGMT_t *pagmt)
{
if (pagmt == NULL)
{
return ICM_20948_Stat_ParamErr;
}
ICM_20948_Status_e retval = ICM_20948_Stat_Ok;
const uint8_t numbytes = 14 + 9; //Read Accel, gyro, temp, and 9 bytes of mag
uint8_t buff[numbytes];
// Get readings
retval |= ICM_20948_set_bank(pdev, 0);
retval |= ICM_20948_execute_r(pdev, (uint8_t)AGB0_REG_ACCEL_XOUT_H, buff, numbytes);
pagmt->acc.axes.x = ((buff[0] << 8) | (buff[1] & 0xFF));
pagmt->acc.axes.y = ((buff[2] << 8) | (buff[3] & 0xFF));
pagmt->acc.axes.z = ((buff[4] << 8) | (buff[5] & 0xFF));
pagmt->gyr.axes.x = ((buff[6] << 8) | (buff[7] & 0xFF));
pagmt->gyr.axes.y = ((buff[8] << 8) | (buff[9] & 0xFF));
pagmt->gyr.axes.z = ((buff[10] << 8) | (buff[11] & 0xFF));
pagmt->tmp.val = ((buff[12] << 8) | (buff[13] & 0xFF));
pagmt->magStat1 = buff[14];
pagmt->mag.axes.x = ((buff[16] << 8) | (buff[15] & 0xFF)); //Mag data is read little endian
pagmt->mag.axes.y = ((buff[18] << 8) | (buff[17] & 0xFF));
pagmt->mag.axes.z = ((buff[20] << 8) | (buff[19] & 0xFF));
pagmt->magStat2 = buff[22];
// Get settings to be able to compute scaled values
retval |= ICM_20948_set_bank(pdev, 2);