stm32c011.mmap

0x40000400 A PERIPHERAL TIM3
0x40000400 B  REGISTER CR1: TIM3 control register 1
0x40000400 C   FIELD 00w01 CEN (rw): Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.
0x40000400 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
0x40000400 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
0x40000400 C   FIELD 03w01 OPM (rw): One-pulse mode
0x40000400 C   FIELD 04w01 DIR (rw): Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.
0x40000400 C   FIELD 05w02 CMS (rw): Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1)
0x40000400 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40000400 C   FIELD 08w02 CKD (rw): Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),
0x40000400 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40000404 B  REGISTER CR2: TIM3 control register 2
0x40000404 C   FIELD 03w01 CCDS (rw): Capture/compare DMA selection
0x40000404 C   FIELD 04w03 MMS (rw): Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
0x40000404 C   FIELD 07w01 TI1S (rw): TI1 selection
0x40000408 B  REGISTER SMCR: TIM3 slave mode control register
0x40000408 C   FIELD 00w03 SMS (rw): Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0x40000408 C   FIELD 03w01 OCCS (rw): OCREF clear selection This bit is used to select the OCREF clear source
0x40000408 C   FIELD 04w03 TS (rw): Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
0x40000408 C   FIELD 07w01 MSM (rw): Master/Slave mode
0x40000408 C   FIELD 08w04 ETF (rw): External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
0x40000408 C   FIELD 12w02 ETPS (rw): External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
0x40000408 C   FIELD 14w01 ECE (rw): External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
0x40000408 C   FIELD 15w01 ETP (rw): External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
0x40000408 C   FIELD 16w01 SMS_3 (rw): Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0x40000408 C   FIELD 20w02 TS2 (rw): Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
0x4000040C B  REGISTER DIER: TIM3 DMA/Interrupt enable register
0x4000040C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x4000040C C   FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x4000040C C   FIELD 02w01 CC2IE (rw): Capture/Compare 2 interrupt enable
0x4000040C C   FIELD 03w01 CC3IE (rw): Capture/Compare 3 interrupt enable
0x4000040C C   FIELD 04w01 CC4IE (rw): Capture/Compare 4 interrupt enable
0x4000040C C   FIELD 06w01 TIE (rw): Trigger interrupt enable
0x4000040C C   FIELD 08w01 UDE (rw): Update DMA request enable
0x4000040C C   FIELD 09w01 CC1DE (rw): Capture/Compare 1 DMA request enable
0x4000040C C   FIELD 10w01 CC2DE (rw): Capture/Compare 2 DMA request enable
0x4000040C C   FIELD 11w01 CC3DE (rw): Capture/Compare 3 DMA request enable
0x4000040C C   FIELD 12w01 CC4DE (rw): Capture/Compare 4 DMA request enable
0x4000040C C   FIELD 14w01 TDE (rw): Trigger DMA request enable
0x40000410 B  REGISTER SR: TIM3 status register
0x40000410 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register.
0x40000410 C   FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag
0x40000410 C   FIELD 02w01 CC2IF (rw): Capture/compare 2 interrupt flag
0x40000410 C   FIELD 03w01 CC3IF (rw): Capture/compare 3 interrupt flag
0x40000410 C   FIELD 04w01 CC4IF (rw): Capture/compare 4 interrupt flag
0x40000410 C   FIELD 06w01 TIF (rw): Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
0x40000410 C   FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag
0x40000410 C   FIELD 10w01 CC2OF (rw): Capture/Compare 2 overcapture flag
0x40000410 C   FIELD 11w01 CC3OF (rw): Capture/Compare 3 overcapture flag
0x40000410 C   FIELD 12w01 CC4OF (rw): Capture/Compare 4 overcapture flag
0x40000414 B  REGISTER EGR: TIM3 event generation register
0x40000414 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40000414 C   FIELD 01w01 CC1G (wo): Capture/compare 1 generation
0x40000414 C   FIELD 02w01 CC2G (wo): Capture/compare 2 generation
0x40000414 C   FIELD 03w01 CC3G (wo): Capture/compare 3 generation
0x40000414 C   FIELD 04w01 CC4G (wo): Capture/compare 4 generation
0x40000414 C   FIELD 06w01 TG (wo): Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40000418 B  REGISTER CCMR1_Input: TIM3 capture/compare mode register 1 [alternate]
0x40000418 B  REGISTER CCMR1_Output: TIM3 capture/compare mode register 1 [alternate]
0x40000418 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40000418 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
0x40000418 C   FIELD 02w01 OC1FE (rw): Output compare 1 fast enable
0x40000418 C   FIELD 02w02 IC1PSC (rw): Input capture 1 prescaler
0x40000418 C   FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40000418 C   FIELD 04w03 OC1M (rw): Output compare 1 mode
0x40000418 C   FIELD 04w04 IC1F (rw): Input capture 1 filter
0x40000418 C   FIELD 07w01 OC1CE (rw): Output compare 1 clear enable
0x40000418 C   FIELD 08w02 CC2S (rw): Capture/Compare 2 selection
0x40000418 C   FIELD 08w02 CC2S (rw): Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
0x40000418 C   FIELD 10w01 OC2FE (rw): Output compare 2 fast enable
0x40000418 C   FIELD 10w02 IC2PSC (rw): Input capture 2 prescaler
0x40000418 C   FIELD 11w01 OC2PE (rw): Output compare 2 preload enable
0x40000418 C   FIELD 12w03 OC2M (rw): Output compare 2 mode
0x40000418 C   FIELD 12w04 IC2F (rw): Input capture 2 filter
0x40000418 C   FIELD 15w01 OC2CE (rw): Output compare 2 clear enable
0x40000418 C   FIELD 16w01 OC1M_3 (rw): Output compare 1 mode, bit 3
0x40000418 C   FIELD 24w01 OC2M_3 (rw): Output compare 2 mode, bit 3
0x4000041C B  REGISTER CCMR2_Input: TIM3 capture/compare mode register 2 [alternate]
0x4000041C B  REGISTER CCMR2_Output: TIM3 capture/compare mode register 2 [alternate]
0x4000041C C   FIELD 00w02 CC3S (=TIM3.CCMR1_Output.CC%sS) (rw): Capture/Compare 3 selection
0x4000041C C   FIELD 00w02 CC3S (rw): Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
0x4000041C C   FIELD 02w01 OC3FE (=TIM3.CCMR1_Output.OC%sFE) (rw): Output compare 3 fast enable
0x4000041C C   FIELD 02w02 IC3PSC (=TIM3.CCMR1_Input.IC%sPSC) (rw): Input capture 3 prescaler
0x4000041C C   FIELD 03w01 OC3PE (=TIM3.CCMR1_Output.OC%sPE) (rw): Output compare 3 preload enable
0x4000041C C   FIELD 04w03 OC3M (=TIM3.CCMR1_Output.OC%sM) (rw): Output compare 3 mode
0x4000041C C   FIELD 04w04 IC3F (=TIM3.CCMR1_Input.IC%sF) (rw): Input capture 3 filter
0x4000041C C   FIELD 07w01 OC3CE (=TIM3.CCMR1_Output.OC%sCE) (rw): Output compare 3 clear enable
0x4000041C C   FIELD 08w02 CC4S (=TIM3.CCMR1_Output.CC%sS) (rw): Capture/Compare 4 selection
0x4000041C C   FIELD 08w02 CC4S (rw): Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
0x4000041C C   FIELD 10w01 OC4FE (=TIM3.CCMR1_Output.OC%sFE) (rw): Output compare 4 fast enable
0x4000041C C   FIELD 10w02 IC4PSC (=TIM3.CCMR1_Input.IC%sPSC) (rw): Input capture 4 prescaler
0x4000041C C   FIELD 11w01 OC4PE (=TIM3.CCMR1_Output.OC%sPE) (rw): Output compare 4 preload enable
0x4000041C C   FIELD 12w03 OC4M (=TIM3.CCMR1_Output.OC%sM) (rw): Output compare 4 mode
0x4000041C C   FIELD 12w04 IC4F (=TIM3.CCMR1_Input.IC%sF) (rw): Input capture 4 filter
0x4000041C C   FIELD 15w01 OC4CE (=TIM3.CCMR1_Output.OC%sCE) (rw): Output compare 4 clear enable
0x4000041C C   FIELD 16w01 OC3M_3 (=TIM3.CCMR1_Output.OC%sM_3) (rw): Output compare 3 mode, bit 3
0x4000041C C   FIELD 24w01 OC4M_3 (=TIM3.CCMR1_Output.OC%sM_3) (rw): Output compare 4 mode, bit 3
0x40000420 B  REGISTER CCER: TIM3 capture/compare enable register
0x40000420 C   FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable
0x40000420 C   FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity
0x40000420 C   FIELD 03w01 CC1NP (rw): Capture/Compare 1 output Polarity
0x40000420 C   FIELD 04w01 CC2E (rw): Capture/Compare 2 output enable
0x40000420 C   FIELD 05w01 CC2P (rw): Capture/Compare 2 output Polarity
0x40000420 C   FIELD 07w01 CC2NP (rw): Capture/Compare 2 output Polarity
0x40000420 C   FIELD 08w01 CC3E (rw): Capture/Compare 3 output enable
0x40000420 C   FIELD 09w01 CC3P (rw): Capture/Compare 3 output Polarity
0x40000420 C   FIELD 11w01 CC3NP (rw): Capture/Compare 3 output Polarity
0x40000420 C   FIELD 12w01 CC4E (rw): Capture/Compare 4 output enable
0x40000420 C   FIELD 13w01 CC4P (rw): Capture/Compare 4 output Polarity
0x40000420 C   FIELD 15w01 CC4NP (rw): Capture/Compare 4 output Polarity
0x40000424 B  REGISTER CNT: TIM3 counter [alternate]
0x40000424 B  REGISTER CNT_remap: TIM3 counter [alternate]
0x40000424 C   FIELD 00w16 CNT (rw): counter value
0x40000424 C   FIELD 00w16 CNT (rw): counter value
0x40000424 C   FIELD 31w01 UIFCPY (rw): UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register
0x40000428 B  REGISTER PSC: TIM3 prescaler
0x40000428 C   FIELD 00w16 PSC (rw): Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode).
0x4000042C B  REGISTER ARR: TIM3 auto-reload register
0x4000042C C   FIELD 00w16 ARR (rw): Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null.
0x40000434 B  REGISTER CCR1: capture/compare register
0x40000434 C   FIELD 00w16 CCR (rw): Capture/Compare value
0x40000438 B  REGISTER CCR2: capture/compare register
0x40000438 C   FIELD 00w16 CCR (rw): Capture/Compare value
0x4000043C B  REGISTER CCR3: capture/compare register
0x4000043C C   FIELD 00w16 CCR (rw): Capture/Compare value
0x40000440 B  REGISTER CCR4: capture/compare register
0x40000440 C   FIELD 00w16 CCR (rw): Capture/Compare value
0x40000448 B  REGISTER DCR: TIM3 DMA control register
0x40000448 C   FIELD 00w05 DBA (rw): DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
0x40000448 C   FIELD 08w05 DBL (rw): DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ...
0x4000044C B  REGISTER DMAR: TIM3 DMA address for full transfer
0x4000044C C   FIELD 00w16 DMAB (rw): DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
0x40000460 B  REGISTER AF1: TIM3 alternate function option register 1
0x40000460 C   FIELD 14w04 ETRSEL (rw): ETR source selection These bits select the ETR input source. Others: Reserved
0x40000468 B  REGISTER TISEL: TIM3 timer input selection register
0x40000468 C   FIELD 00w04 TI1SEL (rw): TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved
0x40000468 C   FIELD 08w04 TI2SEL (rw): TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved
0x40000468 C   FIELD 16w04 TI3SEL (rw): TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. Others: Reserved
0x40002000 A PERIPHERAL TIM14
0x40002000 B  REGISTER CR1: TIM14 control register 1
0x40002000 C   FIELD 00w01 CEN (rw): Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
0x40002000 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. Counter overflow Setting the UG bit. Buffered registers are then loaded with their preload values.
0x40002000 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. Counter overflow Setting the UG bit
0x40002000 C   FIELD 03w01 OPM (rw): One-pulse mode
0x40002000 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40002000 C   FIELD 08w02 CKD (rw): Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx),
0x40002000 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x4000200C B  REGISTER DIER: TIM14 Interrupt enable register
0x4000200C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x4000200C C   FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x40002010 B  REGISTER SR: TIM14 status register
0x40002010 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register.
0x40002010 C   FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag
0x40002010 C   FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag
0x40002014 B  REGISTER EGR: TIM14 event generation register
0x40002014 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40002014 C   FIELD 01w01 CC1G (wo): Capture/compare 1 generation
0x40002018 B  REGISTER CCMR1_Input: TIM14 capture/compare mode register 1 [alternate]
0x40002018 B  REGISTER CCMR1_Output: TIM14 capture/compare mode register 1 [alternate]
0x40002018 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40002018 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
0x40002018 C   FIELD 02w01 OC1FE (rw): Output compare 1 fast enable
0x40002018 C   FIELD 02w02 IC1PSC (rw): Input capture 1 prescaler
0x40002018 C   FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40002018 C   FIELD 04w03 OC1M (rw): Output compare 1 mode
0x40002018 C   FIELD 04w04 IC1F (rw): Input capture 1 filter
0x40002018 C   FIELD 16w01 OC1M_3 (rw): Output compare 1 mode, bit 3
0x40002020 B  REGISTER CCER: TIM14 capture/compare enable register
0x40002020 C   FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable
0x40002020 C   FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity
0x40002020 C   FIELD 03w01 CC1NP (rw): Capture/Compare 1 output Polarity
0x40002024 B  REGISTER CNT: TIM14 counter
0x40002024 C   FIELD 00w16 CNT (rw): Counter value
0x40002024 C   FIELD 31w01 UIFCPY (rw): UIF Copy This bit is a read-only copy of the UIF bit in the TIMx_ISR register.
0x40002028 B  REGISTER PSC: TIM14 prescaler
0x40002028 C   FIELD 00w16 PSC (rw): Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode).
0x4000202C B  REGISTER ARR: TIM14 auto-reload register
0x4000202C C   FIELD 00w16 ARR (rw): Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null.
0x40002034 B  REGISTER CCR1: capture/compare register
0x40002034 C   FIELD 00w16 CCR (rw): Capture/Compare value
0x40002068 B  REGISTER TISEL: TIM14 timer input selection register
0x40002068 C   FIELD 00w04 TI1SEL (rw): selects TI1[0] to TI1[15] input Others: Reserved
0x40002800 A PERIPHERAL RTC
0x40002800 B  REGISTER TR: RTC time register
0x40002800 C   FIELD 00w04 SU (rw): Second units in BCD format
0x40002800 C   FIELD 04w03 ST (rw): Second tens in BCD format
0x40002800 C   FIELD 08w04 MNU (rw): Minute units in BCD format
0x40002800 C   FIELD 12w03 MNT (rw): Minute tens in BCD format
0x40002800 C   FIELD 16w04 HU (rw): Hour units in BCD format
0x40002800 C   FIELD 20w02 HT (rw): Hour tens in BCD format
0x40002800 C   FIELD 22w01 PM (rw): AM/PM notation
0x40002804 B  REGISTER DR: RTC date register
0x40002804 C   FIELD 00w04 DU (rw): Date units in BCD format
0x40002804 C   FIELD 04w02 DT (rw): Date tens in BCD format
0x40002804 C   FIELD 08w04 MU (rw): Month units in BCD format
0x40002804 C   FIELD 12w01 MT (rw): Month tens in BCD format
0x40002804 C   FIELD 13w03 WDU (rw): Week day units ...
0x40002804 C   FIELD 16w04 YU (rw): Year units in BCD format
0x40002804 C   FIELD 20w04 YT (rw): Year tens in BCD format
0x40002808 B  REGISTER SSR: RTC sub second register
0x40002808 C   FIELD 00w16 SS (ro): Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR.
0x4000280C B  REGISTER ICSR: RTC initialization control and status register
0x4000280C C   FIELD 00w01 ALRAWF (ro): Alarm A write flag This bit is set by hardware when alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode.
0x4000280C C   FIELD 03w01 SHPF (ro): Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect.
0x4000280C C   FIELD 04w01 INITS (ro): Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Power-on reset state).
0x4000280C C   FIELD 05w01 RSF (rw): Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode.
0x4000280C C   FIELD 06w01 INITF (ro): Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated.
0x4000280C C   FIELD 07w01 INIT (rw): Initialization mode
0x4000280C C   FIELD 16w01 RECALPF (ro): Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to .
0x40002810 B  REGISTER PRER: RTC prescaler register
0x40002810 C   FIELD 00w15 PREDIV_S (rw): Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1)
0x40002810 C   FIELD 16w07 PREDIV_A (rw): Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
0x40002818 B  REGISTER CR: RTC control register
0x40002818 C   FIELD 03w01 TSEDGE (rw): Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
0x40002818 C   FIELD 04w01 REFCKON (rw): RTC_REFIN reference clock detection enable (50 or 60 Hz) Note: PREDIV_S must be 0x00FF.
0x40002818 C   FIELD 05w01 BYPSHAD (rw): Bypass the shadow registers Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1.
0x40002818 C   FIELD 06w01 FMT (rw): Hour format
0x40002818 C   FIELD 08w01 ALRAE (rw): Alarm A enable
0x40002818 C   FIELD 11w01 TSE (rw): timestamp enable
0x40002818 C   FIELD 12w01 ALRAIE (rw): Alarm A interrupt enable
0x40002818 C   FIELD 15w01 TSIE (rw): Timestamp interrupt enable
0x40002818 C   FIELD 16w01 ADD1H (wo): Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0.
0x40002818 C   FIELD 17w01 SUB1H (wo): Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0.
0x40002818 C   FIELD 18w01 BKP (rw): Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.
0x40002818 C   FIELD 19w01 COSEL (rw): Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to .
0x40002818 C   FIELD 20w01 POL (rw): Output polarity This bit is used to configure the polarity of TAMPALRM output.
0x40002818 C   FIELD 21w02 OSEL (rw): Output selection These bits are used to select the flag to be routed to TAMPALRM output.
0x40002818 C   FIELD 23w01 COE (rw): Calibration output enable This bit enables the CALIB output
0x40002818 C   FIELD 29w01 TAMPALRM_PU (rw): TAMPALRM pull-up enable
0x40002818 C   FIELD 30w01 TAMPALRM_TYPE (rw): TAMPALRM output type
0x40002818 C   FIELD 31w01 OUT2EN (rw): RTC_OUT2 output enable Setting this bit allows to remap the RTC outputs on RTC_OUT2 as follows: OUT2EN = 0: RTC output 2 disable If OSEL different of 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL different of 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2 If (OSELdifferent of 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and TAMPALRM is output on RTC_OUT1.
0x40002824 B  REGISTER WPR: RTC write protection register
0x40002824 C   FIELD 00w08 KEY (wo): Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to for a description of how to unlock RTC register write protection.
0x40002828 B  REGISTER CALR: RTC calibration register
0x40002828 C   FIELD 00w09 CALM (rw): Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See .
0x40002828 C   FIELD 13w01 CALW16 (rw): Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1. Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to calibration.
0x40002828 C   FIELD 14w01 CALW8 (rw): Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to digital calibration.
0x40002828 C   FIELD 15w01 CALP (rw): Increase frequency of RTC by 488.5 ppm This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 CALP) - CALM. Refer to .
0x4000282C B  REGISTER SHIFTR: RTC shift control register
0x4000282C C   FIELD 00w15 SUBFS (wo): Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time.
0x4000282C C   FIELD 31w01 ADD1S (wo): Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation.
0x40002830 B  REGISTER TSTR (=TR): RTC timestamp time register
0x40002834 B  REGISTER TSDR (=DR): RTC timestamp date register
0x40002838 B  REGISTER TSSSR (=SSR): RTC timestamp sub second register
0x40002840 B  REGISTER ALRMAR: Alarm register
0x40002840 C   FIELD 00w04 SU (rw): Second units in BCD format
0x40002840 C   FIELD 04w03 ST (rw): Second tens in BCD format
0x40002840 C   FIELD 07w01 MSK1 (rw): Alarm seconds mask
0x40002840 C   FIELD 08w04 MNU (rw): Minute units in BCD format
0x40002840 C   FIELD 12w03 MNT (rw): Minute tens in BCD format
0x40002840 C   FIELD 15w01 MSK2 (rw): Alarm minutes mask
0x40002840 C   FIELD 16w04 HU (rw): Hour units in BCD format
0x40002840 C   FIELD 20w02 HT (rw): Hour tens in BCD format
0x40002840 C   FIELD 22w01 PM (rw): AM/PM notation
0x40002840 C   FIELD 23w01 MSK3 (rw): Alarm hours mask
0x40002840 C   FIELD 24w04 DU (rw): Date units or day in BCD format
0x40002840 C   FIELD 28w02 DT (rw): Date tens in BCD format
0x40002840 C   FIELD 30w01 WDSEL (rw): Week day selection
0x40002840 C   FIELD 31w01 MSK4 (rw): Alarm date mask
0x40002844 B  REGISTER ALRMASSR: Alarm sub-second register
0x40002844 C   FIELD 00w15 SS (rw): Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.
0x40002844 C   FIELD 24w04 MASKSS (rw): Mask the most-significant bits starting at this bit 2: SS[14:2] are dont care in alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are dont care in alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are dont care in alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are dont care in alarm A comparison. SS[12:0] are compared. 14: SS[14] is dont care in alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation.
0x40002850 B  REGISTER SR: RTC status register
0x40002850 C   FIELD 00w01 ALRAF (ro): Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm A register (RTC_ALRMAR).
0x40002850 C   FIELD 03w01 TSF (ro): Timestamp flag This flag is set by hardware when a timestamp event occurs.
0x40002850 C   FIELD 04w01 TSOVF (ro): Timestamp overflow flag This flag is set by hardware when a timestamp event occurs while TSF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
0x40002854 B  REGISTER MISR: RTC masked interrupt status register
0x40002854 C   FIELD 00w01 ALRAMF (ro): Alarm A masked flag This flag is set by hardware when the alarm A interrupt occurs.
0x40002854 C   FIELD 03w01 TSMF (ro): Timestamp masked flag This flag is set by hardware when a timestamp interrupt occurs.
0x40002854 C   FIELD 04w01 TSOVMF (ro): Timestamp overflow masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
0x4000285C B  REGISTER SCR: RTC status clear register
0x4000285C C   FIELD 00w01 CALRAF (wo): Clear alarm A flag Writing 1 in this bit clears the ALRAF bit in the RTC_SR register.
0x4000285C C   FIELD 03w01 CTSF (wo): Clear timestamp flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register.
0x4000285C C   FIELD 04w01 CTSOVF (wo): Clear timestamp overflow flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
0x40002C00 A PERIPHERAL WWDG
0x40002C00 B  REGISTER CR: WWDG control register
0x40002C00 C   FIELD 00w07 T (rw): 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter, decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared).
0x40002C00 C   FIELD 07w01 WDGA (rw): Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset.
0x40002C04 B  REGISTER CFR: WWDG configuration register
0x40002C04 C   FIELD 00w07 W (rw): 7-bit window value These bits contain the window value to be compared with the down-counter.
0x40002C04 C   FIELD 09w01 EWI (rw): Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset.
0x40002C04 C   FIELD 11w03 WDGTB: Timer base The timebase of the prescaler can be modified as follows:
0x40002C08 B  REGISTER SR: WWDG status register
0x40002C08 C   FIELD 00w01 EWIF (rw): Early wakeup interrupt flag This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. Writing 1 has no effect. This bit is also set if the interrupt is not enabled.
0x40003000 A PERIPHERAL IWDG
0x40003000 B  REGISTER KR: IWDG key register
0x40003000 C   FIELD 00w16 KEY (wo): Key value (write only, read 0x0000) These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see ) Writing the key value 0xCCCC starts the watchdog (except if the hardware watchdog option is selected)
0x40003004 B  REGISTER PR: IWDG prescaler register
0x40003004 C   FIELD 00w03 PR (rw): Prescaler divider These bits are write access protected see . They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the must be reset in order to be able to change the prescaler divider. Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the status register (IWDG_SR) is reset.
0x40003008 B  REGISTER RLR: IWDG reload register
0x40003008 C   FIELD 00w12 RL (rw): Watchdog counter reload value These bits are write access protected see . They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the . The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. Refer to the datasheet for the timeout information. The RVU bit in the must be reset to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing on it. For this reason the value read from this register is valid only when the RVU bit in the status register (IWDG_SR) is reset.
0x4000300C B  REGISTER SR: IWDG status register
0x4000300C C   FIELD 00w01 PVU (ro): Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Prescaler value can be updated only when PVU bit is reset.
0x4000300C C   FIELD 01w01 RVU (ro): Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Reload value can be updated only when RVU bit is reset.
0x4000300C C   FIELD 02w01 WVU (ro): Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Window value can be updated only when WVU bit is reset.
0x40003010 B  REGISTER WINR: IWDG window register
0x40003010 C   FIELD 00w12 WIN (rw): Watchdog counter window value These bits are write access protected, see , they contain the high limit of the window value to be compared with the downcounter. To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 The WVU bit in the must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the (IWDG_SR) is reset.
0x40004400 A PERIPHERAL USART2
0x40004400 B  REGISTER CR1: USART control register 1 [alternate]
0x40004400 C   FIELD 00w01 UE (rw): USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value.
0x40004400 C   FIELD 01w01 UESM (rw): USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985.
0x40004400 C   FIELD 02w01 RE (rw): Receiver enable This bit enables the receiver. It is set and cleared by software.
0x40004400 C   FIELD 03w01 TE (rw): Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.
0x40004400 C   FIELD 04w01 IDLEIE (rw): IDLE interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 05w01 RXNEIE (rw): RXFIFO not empty interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 06w01 TCIE (rw): Transmission complete interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 07w01 TXEIE (rw): TXFIFO not full interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 08w01 PEIE (rw): PE interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 09w01 PS (rw): Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0).
0x40004400 C   FIELD 10w01 PCE (rw): Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0).
0x40004400 C   FIELD 11w01 WAKE (rw): Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0).
0x40004400 C   FIELD 12w01 M0 (rw): Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0).
0x40004400 C   FIELD 13w01 MME (rw): Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software.
0x40004400 C   FIELD 14w01 CMIE (rw): Character match interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 15w01 OVER8 (rw): Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.
0x40004400 C   FIELD 16w05 DEDT (rw): Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004400 C   FIELD 21w05 DEAT (rw): Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004400 C   FIELD 26w01 RTOIE (rw): Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. .
0x40004400 C   FIELD 27w01 EOBIE (rw): End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40004400 C   FIELD 28w01 M1 (rw): Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00: 1 start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 start bit, 9 Data bits, n Stop bit M[1:0] = 10: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported.
0x40004400 C   FIELD 29w01 FIFOEN (rw): FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
0x40004400 C   FIELD 30w01 TXFEIE (rw): TXFIFO empty interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 31w01 RXFFIE (rw): RXFIFO Full interrupt enable This bit is set and cleared by software.
0x40004404 B  REGISTER CR2: USART control register 2
0x40004404 C   FIELD 00w01 SLVEN (rw): Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 03w01 DIS_NSS (rw): When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 04w01 ADDM7 (rw): 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively.
0x40004404 C   FIELD 05w01 LBDL (rw): LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 06w01 LBDIE (rw): LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 08w01 LBCL (rw): Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 09w01 CPHA (rw): Clock phase This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 10w01 CPOL (rw): Clock polarity This bit enables the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 11w01 CLKEN (rw): Clock enable This bit enables the user to enable the CK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1
0x40004404 C   FIELD 12w02 STOP (rw): stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0).
0x40004404 C   FIELD 14w01 LINEN (rw): LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 15w01 SWAP (rw): Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0).
0x40004404 C   FIELD 16w01 RXINV (rw): RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0).
0x40004404 C   FIELD 17w01 TXINV (rw): TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0).
0x40004404 C   FIELD 18w01 DATAINV (rw): Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0).
0x40004404 C   FIELD 19w01 MSBFIRST (rw): Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0).
0x40004404 C   FIELD 20w01 ABREN (rw): Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 21w02 ABRMOD (rw): Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 23w01 RTOEN (rw): Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 24w08 ADD (rw): Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0).
0x40004408 B  REGISTER CR3: USART control register 3
0x40004408 C   FIELD 00w01 EIE (rw): Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register).
0x40004408 C   FIELD 01w01 IREN (rw): IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 02w01 IRLP (rw): IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 03w01 HDSEL (rw): Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0).
0x40004408 C   FIELD 04w01 NACK (rw): Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 05w01 SCEN (rw): Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 06w01 DMAR (rw): DMA enable receiver This bit is set/reset by software
0x40004408 C   FIELD 07w01 DMAT (rw): DMA enable transmitter This bit is set/reset by software
0x40004408 C   FIELD 08w01 RTSE (rw): RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 09w01 CTSE (rw): CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 10w01 CTSIE (rw): CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 11w01 ONEBIT (rw): One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0).
0x40004408 C   FIELD 12w01 OVRDIS (rw): Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data
0x40004408 C   FIELD 13w01 DDRE (rw): DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error.
0x40004408 C   FIELD 14w01 DEM (rw): Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. .
0x40004408 C   FIELD 15w01 DEP (rw): Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 17w03 SCARCNT (rw): Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 20w02 WUS (rw): Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985.
0x40004408 C   FIELD 22w01 WUFIE (rw): Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985.
0x40004408 C   FIELD 23w01 TXFTIE (rw): TXFIFO threshold interrupt enable This bit is set and cleared by software.
0x40004408 C   FIELD 24w01 TCBGTIE (rw): Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 25w03 RXFTCFG (rw): Receive FIFO threshold configuration Remaining combinations: Reserved
0x40004408 C   FIELD 28w01 RXFTIE (rw): RXFIFO threshold interrupt enable This bit is set and cleared by software.
0x40004408 C   FIELD 29w03 TXFTCFG (rw): TXFIFO threshold configuration Remaining combinations: Reserved
0x4000440C B  REGISTER BRR: USART baud rate register
0x4000440C C   FIELD 00w16 BRR (rw): USART baud rate BRR[15:4] BRR[15:4] = USARTDIV[15:4] BRR[3:0] When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. When OVER8 = 1: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared.
0x40004410 B  REGISTER GTPR: USART guard time and prescaler register
0x40004410 C   FIELD 00w08 PSC (rw): Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... ... This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to 0 when the Smartcard and IrDA modes are not supported. Refer to .
0x40004410 C   FIELD 08w08 GT (rw): Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004414 B  REGISTER RTOR: USART receiver timeout register
0x40004414 C   FIELD 00w24 RTO (rw): Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character.
0x40004414 C   FIELD 24w08 BLEN (rw): Block Length This bitfield gives the Block length in Smartcard T = 1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0: 0 information characters + LEC BLEN = 1: 0 information characters + CRC BLEN = 255: 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE = 0 (TXFE = 0 in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE = 0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block.
0x40004418 B  REGISTER RQR: USART request register
0x40004418 C   FIELD 00w01 ABRRQ (wo): Auto baud rate request Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0x40004418 C   FIELD 01w01 SBKRQ (wo): Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit.
0x40004418 C   FIELD 02w01 MMRQ (wo): Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag.
0x40004418 C   FIELD 03w01 RXFRQ (wo): Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition.
0x40004418 C   FIELD 04w01 TXFRQ (wo): Transmit data flush request When FIFO mode is disabled, writing 1 to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register.
0x4000441C B  REGISTER ISR: USART interrupt and status register [alternate]
0x4000441C C   FIELD 00w01 PE (ro): Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
0x4000441C C   FIELD 01w01 FE (ro): Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
0x4000441C C   FIELD 02w01 NE (ro): Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 2012). This error is associated with the character in the USART_RDR.
0x4000441C C   FIELD 03w01 ORE (ro): Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE = 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register.
0x4000441C C   FIELD 04w01 IDLE (ro): Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set.
0x4000441C C   FIELD 05w01 RXFNE (ro): RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register.
0x4000441C C   FIELD 06w01 TC (ro): Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set.
0x4000441C C   FIELD 07w01 TXFNF (ro): TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission.
0x4000441C C   FIELD 08w01 LBDF (ro): LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to .
0x4000441C C   FIELD 09w01 CTSIF (ro): CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
0x4000441C C   FIELD 10w01 CTS (ro): CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
0x4000441C C   FIELD 11w01 RTOF (ro): Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value.
0x4000441C C   FIELD 12w01 EOBF (ro): End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to .
0x4000441C C   FIELD 13w01 UDR (ro): SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to .
0x4000441C C   FIELD 14w01 ABRE (ro): Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
0x4000441C C   FIELD 15w01 ABRF (ro): Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
0x4000441C C   FIELD 16w01 BUSY (ro): Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not).
0x4000441C C   FIELD 17w01 CMF (ro): Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register.
0x4000441C C   FIELD 18w01 SBKF (ro): Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission.
0x4000441C C   FIELD 19w01 RWU (ro): Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4000441C C   FIELD 20w01 WUF (ro): Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4000441C C   FIELD 21w01 TEACK (ro): Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period.
0x4000441C C   FIELD 22w01 REACK (ro): Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4000441C C   FIELD 23w01 TXFE (ro): TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the USART_CR1 register.
0x4000441C C   FIELD 24w01 RXFF (ro): RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit = 1 in the USART_CR1 register.
0x4000441C C   FIELD 25w01 TCBGT (ro): Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is 1. Refer to on page 1985.
0x4000441C C   FIELD 26w01 RXFT (ro): RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to 101, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data.
0x4000441C C   FIELD 27w01 TXFT (ro): TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit = 1 (bit 31) in the USART_CR3 register.
0x40004420 B  REGISTER ICR: USART interrupt flag clear register
0x40004420 C   FIELD 00w01 PECF (wo): Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register.
0x40004420 C   FIELD 01w01 FECF (wo): Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register.
0x40004420 C   FIELD 02w01 NECF (wo): Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register.
0x40004420 C   FIELD 03w01 ORECF (wo): Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register.
0x40004420 C   FIELD 04w01 IDLECF (wo): Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
0x40004420 C   FIELD 05w01 TXFECF (wo): TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register.
0x40004420 C   FIELD 06w01 TCCF (wo): Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register.
0x40004420 C   FIELD 07w01 TCBGTCF (wo): Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register.
0x40004420 C   FIELD 08w01 LBDCF (wo): LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004420 C   FIELD 09w01 CTSCF (wo): CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004420 C   FIELD 11w01 RTOCF (wo): Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 1985.
0x40004420 C   FIELD 12w01 EOBCF (wo): End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40004420 C   FIELD 13w01 UDRCF (wo): SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to
0x40004420 C   FIELD 17w01 CMCF (wo): Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register.
0x40004420 C   FIELD 20w01 WUCF (wo): Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985.
0x40004424 B  REGISTER RDR: USART receive data register
0x40004424 C   FIELD 00w09 RDR (ro): Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see ). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit.
0x40004428 B  REGISTER TDR: USART transmit data register
0x40004428 C   FIELD 00w09 TDR (rw): Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see ). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF = 1.
0x4000442C B  REGISTER PRESC: USART prescaler register
0x4000442C C   FIELD 00w04 PRESCALER (rw): Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256.
0x40005400 A PERIPHERAL I2C1
0x40005400 B  REGISTER CR1: I2C control register 1
0x40005400 C   FIELD 00w01 PE (rw): Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
0x40005400 C   FIELD 01w01 TXIE (rw): TX Interrupt enable
0x40005400 C   FIELD 02w01 RXIE (rw): RX Interrupt enable
0x40005400 C   FIELD 03w01 ADDRIE (rw): Address match Interrupt enable (slave only)
0x40005400 C   FIELD 04w01 NACKIE (rw): Not acknowledge received Interrupt enable
0x40005400 C   FIELD 05w01 STOPIE (rw): Stop detection Interrupt enable
0x40005400 C   FIELD 06w01 TCIE (rw): Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)
0x40005400 C   FIELD 07w01 ERRIE (rw): Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)
0x40005400 C   FIELD 08w04 DNF (rw): Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0).
0x40005400 C   FIELD 12w01 ANFOFF (rw): Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0).
0x40005400 C   FIELD 14w01 TXDMAEN (rw): DMA transmission requests enable
0x40005400 C   FIELD 15w01 RXDMAEN (rw): DMA reception requests enable
0x40005400 C   FIELD 16w01 SBC (rw): Slave byte control This bit is used to enable hardware byte control in slave mode.
0x40005400 C   FIELD 17w01 NOSTRETCH (rw): Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0).
0x40005400 C   FIELD 18w01 WUPEN (rw): Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Refer to . Note: WUPEN can be set only when DNF = 0000
0x40005400 C   FIELD 19w01 GCEN (rw): General call enable
0x40005400 C   FIELD 20w01 SMBHEN (rw): SMBus host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to .
0x40005400 C   FIELD 21w01 SMBDEN (rw): SMBus device default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to .
0x40005400 C   FIELD 22w01 ALERTEN (rw): SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to .
0x40005400 C   FIELD 23w01 PECEN (rw): PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to .
0x40005404 B  REGISTER CR2: I2C control register 2
0x40005404 C   FIELD 00w10 SADD (rw): Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed.
0x40005404 C   FIELD 10w01 RD_WRN (rw): Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005404 C   FIELD 11w01 ADD10 (rw): 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005404 C   FIELD 12w01 HEAD10R (rw): 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005404 C   FIELD 13w01 START (rw): Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by an address matched in slave mode, by a timeout error detection, or when PE = 0. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing 0 to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set.
0x40005404 C   FIELD 14w01 STOP (rw): Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing 0 to this bit has no effect.
0x40005404 C   FIELD 15w01 NACK (rw): NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing 0 to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value.
0x40005404 C   FIELD 16w08 NBYTES (rw): Number of bytes The number of bytes to be transmitted/received is programmed there. This field is dont care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed.
0x40005404 C   FIELD 24w01 RELOAD (rw): NBYTES reload mode This bit is set and cleared by software.
0x40005404 C   FIELD 25w01 AUTOEND (rw): Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set.
0x40005404 C   FIELD 26w01 PECBYTE (rw): Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing 0 to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to .
0x40005408 B  REGISTER OAR1: I2C own address 1 register
0x40005408 C   FIELD 00w10 OA1 (rw): Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0.
0x40005408 C   FIELD 10w01 OA1MODE (rw): Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0.
0x40005408 C   FIELD 15w01 OA1EN (rw): Own Address 1 enable
0x4000540C B  REGISTER OAR2: I2C own address 2 register
0x4000540C C   FIELD 01w07 OA2 (rw): Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0.
0x4000540C C   FIELD 08w03 OA2MSK (rw): Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches.
0x4000540C C   FIELD 15w01 OA2EN (rw): Own Address 2 enable
0x40005410 B  REGISTER TIMINGR: I2C timing register
0x40005410 C   FIELD 00w08 SCLL (rw): SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings.
0x40005410 C   FIELD 08w08 SCLH (rw): SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing.
0x40005410 C   FIELD 16w04 SDADEL (rw): Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing.
0x40005410 C   FIELD 20w04 SCLDEL (rw): Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing.
0x40005410 C   FIELD 28w04 PRESC (rw): Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters (refer to ) and for SCL high and low level counters (refer to ). tPRESC = (PRESC+1) x tI2CCLK
0x40005414 B  REGISTER TIMEOUTR: I2C timeout register
0x40005414 C   FIELD 00w12 TIMEOUTA (rw): Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0.
0x40005414 C   FIELD 12w01 TIDLE (rw): Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0.
0x40005414 C   FIELD 15w01 TIMOUTEN (rw): Clock timeout enable
0x40005414 C   FIELD 16w12 TIMEOUTB (rw): Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0.
0x40005414 C   FIELD 31w01 TEXTEN (rw): Extended clock timeout enable
0x40005418 B  REGISTER ISR: I2C interrupt and status register
0x40005418 C   FIELD 00w01 TXE (rw): Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE=0.
0x40005418 C   FIELD 01w01 TXIS (rw): Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0.
0x40005418 C   FIELD 02w01 RXNE (ro): Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0.
0x40005418 C   FIELD 03w01 ADDR (ro): Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE=0.
0x40005418 C   FIELD 04w01 NACKF (ro): Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE=0.
0x40005418 C   FIELD 05w01 STOPF (ro): Stop detection flag This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE=0.
0x40005418 C   FIELD 06w01 TC (ro): Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE=0.
0x40005418 C   FIELD 07w01 TCR (ro): Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE=0. This flag is only for master mode, or for slave mode when the SBC bit is set.
0x40005418 C   FIELD 08w01 BERR (ro): Bus error This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE=0.
0x40005418 C   FIELD 09w01 ARLO (ro): Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE=0.
0x40005418 C   FIELD 10w01 OVR (ro): Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE=0.
0x40005418 C   FIELD 11w01 PECERR (ro): PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to .
0x40005418 C   FIELD 12w01 TIMEOUT (ro): Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to .
0x40005418 C   FIELD 13w01 ALERT (ro): SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to .
0x40005418 C   FIELD 15w01 BUSY (ro): Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected, or when PE=0.
0x40005418 C   FIELD 16w01 DIR (ro): Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1).
0x40005418 C   FIELD 17w07 ADDCODE (ro): Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address.
0x4000541C B  REGISTER ICR: I2C interrupt clear register
0x4000541C C   FIELD 03w01 ADDRCF (wo): Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register.
0x4000541C C   FIELD 04w01 NACKCF (wo): Not Acknowledge flag clear Writing 1 to this bit clears the NACKF flag in I2C_ISR register.
0x4000541C C   FIELD 05w01 STOPCF (wo): STOP detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register.
0x4000541C C   FIELD 08w01 BERRCF (wo): Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register.
0x4000541C C   FIELD 09w01 ARLOCF (wo): Arbitration lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register.
0x4000541C C   FIELD 10w01 OVRCF (wo): Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register.
0x4000541C C   FIELD 11w01 PECCF (wo): PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to .
0x4000541C C   FIELD 12w01 TIMOUTCF (wo): Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to .
0x4000541C C   FIELD 13w01 ALERTCF (wo): Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to .
0x40005420 B  REGISTER PECR: I2C PEC register
0x40005420 C   FIELD 00w08 PEC (ro): Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE=0.
0x40005424 B  REGISTER RXDR: I2C receive data register
0x40005424 C   FIELD 00w08 RXDATA (ro): 8-bit receive data Data byte received from the I2C bus
0x40005428 B  REGISTER TXDR: I2C transmit data register
0x40005428 C   FIELD 00w08 TXDATA (rw): 8-bit transmit data Data byte to be transmitted to the I2C bus Note: These bits can be written only when TXE=1.
0x40007000 A PERIPHERAL PWR
0x40007000 B  REGISTER CR1: PWR control register 1
0x40007000 C   FIELD 00w03 LPMS (rw): Low-power mode selection These bits select the low-power mode entered when CPU enters deepsleep mode. 1XX: Shutdown mode
0x40007000 C   FIELD 03w01 FPD_STOP (rw): Flash memory powered down during Stop mode This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode.
0x40007000 C   FIELD 05w01 FPD_SLP (rw): Flash memory powered down during Sleep mode This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Sleep mode.
0x40007008 B  REGISTER CR3: PWR control register 3
0x40007008 C   FIELD 00w01 EWUP1 (rw): Enable WKUP1 wakeup pin When this bit is set, the WKUP1 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit of the PWR_CR4 register.
0x40007008 C   FIELD 01w01 EWUP2 (rw): Enable WKUP2 wakeup pin When this bit is set, the WKUP2 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit of the PWR_CR4 register.
0x40007008 C   FIELD 02w01 EWUP3 (rw): Enable WKUP3 wakeup pin When this bit is set, the WKUP3 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit of the PWR_CR4 register.
0x40007008 C   FIELD 03w01 EWUP4 (rw): Enable WKUP4 wakeup pin When this bit is set, the WKUP4 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register.
0x40007008 C   FIELD 05w01 EWUP6 (rw): Enable WKUP6 wakeup pin When this bit is set, the WKUP6 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured through WP6 bit in the PWR_CR4 register.
0x40007008 C   FIELD 10w01 APC (rw): Apply pull-up and pull-down configuration This bit determines whether the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied.
0x40007008 C   FIELD 15w01 EIWUL (rw): Enable internal wakeup line When set, a rising edge on the internal wakeup line triggers a wakeup event.
0x4000700C B  REGISTER CR4: PWR control register 4
0x4000700C C   FIELD 00w01 WP1 (rw): WKUP1 wakeup pin polarity WKUP1 external wakeup signal polarity (level or edge) to generate wakeup condition:
0x4000700C C   FIELD 01w01 WP2 (rw): WKUP2 wakeup pin polarity WKUP2 external wakeup signal polarity (level or edge) to generate wakeup condition:
0x4000700C C   FIELD 02w01 WP3 (rw): WKUP3 wakeup pin polarity WKUP3 external wakeup signal polarity (level or edge) to generate wakeup condition:
0x4000700C C   FIELD 03w01 WP4 (rw): WKUP4 wakeup pin polarity WKUP4 external wakeup signal polarity (level or edge) to generate wakeup condition:
0x4000700C C   FIELD 05w01 WP6 (rw): WKUP6 wakeup pin polarity WKUP6 external wakeup signal polarity (level or edge) to generate wakeup condition:
0x40007010 B  REGISTER SR1: PWR status register 1
0x40007010 C   FIELD 00w01 WUF1 (ro): Wakeup flag 1 This bit is set when a wakeup condition is detected on WKUP1 wakeup pin. It is cleared by setting the CWUF1 bit of the PWR_SCR register.
0x40007010 C   FIELD 01w01 WUF2 (ro): Wakeup flag 2 This bit is set when a wakeup condition is detected on WKUP2 wakeup pin. It is cleared by setting the CWUF2 bit of the PWR_SCR register.
0x40007010 C   FIELD 02w01 WUF3 (ro): Wakeup flag 3 This bit is set when a wakeup condition is detected on WKUP3 wakeup pin. It is cleared by setting the CWUF3 bit of the PWR_SCR register.
0x40007010 C   FIELD 03w01 WUF4 (ro): Wakeup flag 4 This bit is set when a wakeup condition is detected on WKUP4 wakeup pin. It is cleared by setting the CWUF4 bit of the PWR_SCR register.
0x40007010 C   FIELD 05w01 WUF6 (ro): Wakeup flag 6 This bit is set when a wakeup condition is detected on WKUP6 wakeup pin. It is cleared by setting the CWUF6 bit of the PWR_SCR register.
0x40007010 C   FIELD 08w01 SBF (ro): Standby/Shutdown flag This bit is set by hardware when the device enters Standby or Shutdown mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset.
0x40007010 C   FIELD 15w01 WUFI (ro): Wakeup flag internal This bit is set when a wakeup condition is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared.
0x40007014 B  REGISTER SR2: PWR status register 2
0x40007014 C   FIELD 07w01 FLASH_RDY (ro): Flash ready flag This bit is set by hardware to indicate when the Flash memory is ready to be accessed after wakeup from power-down. To place the Flash memory in power-down, set either FPD_SLP or FPD_STP bit. Note: If the system boots from SRAM, the user application must wait till FLASH_RDY bit is set, prior to jumping to Flash memory.
0x40007018 B  REGISTER SCR: PWR status clear register
0x40007018 C   FIELD 00w01 CWUF1 (wo): Clear wakeup flag 1 Setting this bit clears the WUF1 flag in the PWR_SR1 register.
0x40007018 C   FIELD 01w01 CWUF2 (wo): Clear wakeup flag 2 Setting this bit clears the WUF2 flag in the PWR_SR1 register.
0x40007018 C   FIELD 02w01 CWUF3 (wo): Clear wakeup flag 3 Setting this bit clears the WUF3 flag in the PWR_SR1 register.
0x40007018 C   FIELD 03w01 CWUF4 (wo): Clear wakeup flag 4 Setting this bit clears the WUF4 flag in the PWR_SR1 register.
0x40007018 C   FIELD 05w01 CWUF6 (wo): Clear wakeup flag 6 Setting this bit clears the WUF6 flag in the PWR_SR1 register.
0x40007018 C   FIELD 08w01 CSBF (wo): Clear standby flag Setting this bit clears the SBF flag in the PWR_SR1 register.
0x40007020 B  REGISTER PUCRA: PWR Port A pull-up control register
0x40007020 C   FIELD 00w01 PU0 (rw): Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O.
0x40007020 C   FIELD 01w01 PU1 (rw): Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O.
0x40007020 C   FIELD 02w01 PU2 (rw): Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O.
0x40007020 C   FIELD 03w01 PU3 (rw): Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O.
0x40007020 C   FIELD 04w01 PU4 (rw): Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O.
0x40007020 C   FIELD 05w01 PU5 (rw): Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O.
0x40007020 C   FIELD 06w01 PU6 (rw): Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O.
0x40007020 C   FIELD 07w01 PU7 (rw): Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O.
0x40007020 C   FIELD 08w01 PU8 (rw): Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O.
0x40007020 C   FIELD 09w01 PU9 (rw): Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O.
0x40007020 C   FIELD 10w01 PU10 (rw): Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O.
0x40007020 C   FIELD 11w01 PU11 (rw): Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O.
0x40007020 C   FIELD 12w01 PU12 (rw): Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O.
0x40007020 C   FIELD 13w01 PU13 (rw): Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O.
0x40007020 C   FIELD 14w01 PU14 (rw): Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O.
0x40007020 C   FIELD 15w01 PU15 (rw): Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O.
0x40007024 B  REGISTER PDCRA: PWR Port A pull-down control register
0x40007024 C   FIELD 00w01 PD0 (rw): Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O.
0x40007024 C   FIELD 01w01 PD1 (rw): Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O.
0x40007024 C   FIELD 02w01 PD2 (rw): Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O.
0x40007024 C   FIELD 03w01 PD3 (rw): Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O.
0x40007024 C   FIELD 04w01 PD4 (rw): Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O.
0x40007024 C   FIELD 05w01 PD5 (rw): Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O.
0x40007024 C   FIELD 06w01 PD6 (rw): Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O.
0x40007024 C   FIELD 07w01 PD7 (rw): Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O.
0x40007024 C   FIELD 08w01 PD8 (rw): Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O.
0x40007024 C   FIELD 09w01 PD9 (rw): Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O.
0x40007024 C   FIELD 10w01 PD10 (rw): Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O.
0x40007024 C   FIELD 11w01 PD11 (rw): Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O.
0x40007024 C   FIELD 12w01 PD12 (rw): Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O.
0x40007024 C   FIELD 13w01 PD13 (rw): Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O.
0x40007024 C   FIELD 14w01 PD14 (rw): Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O.
0x40007024 C   FIELD 15w01 PD15 (rw): Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O.
0x40007028 B  REGISTER PUCRB: PWR Port B pull-up control register
0x40007028 C   FIELD 06w01 PU6 (rw): Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available
0x40007028 C   FIELD 07w01 PU7 (rw): Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available
0x4000702C B  REGISTER PDCRB: PWR Port B pull-down control register
0x4000702C C   FIELD 06w01 PD6 (rw): Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available
0x4000702C C   FIELD 07w01 PD7 (rw): Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available
0x40007030 B  REGISTER PUCRC: PWR Port C pull-up control register
0x40007030 C   FIELD 14w01 PU14 (rw): Port C pull-up bit i (i = 15 to 13, 7 to 6) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. On STM32C011xx, only PU15 and PU14 are available
0x40007030 C   FIELD 15w01 PU15 (rw): Port C pull-up bit i (i = 15 to 13, 7 to 6) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. On STM32C011xx, only PU15 and PU14 are available
0x40007034 B  REGISTER PDCRC: PWR Port C pull-down control register
0x40007034 C   FIELD 14w01 PD14 (rw): Port C pull-down bit i (i = 15, 14, 13, 7, 6) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. On STM32C011xx, only PD15 and PD14 are available.
0x40007034 C   FIELD 15w01 PD15 (rw): Port C pull-down bit i (i = 15, 14, 13, 7, 6) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. On STM32C011xx, only PD15 and PD14 are available.
0x40007038 B  REGISTER PUCRD: PWR Port D pull-up control register
0x40007038 C   FIELD 00w01 PU0 (rw): Port D pull-up bit i (i = 3 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O.
0x40007038 C   FIELD 01w01 PU1 (rw): Port D pull-up bit i (i = 3 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O.
0x40007038 C   FIELD 02w01 PU2 (rw): Port D pull-up bit i (i = 3 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O.
0x40007038 C   FIELD 03w01 PU3 (rw): Port D pull-up bit i (i = 3 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O.
0x4000703C B  REGISTER PDCRD: PWR Port D pull-down control register
0x4000703C C   FIELD 00w01 PD0 (rw): Port D pull-down bit i (i = 3 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O.
0x4000703C C   FIELD 01w01 PD1 (rw): Port D pull-down bit i (i = 3 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O.
0x4000703C C   FIELD 02w01 PD2 (rw): Port D pull-down bit i (i = 3 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O.
0x4000703C C   FIELD 03w01 PD3 (rw): Port D pull-down bit i (i = 3 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O.
0x40007048 B  REGISTER PUCRF: PWR Port F pull-up control register
0x40007048 C   FIELD 02w01 PU2 (rw): Port F pull-up bit i (i = 2 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PF[i] I/O. On STM32C011xx, only PU2 is available.
0x4000704C B  REGISTER PDCRF: PWR Port F pull-down control register
0x4000704C C   FIELD 02w01 PD2 (rw): Port F pull-down bit i (i = 2 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PF[i] I/O. On STM32C011xx, only PD2 is available.
0x40010000 A PERIPHERAL SYSCFG
0x40010000 B  REGISTER CFGR1: SYSCFG configuration register 1
0x40010000 C   FIELD 00w02 MEM_MODE (rw): Memory mapping selection bits This bitfield controlled by software selects the memory internally mapped at the address 0x0000 0000. Its reset value is determined by the boot mode configuration. Refer to for more details. x0: Main Flash memory
0x40010000 C   FIELD 03w01 PA11_RMP (rw): PA11 pin remapping This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port.
0x40010000 C   FIELD 04w01 PA12_RMP (rw): PA12 pin remapping This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port.
0x40010000 C   FIELD 05w01 IR_POL (rw): IR output polarity selection
0x40010000 C   FIELD 06w02 IR_MOD (rw): IR Modulation Envelope signal selection This bitfield selects the signal for IR modulation envelope:
0x40010000 C   FIELD 16w01 I2C_PB6_FMP (rw): Fast Mode Plus (FM+) enable for PB6 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB6 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored.
0x40010000 C   FIELD 17w01 I2C_PB7_FMP (rw): Fast Mode Plus (FM+) enable for PB7 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB7 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored.
0x40010000 C   FIELD 18w01 I2C_PB8_FMP (rw): Fast Mode Plus (FM+) enable for PB8 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB8 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored.
0x40010000 C   FIELD 19w01 I2C_PB9_FMP (rw): Fast Mode Plus (FM+) enable for PB9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored.
0x40010000 C   FIELD 20w01 I2C1_FMP (rw): Fast Mode Plus (FM+) enable for I2C1 This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports configured as I2C1 through GPIOx_AFR registers. With this bit in disable state, the I2C FM+ driving capability on I/O ports configured as I2C1 can be enabled through their corresponding I2Cx_FMP bit. When I2C FM+ is enabled, the speed control is ignored.
0x40010000 C   FIELD 22w01 I2C_PA9_FMP (rw): Fast Mode Plus (FM+) enable for PA9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored.
0x40010000 C   FIELD 23w01 I2C_PA10_FMP (rw): Fast Mode Plus (FM+) enable for PA10 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA10 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored.
0x40010000 C   FIELD 24w01 I2C_PC14_FMP (rw): Fast Mode Plus (FM+) enable for PC14 This bit is set and cleared by software. It enables I2C FM+ driving capability on PC14 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored.
0x40010018 B  REGISTER CFGR2: SYSCFG configuration register 2
0x40010018 C   FIELD 00w01 LOCKUP_LOCK (rw): Cortex<Superscript><Default Font>-M0+ LOCKUP enable This bit is set by software and cleared by system reset. When set, it enables the connection of Cortex<Superscript><Default Font>-M0+ LOCKUP (HardFault) output to the TIM1/16/17 Break input.
0x4001003C B  REGISTER CFGR3: SYSCFG configuration register 3
0x4001003C C   FIELD 00w02 PINMUX0 (rw): Pin GPIO multiplexer 0 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved Pin F2 of WLCSP14 package GPIO assignment 1x: Reserved
0x4001003C C   FIELD 02w02 PINMUX1 (rw): Pin GPIO multiplexer 1 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved
0x4001003C C   FIELD 04w02 PINMUX2 (rw): Pin GPIO multiplexer 2 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved 1x: Reserved
0x4001003C C   FIELD 06w02 PINMUX3 (rw): Pin GPIO multiplexer 3 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved
0x4001003C C   FIELD 08w02 PINMUX4 (rw): Pin GPIO multiplexer 4 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved 1x: Reserved
0x4001003C C   FIELD 10w02 PINMUX5 (rw): Pin GPIO multiplexer 5 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved
0x40010080 B  REGISTER ITLINE0: SYSCFG interrupt line 0 status register
0x40010080 C   FIELD 00w01 WWDG (ro): Window watchdog interrupt pending flag
0x40010088 B  REGISTER ITLINE2: SYSCFG interrupt line 2 status register
0x40010088 C   FIELD 01w01 RTC (ro): RTC interrupt request pending (EXTI line 19)
0x4001008C B  REGISTER ITLINE3: SYSCFG interrupt line 3 status register
0x4001008C C   FIELD 01w01 FLASH_ITF (ro): Flash interface interrupt request pending
0x40010090 B  REGISTER ITLINE4: SYSCFG interrupt line 4 status register
0x40010090 C   FIELD 00w01 RCC (ro): Reset and clock control interrupt request pending
0x40010094 B  REGISTER ITLINE5: SYSCFG interrupt line 5 status register
0x40010094 C   FIELD 00w01 EXTI0 (ro): EXTI line 0 interrupt request pending
0x40010094 C   FIELD 01w01 EXTI1 (ro): EXTI line 1 interrupt request pending
0x40010098 B  REGISTER ITLINE6: SYSCFG interrupt line 6 status register
0x40010098 C   FIELD 00w01 EXTI2 (ro): EXTI line 2 interrupt request pending
0x40010098 C   FIELD 01w01 EXTI3 (ro): EXTI line 3 interrupt request pending
0x4001009C B  REGISTER ITLINE7: SYSCFG interrupt line 7 status register
0x4001009C C   FIELD 00w01 EXTI4 (ro): EXTI line 4 interrupt request pending
0x4001009C C   FIELD 01w01 EXTI5 (ro): EXTI line 5 interrupt request pending
0x4001009C C   FIELD 02w01 EXTI6 (ro): EXTI line 6 interrupt request pending
0x4001009C C   FIELD 03w01 EXTI7 (ro): EXTI line 7 interrupt request pending
0x4001009C C   FIELD 04w01 EXTI8 (ro): EXTI line 8 interrupt request pending
0x4001009C C   FIELD 05w01 EXTI9 (ro): EXTI line 9 interrupt request pending
0x4001009C C   FIELD 06w01 EXTI10 (ro): EXTI line 10 interrupt request pending
0x4001009C C   FIELD 07w01 EXTI11 (ro): EXTI line 11 interrupt request pending
0x4001009C C   FIELD 08w01 EXTI12 (ro): EXTI line 12 interrupt request pending
0x4001009C C   FIELD 09w01 EXTI13 (ro): EXTI line 13 interrupt request pending
0x4001009C C   FIELD 10w01 EXTI14 (ro): EXTI line 14 interrupt request pending
0x4001009C C   FIELD 11w01 EXTI15 (ro): EXTI line 15 interrupt request pending
0x400100A4 B  REGISTER ITLINE9: SYSCFG interrupt line 9 status register
0x400100A4 C   FIELD 00w01 DMA1_CH1 (ro): DMA1 channel 1interrupt request pending
0x400100A8 B  REGISTER ITLINE10: SYSCFG interrupt line 10 status register
0x400100A8 C   FIELD 00w01 DMA1_CH2 (ro): DMA1 channel 2 interrupt request pending
0x400100A8 C   FIELD 01w01 DMA1_CH3 (ro): DMA1 channel 3 interrupt request pending
0x400100AC B  REGISTER ITLINE11: SYSCFG interrupt line 11 status register
0x400100AC C   FIELD 00w01 DMAMUX (ro): DMAMUX interrupt request pending
0x400100B0 B  REGISTER ITLINE12: SYSCFG interrupt line 12 status register
0x400100B0 C   FIELD 00w01 ADC (ro): ADC interrupt request pending
0x400100B4 B  REGISTER ITLINE13: SYSCFG interrupt line 13 status register
0x400100B4 C   FIELD 00w01 TIM1_CCU (ro): Timer 1 commutation interrupt request pending
0x400100B4 C   FIELD 01w01 TIM1_TRG (ro): Timer 1 trigger interrupt request pending
0x400100B4 C   FIELD 02w01 TIM1_UPD (ro): Timer 1 update interrupt request pending
0x400100B4 C   FIELD 03w01 TIM1_BRK (ro): Timer 1 break interrupt request pending
0x400100B8 B  REGISTER ITLINE14: SYSCFG interrupt line 14 status register
0x400100B8 C   FIELD 00w01 TIM1_CC (ro): Timer 1 capture compare interrupt request pending
0x400100C0 B  REGISTER ITLINE16: SYSCFG interrupt line 16 status register
0x400100C0 C   FIELD 00w01 TIM3 (ro): Timer 3 interrupt request pending
0x400100CC B  REGISTER ITLINE19: SYSCFG interrupt line 19 status register
0x400100CC C   FIELD 00w01 TIM14 (ro): Timer 14 interrupt request pending
0x400100D4 B  REGISTER ITLINE21: SYSCFG interrupt line 21 status register
0x400100D4 C   FIELD 00w01 TIM16 (ro): Timer 16 interrupt request pending
0x400100D8 B  REGISTER ITLINE22: SYSCFG interrupt line 22 status register
0x400100D8 C   FIELD 00w01 TIM17 (ro): Timer 17 interrupt request pending
0x400100DC B  REGISTER ITLINE23: SYSCFG interrupt line 23 status register
0x400100DC C   FIELD 00w01 I2C1 (ro): I2C1 interrupt request pending, combined with EXTI line 23
0x400100E4 B  REGISTER ITLINE25: SYSCFG interrupt line 25 status register
0x400100E4 C   FIELD 00w01 SPI1 (ro): SPI1 interrupt request pending
0x400100EC B  REGISTER ITLINE27: SYSCFG interrupt line 27 status register
0x400100EC C   FIELD 00w01 USART1 (ro): USART1 interrupt request pending, combined with EXTI line 25
0x400100F0 B  REGISTER ITLINE28: SYSCFG interrupt line 28 status register
0x400100F0 C   FIELD 00w01 USART2 (ro): USART2 interrupt request pending (EXTI line 26)
0x40012400 A PERIPHERAL ADC
0x40012400 B  REGISTER ISR: ADC interrupt and status register
0x40012400 C   FIELD 00w01 ADRDY (rw): ADC ready This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it.
0x40012400 C   FIELD 01w01 EOSMP (rw): End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to 1.
0x40012400 C   FIELD 02w01 EOC (rw): End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.
0x40012400 C   FIELD 03w01 EOS (rw): End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it.
0x40012400 C   FIELD 04w01 OVR (rw): ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it.
0x40012400 C   FIELD 07w01 AWD1 (rw): Analog watchdog 1 flag
0x40012400 C   FIELD 08w01 AWD2 (rw): Analog watchdog 2 flag
0x40012400 C   FIELD 09w01 AWD3 (rw): Analog watchdog 3 flag
0x40012400 C   FIELD 11w01 EOCAL (rw): End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.
0x40012400 C   FIELD 13w01 CCRDY (rw): Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration.
0x40012404 B  REGISTER IER: ADC interrupt enable register
0x40012404 C   FIELD 00w01 ADRDYIE (rw): ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 01w01 EOSMPIE (rw): End of sampling flag interrupt enable This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 02w01 EOCIE (rw): End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 03w01 EOSIE (rw): End of conversion sequence interrupt enable This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 04w01 OVRIE (rw): Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 07w01 AWD1IE (rw): Analog watchdog 1 interrupt enable
0x40012404 C   FIELD 08w01 AWD2IE (rw): Analog watchdog 2 interrupt enable
0x40012404 C   FIELD 09w01 AWD3IE (rw): Analog watchdog 3 interrupt enable
0x40012404 C   FIELD 11w01 EOCALIE (rw): End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 13w01 CCRDYIE (rw): Channel Configuration Ready Interrupt enable This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012408 B  REGISTER CR: ADC control register
0x40012408 C   FIELD 00w01 ADEN (rw): ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, ADSTP = 0, ADSTART = 0, ADDIS = 0 and ADEN = 0)
0x40012408 C   FIELD 01w01 ADDIS (rw): ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to 1 is only effective when ADEN = 1 and ADSTART = 0 (which ensures that no conversion is ongoing)
0x40012408 C   FIELD 02w01 ADSTART (rw): ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT = 0, DISCEN = 0), when software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT = 0, DISCEN = 1), when the software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored.
0x40012408 C   FIELD 04w01 ADSTP (rw): ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to 1 is only effective when ADSTART = 1 and ADDIS = 0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)
0x40012408 C   FIELD 28w01 ADVREGEN (rw): ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
0x40012408 C   FIELD 31w01 ADCAL (rw): ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 (ADC enabled and no conversion is ongoing).
0x4001240C B  REGISTER CFGR1: ADC configuration register 1
0x4001240C C   FIELD 00w01 DMAEN (rw): Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to . Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 01w01 DMACFG (rw): Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to page 355 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 02w01 SCANDIR (rw): Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared to 0. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x4001240C C   FIELD 03w02 RES (rw): Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADEN = 0.
0x4001240C C   FIELD 05w01 ALIGN (rw): Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Data alignment and resolution (oversampling disabled: OVSE = 0) on page 353 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 06w03 EXTSEL (rw): External trigger selection These bits select the external event used to trigger the start of conversion (refer to External triggers for details): Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 10w02 EXTEN (rw): External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 12w01 OVRMOD (rw): Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 13w01 CONT (rw): Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 14w01 WAIT (rw): Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 15w01 AUTOFF (rw): Auto-off mode This bit is set and cleared by software to enable/disable auto-off mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 16w01 DISCEN (rw): Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 21w01 CHSELRMOD (rw): Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x4001240C C   FIELD 22w01 AWD1SGL (rw): Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 23w01 AWD1EN (rw): Analog watchdog enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 26w05 AWD1CH (rw): Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012410 B  REGISTER CFGR2: ADC configuration register 2
0x40012410 C   FIELD 00w01 OVSE (rw): Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x40012410 C   FIELD 02w03 OVSR (rw): Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x40012410 C   FIELD 05w04 OVSS (rw): Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x40012410 C   FIELD 09w01 TOVS (rw): Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x40012410 C   FIELD 29w01 LFTRIG (rw): Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012410 C   FIELD 30w02 CKMODE (rw): ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
0x40012414 B  REGISTER SMPR: ADC sampling time register
0x40012414 C   FIELD 00w03 SMP1 (rw): Sampling time selection 1
0x40012414 C   FIELD 04w03 SMP2 (rw): Sampling time selection 2
0x40012414 C   FIELD 08w01 SMPSEL0 (rw): Channel-0 sampling time selection
0x40012414 C   FIELD 09w01 SMPSEL1 (rw): Channel-1 sampling time selection
0x40012414 C   FIELD 10w01 SMPSEL2 (rw): Channel-2 sampling time selection
0x40012414 C   FIELD 11w01 SMPSEL3 (rw): Channel-3 sampling time selection
0x40012414 C   FIELD 12w01 SMPSEL4 (rw): Channel-4 sampling time selection
0x40012414 C   FIELD 13w01 SMPSEL5 (rw): Channel-5 sampling time selection
0x40012414 C   FIELD 14w01 SMPSEL6 (rw): Channel-6 sampling time selection
0x40012414 C   FIELD 15w01 SMPSEL7 (rw): Channel-7 sampling time selection
0x40012414 C   FIELD 16w01 SMPSEL8 (rw): Channel-8 sampling time selection
0x40012414 C   FIELD 17w01 SMPSEL9 (rw): Channel-9 sampling time selection
0x40012414 C   FIELD 18w01 SMPSEL10 (rw): Channel-10 sampling time selection
0x40012414 C   FIELD 19w01 SMPSEL11 (rw): Channel-11 sampling time selection
0x40012414 C   FIELD 20w01 SMPSEL12 (rw): Channel-12 sampling time selection
0x40012414 C   FIELD 21w01 SMPSEL13 (rw): Channel-13 sampling time selection
0x40012414 C   FIELD 22w01 SMPSEL14 (rw): Channel-14 sampling time selection
0x40012414 C   FIELD 23w01 SMPSEL15 (rw): Channel-15 sampling time selection
0x40012414 C   FIELD 24w01 SMPSEL16 (rw): Channel-16 sampling time selection
0x40012414 C   FIELD 25w01 SMPSEL17 (rw): Channel-17 sampling time selection
0x40012414 C   FIELD 26w01 SMPSEL18 (rw): Channel-18 sampling time selection
0x40012414 C   FIELD 27w01 SMPSEL19 (rw): Channel-19 sampling time selection
0x40012414 C   FIELD 28w01 SMPSEL20 (rw): Channel-20 sampling time selection
0x40012414 C   FIELD 29w01 SMPSEL21 (rw): Channel-21 sampling time selection
0x40012414 C   FIELD 30w01 SMPSEL22 (rw): Channel-22 sampling time selection
0x40012420 B  REGISTER AWD1TR: ADC watchdog threshold register
0x40012420 C   FIELD 00w12 LT1 (rw): Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359.
0x40012420 C   FIELD 16w12 HT1 (rw): Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359.
0x40012424 B  REGISTER AWD2TR: ADC watchdog threshold register
0x40012424 C   FIELD 00w12 LT2 (rw): Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359.
0x40012424 C   FIELD 16w12 HT2 (rw): Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359.
0x40012428 B  REGISTER CHSELR0: ADC channel selection register [alternate]
0x40012428 B  REGISTER CHSELR1: ADC channel selection register [alternate]
0x40012428 C   FIELD 00w01 CHSEL0 (rw): Channel-0 selection
0x40012428 C   FIELD 00w04 SQ1 (rw): 1 conversion of the sequence
0x40012428 C   FIELD 01w01 CHSEL1 (rw): Channel-1 selection
0x40012428 C   FIELD 02w01 CHSEL2 (rw): Channel-2 selection
0x40012428 C   FIELD 03w01 CHSEL3 (rw): Channel-3 selection
0x40012428 C   FIELD 04w01 CHSEL4 (rw): Channel-4 selection
0x40012428 C   FIELD 04w04 SQ2 (rw): 2 conversion of the sequence
0x40012428 C   FIELD 05w01 CHSEL5 (rw): Channel-5 selection
0x40012428 C   FIELD 06w01 CHSEL6 (rw): Channel-6 selection
0x40012428 C   FIELD 07w01 CHSEL7 (rw): Channel-7 selection
0x40012428 C   FIELD 08w01 CHSEL8 (rw): Channel-8 selection
0x40012428 C   FIELD 08w04 SQ3 (rw): 3 conversion of the sequence
0x40012428 C   FIELD 09w01 CHSEL9 (rw): Channel-9 selection
0x40012428 C   FIELD 10w01 CHSEL10 (rw): Channel-10 selection
0x40012428 C   FIELD 11w01 CHSEL11 (rw): Channel-11 selection
0x40012428 C   FIELD 12w01 CHSEL12 (rw): Channel-12 selection
0x40012428 C   FIELD 12w04 SQ4 (rw): 4 conversion of the sequence
0x40012428 C   FIELD 13w01 CHSEL13 (rw): Channel-13 selection
0x40012428 C   FIELD 14w01 CHSEL14 (rw): Channel-14 selection
0x40012428 C   FIELD 15w01 CHSEL15 (rw): Channel-15 selection
0x40012428 C   FIELD 16w01 CHSEL16 (rw): Channel-16 selection
0x40012428 C   FIELD 16w04 SQ5 (rw): 5 conversion of the sequence
0x40012428 C   FIELD 17w01 CHSEL17 (rw): Channel-17 selection
0x40012428 C   FIELD 18w01 CHSEL18 (rw): Channel-18 selection
0x40012428 C   FIELD 19w01 CHSEL19 (rw): Channel-19 selection
0x40012428 C   FIELD 20w01 CHSEL20 (rw): Channel-20 selection
0x40012428 C   FIELD 20w04 SQ6 (rw): 6 conversion of the sequence
0x40012428 C   FIELD 21w01 CHSEL21 (rw): Channel-21 selection
0x40012428 C   FIELD 22w01 CHSEL22 (rw): Channel-22 selection
0x40012428 C   FIELD 24w04 SQ7 (rw): 7 conversion of the sequence
0x40012428 C   FIELD 28w04 SQ8 (rw): 8 conversion of the sequence
0x4001242C B  REGISTER AWD3TR: ADC watchdog threshold register
0x4001242C C   FIELD 00w12 LT3 (rw): Analog watchdog 3lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359.
0x4001242C C   FIELD 16w12 HT3 (rw): Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359.
0x40012440 B  REGISTER DR: ADC data register
0x40012440 C   FIELD 00w16 DATA (ro): Converted data These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in OVSE = 0) on page 353. Just after a calibration is complete, DATA[6:0] contains the calibration factor.
0x400124A0 B  REGISTER AWD2CR: ADC Analog Watchdog 2 Configuration register
0x400124A0 C   FIELD 00w01 AWD2CH0 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 01w01 AWD2CH1 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 02w01 AWD2CH2 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 03w01 AWD2CH3 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 04w01 AWD2CH4 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 05w01 AWD2CH5 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 06w01 AWD2CH6 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 07w01 AWD2CH7 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 08w01 AWD2CH8 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 09w01 AWD2CH9 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 10w01 AWD2CH10 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 11w01 AWD2CH11 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 12w01 AWD2CH12 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 13w01 AWD2CH13 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 14w01 AWD2CH14 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 15w01 AWD2CH15 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 16w01 AWD2CH16 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 17w01 AWD2CH17 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 18w01 AWD2CH18 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 19w01 AWD2CH19 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 20w01 AWD2CH20 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 21w01 AWD2CH21 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 22w01 AWD2CH22 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x400124A4 B  REGISTER AWD3CR: ADC Analog Watchdog 3 Configuration register
0x400124A4 C   FIELD 00w01 AWD3CH0 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 01w01 AWD3CH1 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 02w01 AWD3CH2 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 03w01 AWD3CH3 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 04w01 AWD3CH4 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 05w01 AWD3CH5 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 06w01 AWD3CH6 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 07w01 AWD3CH7 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 08w01 AWD3CH8 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 09w01 AWD3CH9 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 10w01 AWD3CH10 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 11w01 AWD3CH11 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 12w01 AWD3CH12 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 13w01 AWD3CH13 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 14w01 AWD3CH14 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 15w01 AWD3CH15 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 16w01 AWD3CH16 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 17w01 AWD3CH17 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 18w01 AWD3CH18 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 19w01 AWD3CH19 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 20w01 AWD3CH20 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 21w01 AWD3CH21 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 22w01 AWD3CH22 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124B4 B  REGISTER CALFACT: ADC Calibration factor
0x400124B4 C   FIELD 00w07 CALFACT (rw): Calibration factor These bits are written by hardware or by software. Once a calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new calibration is launched. Just after a calibration is complete, DATA[6:0] contains the calibration factor. Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). Refer to SQ8[3:0] for a definition of channel selection.
0x40012708 B  REGISTER CCR: ADC common configuration register
0x40012708 C   FIELD 18w04 PRESC (rw): ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
0x40012708 C   FIELD 22w01 VREFEN (rw): VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x40012708 C   FIELD 23w01 TSEN (rw): Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
0x40012C00 A PERIPHERAL TIM1
0x40012C00 B  REGISTER CR1: TIM1 control register 1
0x40012C00 C   FIELD 00w01 CEN (rw): Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
0x40012C00 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
0x40012C00 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
0x40012C00 C   FIELD 03w01 OPM (rw): One pulse mode
0x40012C00 C   FIELD 04w01 DIR (rw): Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.
0x40012C00 C   FIELD 05w02 CMS (rw): Center-aligned mode selection Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed
0x40012C00 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40012C00 C   FIELD 08w02 CKD (rw): Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx): Note: tDTS = 1/fDTS, tCK_INT = 1/fCK_INT.
0x40012C00 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40012C04 B  REGISTER CR2: TIM1 control register 2
0x40012C04 C   FIELD 00w01 CCPC (rw): Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
0x40012C04 C   FIELD 02w01 CCUS (rw): Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
0x40012C04 C   FIELD 03w01 CCDS (rw): Capture/compare DMA selection
0x40012C04 C   FIELD 04w03 MMS (rw): Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
0x40012C04 C   FIELD 07w01 TI1S (rw): TI1 selection
0x40012C04 C   FIELD 08w01 OIS1 (rw): Output Idle state (OC1 output)
0x40012C04 C   FIELD 09w01 OIS1N (rw): Output Idle state (OC1N output)
0x40012C04 C   FIELD 10w01 OIS2 (rw): Output Idle state (OC2 output)
0x40012C04 C   FIELD 11w01 OIS2N (rw): Output Idle state (OC2N output)
0x40012C04 C   FIELD 12w01 OIS3 (rw): Output Idle state (OC3 output)
0x40012C04 C   FIELD 13w01 OIS3N (rw): Output Idle state (OC3N output)
0x40012C04 C   FIELD 14w01 OIS4 (rw): Output Idle state (OC4 output)
0x40012C04 C   FIELD 16w01 OIS5 (rw): Output Idle state (OC5 output)
0x40012C04 C   FIELD 18w01 OIS6 (rw): Output Idle state (OC6 output)
0x40012C04 C   FIELD 20w04 MMS2 (rw): Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
0x40012C08 B  REGISTER SMCR: TIM1 slave mode control register
0x40012C08 C   FIELD 00w03 SMS (rw): Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0x40012C08 C   FIELD 03w01 OCCS (rw): OCREF clear selection This bit is used to select the OCREF clear source.
0x40012C08 C   FIELD 04w03 TS (rw): Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
0x40012C08 C   FIELD 07w01 MSM (rw): Master/slave mode
0x40012C08 C   FIELD 08w04 ETF (rw): External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
0x40012C08 C   FIELD 12w02 ETPS (rw): External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
0x40012C08 C   FIELD 14w01 ECE (rw): External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
0x40012C08 C   FIELD 15w01 ETP (rw): External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
0x40012C08 C   FIELD 16w01 SMS_3 (rw): Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0x40012C08 C   FIELD 20w02 TS2 (rw): Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
0x40012C0C B  REGISTER DIER: TIM1 DMA/interrupt enable register
0x40012C0C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x40012C0C C   FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x40012C0C C   FIELD 02w01 CC2IE (rw): Capture/Compare 2 interrupt enable
0x40012C0C C   FIELD 03w01 CC3IE (rw): Capture/Compare 3 interrupt enable
0x40012C0C C   FIELD 04w01 CC4IE (rw): Capture/Compare 4 interrupt enable
0x40012C0C C   FIELD 05w01 COMIE (rw): COM interrupt enable
0x40012C0C C   FIELD 06w01 TIE (rw): Trigger interrupt enable
0x40012C0C C   FIELD 07w01 BIE (rw): Break interrupt enable
0x40012C0C C   FIELD 08w01 UDE (rw): Update DMA request enable
0x40012C0C C   FIELD 09w01 CC1DE (rw): Capture/Compare 1 DMA request enable
0x40012C0C C   FIELD 10w01 CC2DE (rw): Capture/Compare 2 DMA request enable
0x40012C0C C   FIELD 11w01 CC3DE (rw): Capture/Compare 3 DMA request enable
0x40012C0C C   FIELD 12w01 CC4DE (rw): Capture/Compare 4 DMA request enable
0x40012C0C C   FIELD 13w01 COMDE (rw): COM DMA request enable
0x40012C0C C   FIELD 14w01 TDE (rw): Trigger DMA request enable
0x40012C10 B  REGISTER SR: TIM1 status register
0x40012C10 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)N/A), if URS=0 and UDIS=0 in the TIMx_CR1 register.
0x40012C10 C   FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag
0x40012C10 C   FIELD 02w01 CC2IF (rw): Capture/compare 2 interrupt flag
0x40012C10 C   FIELD 03w01 CC3IF (rw): Capture/compare 3 interrupt flag
0x40012C10 C   FIELD 04w01 CC4IF (rw): Capture/compare 4 interrupt flag
0x40012C10 C   FIELD 05w01 COMIF (rw): COM interrupt flag
0x40012C10 C   FIELD 06w01 TIF (rw): Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
0x40012C10 C   FIELD 07w01 BIF (rw): Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
0x40012C10 C   FIELD 08w01 B2IF (rw): Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active.
0x40012C10 C   FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag
0x40012C10 C   FIELD 10w01 CC2OF (rw): Capture/Compare 2 overcapture flag
0x40012C10 C   FIELD 11w01 CC3OF (rw): Capture/Compare 3 overcapture flag
0x40012C10 C   FIELD 12w01 CC4OF (rw): Capture/Compare 4 overcapture flag
0x40012C10 C   FIELD 13w01 SBIF (rw): System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation.
0x40012C10 C   FIELD 16w01 CC5IF (rw): Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output)
0x40012C10 C   FIELD 17w01 CC6IF (rw): Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output)
0x40012C14 B  REGISTER EGR: TIM1 event generation register
0x40012C14 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40012C14 C   FIELD 01w01 CC1G (wo): Capture/compare 1 generation
0x40012C14 C   FIELD 02w01 CC2G (wo): Capture/compare 2 generation
0x40012C14 C   FIELD 03w01 CC3G (wo): Capture/compare 3 generation
0x40012C14 C   FIELD 04w01 CC4G (wo): Capture/compare 4 generation
0x40012C14 C   FIELD 05w01 COMG (wo): Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output.
0x40012C14 C   FIELD 06w01 TG (wo): Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40012C14 C   FIELD 07w01 BG (wo): Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40012C14 C   FIELD 08w01 B2G (wo): Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40012C18 B  REGISTER CCMR1_Input: TIM1 capture/compare mode register 1 [alternate]
0x40012C18 B  REGISTER CCMR1_Output: TIM1 capture/compare mode register 1 [alternate]
0x40012C18 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
0x40012C18 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40012C18 C   FIELD 02w01 OC1FE (rw): Output compare 1 fast enable
0x40012C18 C   FIELD 02w02 IC1PSC (rw): Input capture 1 prescaler
0x40012C18 C   FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40012C18 C   FIELD 04w03 OC1M (rw): Output compare 1 mode
0x40012C18 C   FIELD 04w04 IC1F (rw): Input capture 1 filter
0x40012C18 C   FIELD 07w01 OC1CE (rw): Output compare 1 clear enable
0x40012C18 C   FIELD 08w02 CC2S (rw): Capture/Compare 2 selection
0x40012C18 C   FIELD 08w02 CC2S (rw): Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
0x40012C18 C   FIELD 10w01 OC2FE (rw): Output compare 2 fast enable
0x40012C18 C   FIELD 10w02 IC2PSC (rw): Input capture 2 prescaler
0x40012C18 C   FIELD 11w01 OC2PE (rw): Output compare 2 preload enable
0x40012C18 C   FIELD 12w03 OC2M (rw): Output compare 2 mode
0x40012C18 C   FIELD 12w04 IC2F (rw): Input capture 2 filter
0x40012C18 C   FIELD 15w01 OC2CE (rw): Output compare 2 clear enable
0x40012C18 C   FIELD 16w01 OC1M_3 (rw): Output compare 1 mode, bit 3
0x40012C18 C   FIELD 24w01 OC2M_3 (rw): Output compare 2 mode, bit 3
0x40012C1C B  REGISTER CCMR2_Input: TIM1 capture/compare mode register 2 [alternate]
0x40012C1C B  REGISTER CCMR2_Output: TIM1 capture/compare mode register 2 [alternate]
0x40012C1C C   FIELD 00w02 CC3S (=TIM1.CCMR1_Output.CC%sS) (rw): Capture/Compare 3 selection
0x40012C1C C   FIELD 00w02 CC3S (rw): Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
0x40012C1C C   FIELD 02w01 OC3FE (=TIM1.CCMR1_Output.OC%sFE) (rw): Output compare 3 fast enable
0x40012C1C C   FIELD 02w02 IC3PSC (=TIM1.CCMR1_Input.IC%sPSC) (rw): Input capture 3 prescaler
0x40012C1C C   FIELD 03w01 OC3PE (=TIM1.CCMR1_Output.OC%sPE) (rw): Output compare 3 preload enable
0x40012C1C C   FIELD 04w03 OC3M (=TIM1.CCMR1_Output.OC%sM) (rw): Output compare 3 mode
0x40012C1C C   FIELD 04w04 IC3F (=TIM1.CCMR1_Input.IC%sF) (rw): Input capture 3 filter
0x40012C1C C   FIELD 07w01 OC3CE (=TIM1.CCMR1_Output.OC%sCE) (rw): Output compare 3 clear enable
0x40012C1C C   FIELD 08w02 CC4S (=TIM1.CCMR1_Output.CC%sS) (rw): Capture/Compare 4 selection
0x40012C1C C   FIELD 08w02 CC4S (rw): Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
0x40012C1C C   FIELD 10w01 OC4FE (=TIM1.CCMR1_Output.OC%sFE) (rw): Output compare 4 fast enable
0x40012C1C C   FIELD 10w02 IC4PSC (=TIM1.CCMR1_Input.IC%sPSC) (rw): Input capture 4 prescaler
0x40012C1C C   FIELD 11w01 OC4PE (=TIM1.CCMR1_Output.OC%sPE) (rw): Output compare 4 preload enable
0x40012C1C C   FIELD 12w03 OC4M (=TIM1.CCMR1_Output.OC%sM) (rw): Output compare 4 mode
0x40012C1C C   FIELD 12w04 IC4F (=TIM1.CCMR1_Input.IC%sF) (rw): Input capture 4 filter
0x40012C1C C   FIELD 15w01 OC4CE (=TIM1.CCMR1_Output.OC%sCE) (rw): Output compare 4 clear enable
0x40012C1C C   FIELD 16w01 OC3M_3 (=TIM1.CCMR1_Output.OC%sM_3) (rw): Output compare 3 mode, bit 3
0x40012C1C C   FIELD 24w01 OC4M_3 (=TIM1.CCMR1_Output.OC%sM_3) (rw): Output compare 4 mode, bit 3
0x40012C20 B  REGISTER CCER: TIM1 capture/compare enable register
0x40012C20 C   FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable
0x40012C20 C   FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity
0x40012C20 C   FIELD 02w01 CC1NE (rw): Capture/Compare 1 complementary output enable
0x40012C20 C   FIELD 03w01 CC1NP (rw): Capture/Compare 1 output Polarity
0x40012C20 C   FIELD 04w01 CC2E (rw): Capture/Compare 2 output enable
0x40012C20 C   FIELD 05w01 CC2P (rw): Capture/Compare 2 output Polarity
0x40012C20 C   FIELD 06w01 CC2NE (rw): Capture/Compare 2 complementary output enable
0x40012C20 C   FIELD 07w01 CC2NP (rw): Capture/Compare 2 output Polarity
0x40012C20 C   FIELD 08w01 CC3E (rw): Capture/Compare 3 output enable
0x40012C20 C   FIELD 09w01 CC3P (rw): Capture/Compare 3 output Polarity
0x40012C20 C   FIELD 10w01 CC3NE (rw): Capture/Compare 3 complementary output enable
0x40012C20 C   FIELD 11w01 CC3NP (rw): Capture/Compare 3 output Polarity
0x40012C20 C   FIELD 12w01 CC4E (rw): Capture/Compare 4 output enable
0x40012C20 C   FIELD 13w01 CC4P (rw): Capture/Compare 4 output Polarity
0x40012C20 C   FIELD 15w01 CC4NP (rw): Capture/Compare 4 output Polarity
0x40012C20 C   FIELD 16w01 CC5E (rw): Capture/Compare 5 output enable
0x40012C20 C   FIELD 17w01 CC5P (rw): Capture/Compare 5 output Polarity
0x40012C20 C   FIELD 20w01 CC6E (rw): Capture/Compare 6 output enable
0x40012C20 C   FIELD 21w01 CC6P (rw): Capture/Compare 6 output Polarity
0x40012C24 B  REGISTER CNT: TIM1 counter
0x40012C24 C   FIELD 00w16 CNT (rw): Counter value
0x40012C24 C   FIELD 31w01 UIFCPY (ro): UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0.
0x40012C28 B  REGISTER PSC: TIM1 prescaler
0x40012C28 C   FIELD 00w16 PSC (rw): Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode).
0x40012C2C B  REGISTER ARR: TIM1 auto-reload register
0x40012C2C C   FIELD 00w16 ARR (rw): Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null.
0x40012C30 B  REGISTER RCR: TIM1 repetition counter register
0x40012C30 C   FIELD 00w16 REP (rw): Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to: the number of PWM periods in edge-aligned mode the number of half PWM period in center-aligned mode.
0x40012C34 B  REGISTER CCR1: capture/compare register
0x40012C34 C   FIELD 00w16 CCR (rw): Capture/Compare value
0x40012C38 B  REGISTER CCR2: capture/compare register
0x40012C38 C   FIELD 00w16 CCR (rw): Capture/Compare value
0x40012C3C B  REGISTER CCR3: capture/compare register
0x40012C3C C   FIELD 00w16 CCR (rw): Capture/Compare value
0x40012C40 B  REGISTER CCR4: capture/compare register
0x40012C40 C   FIELD 00w16 CCR (rw): Capture/Compare value
0x40012C44 B  REGISTER BDTR: TIM1 break and dead-time register
0x40012C44 C   FIELD 00w08 DTG (rw): Dead-time generator setup
0x40012C44 C   FIELD 08w02 LOCK (rw): Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
0x40012C44 C   FIELD 10w01 OSSI (rw): Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C44 C   FIELD 11w01 OSSR (rw): Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C44 C   FIELD 12w01 BKE (rw): Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per ). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40012C44 C   FIELD 13w01 BKP (rw): Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40012C44 C   FIELD 14w01 AOE (rw): Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C44 C   FIELD 15w01 MOE (rw): Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A).
0x40012C44 C   FIELD 16w04 BKF (rw): Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C44 C   FIELD 20w04 BK2F (rw): Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C44 C   FIELD 24w01 BK2E (rw): Break 2 enable Note: The BRK2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40012C44 C   FIELD 25w01 BK2P (rw): Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40012C44 C   FIELD 26w01 BKDSRM (rw): Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40012C44 C   FIELD 27w01 BK2DSRM (rw): Break2 Disarm Refer to BKDSRM description
0x40012C44 C   FIELD 28w01 BKBID (rw): Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40012C44 C   FIELD 29w01 BK2BID (rw): Break2 bidirectional Refer to BKBID description
0x40012C48 B  REGISTER DCR: TIM1 DMA control register
0x40012C48 C   FIELD 00w05 DBA (rw): DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ...
0x40012C48 C   FIELD 08w05 DBL (rw): DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA.
0x40012C4C B  REGISTER DMAR: TIM1 DMA address for full transfer
0x40012C4C C   FIELD 00w32 DMAB (rw): DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
0x40012C54 B  REGISTER CCMR3_Output: TIM1 capture/compare mode register 3
0x40012C54 C   FIELD 02w01 OC5FE (=TIM1.CCMR1_Output.OC%sFE) (rw): Output compare 5 fast enable
0x40012C54 C   FIELD 03w01 OC5PE (=TIM1.CCMR1_Output.OC%sPE) (rw): Output compare 5 preload enable
0x40012C54 C   FIELD 04w03 OC5M (=TIM1.CCMR1_Output.OC%sM) (rw): Output compare 5 mode
0x40012C54 C   FIELD 07w01 OC5CE (=TIM1.CCMR1_Output.OC%sCE) (rw): Output compare 5 clear enable
0x40012C54 C   FIELD 10w01 OC6FE (=TIM1.CCMR1_Output.OC%sFE) (rw): Output compare 6 fast enable
0x40012C54 C   FIELD 11w01 OC6PE (=TIM1.CCMR1_Output.OC%sPE) (rw): Output compare 6 preload enable
0x40012C54 C   FIELD 12w03 OC6M (=TIM1.CCMR1_Output.OC%sM) (rw): Output compare 6 mode
0x40012C54 C   FIELD 15w01 OC6CE (=TIM1.CCMR1_Output.OC%sCE) (rw): Output compare 6 clear enable
0x40012C54 C   FIELD 16w01 OC5M_3 (=TIM1.CCMR1_Output.OC%sM_3) (rw): Output compare 5 mode, bit 3
0x40012C54 C   FIELD 24w01 OC6M_3 (=TIM1.CCMR1_Output.OC%sM_3) (rw): Output compare 6 mode, bit 3
0x40012C58 B  REGISTER CCR5: capture/compare register
0x40012C58 C   FIELD 00w16 CCR (rw): Capture/Compare value
0x40012C58 C   FIELD 29w01 GC5C1 (rw): Group Channel 5 and Channel 1 Distortion on Channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals.
0x40012C58 C   FIELD 30w01 GC5C2 (rw): Group Channel 5 and Channel 2 Distortion on Channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals.
0x40012C58 C   FIELD 31w01 GC5C3 (rw): Group Channel 5 and Channel 3 Distortion on Channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals.
0x40012C5C B  REGISTER CCR6: capture/compare register
0x40012C5C C   FIELD 00w16 CCR (rw): Capture/Compare value
0x40012C60 B  REGISTER AF1: TIM1 alternate function option register 1
0x40012C60 C   FIELD 00w01 BKINE (rw): BRK BKIN input enable This bit enables the BKIN alternate function input for the timers BRK input. BKIN input is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C60 C   FIELD 09w01 BKINP (rw): BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C60 C   FIELD 14w04 ETRSEL (rw): ETR source selection These bits select the ETR input source. Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C64 B  REGISTER AF2: TIM1 Alternate function register 2
0x40012C64 C   FIELD 00w01 BK2INE (rw): BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timers BRK2 input. BKIN2 input is ORed with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C64 C   FIELD 09w01 BK2INP (rw): BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C68 B  REGISTER TISEL: TIM1 timer input selection register
0x40012C68 C   FIELD 00w04 TI1SEL (rw): selects TI1[0] to TI1[15] input Others: Reserved
0x40012C68 C   FIELD 08w04 TI2SEL (rw): selects TI2[0] to TI2[15] input Others: Reserved
0x40012C68 C   FIELD 16w04 TI3SEL (rw): selects TI3[0] to TI3[15] input Others: Reserved
0x40012C68 C   FIELD 24w04 TI4SEL (rw): selects TI4[0] to TI4[15] input Others: Reserved
0x40013000 A PERIPHERAL SPI1
0x40013000 B  REGISTER CR1: SPI control register 1
0x40013000 C   FIELD 00w01 CPHA (rw): Clock phase Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode.
0x40013000 C   FIELD 01w01 CPOL (rw): Clock polarity Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode.
0x40013000 C   FIELD 02w01 MSTR (rw): Master selection Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode.
0x40013000 C   FIELD 03w03 BR (rw): Baud rate control Note: These bits should not be changed when communication is ongoing. These bits are not used in I2S mode.
0x40013000 C   FIELD 06w01 SPE (rw): SPI enable Note: When disabling the SPI, follow the procedure described in SPI on page 1349. This bit is not used in I2S mode.
0x40013000 C   FIELD 07w01 LSBFIRST (rw): Frame format Note: 1. This bit should not be changed when communication is ongoing. 2. This bit is not used in I2S mode and SPI TI mode.
0x40013000 C   FIELD 08w01 SSI (rw): Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. Note: This bit is not used in I2S mode and SPI TI mode.
0x40013000 C   FIELD 09w01 SSM (rw): Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. Note: This bit is not used in I2S mode and SPI TI mode.
0x40013000 C   FIELD 10w01 RXONLY (rw): Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. Note: This bit is not used in I2S mode.
0x40013000 C   FIELD 11w01 CRCL (rw): CRC length This bit is set and cleared by software to select the CRC length. Note: This bit should be written only when SPI is disabled (SPE = 0) for correct operation. This bit is not used in I2S mode.
0x40013000 C   FIELD 12w01 CRCNEXT (rw): Transmit CRC next Note: This bit has to be written as soon as the last data is written in the SPI_DR register. This bit is not used in I2S mode.
0x40013000 C   FIELD 13w01 CRCEN (rw): Hardware CRC calculation enable Note: This bit should be written only when SPI is disabled (SPE = 0) for correct operation. This bit is not used in I2S mode.
0x40013000 C   FIELD 14w01 BIDIOE (rw): Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. This bit is not used in I2S mode.
0x40013000 C   FIELD 15w01 BIDIMODE (rw): Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. Note: This bit is not used in I2S mode.
0x40013004 B  REGISTER CR2: SPI control register 2
0x40013004 C   FIELD 00w01 RXDMAEN (rw): Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set.
0x40013004 C   FIELD 01w01 TXDMAEN (rw): Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set.
0x40013004 C   FIELD 02w01 SSOE (rw): SS output enable Note: This bit is not used in I2S mode and SPI TI mode.
0x40013004 C   FIELD 03w01 NSSP (rw): NSS pulse management This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = 1, or FRF = 1. Note: 1. This bit must be written only when the SPI is disabled (SPE=0). 2. This bit is not used in I2S mode and SPI TI mode.
0x40013004 C   FIELD 04w01 FRF (rw): Frame format 1 SPI TI mode Note: This bit must be written only when the SPI is disabled (SPE=0). This bit is not used in I2S mode.
0x40013004 C   FIELD 05w01 ERRIE (rw): Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode).
0x40013004 C   FIELD 06w01 RXNEIE (rw): RX buffer not empty interrupt enable
0x40013004 C   FIELD 07w01 TXEIE (rw): Tx buffer empty interrupt enable
0x40013004 C   FIELD 08w04 DS (rw): Data size These bits configure the data length for SPI transfers. If software attempts to write one of the Not used values, they are forced to the value 0111 (8-bit) Note: These bits are not used in I2S mode.
0x40013004 C   FIELD 12w01 FRXTH (rw): FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event Note: This bit is not used in I2S mode.
0x40013004 C   FIELD 13w01 LDMA_RX (rw): Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). Note: Refer to if the CRCEN bit is set. This bit is not used in IS mode.
0x40013004 C   FIELD 14w01 LDMA_TX (rw): Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). Note: Refer to if the CRCEN bit is set. This bit is not used in ImS mode.
0x40013008 B  REGISTER SR: SPI status register
0x40013008 C   FIELD 00w01 RXNE (ro): Receive buffer not empty
0x40013008 C   FIELD 01w01 TXE (ro): Transmit buffer empty
0x40013008 C   FIELD 02w01 CHSIDE (ro): Channel side Note: This bit is not used in SPI mode. It has no significance in PCM mode.
0x40013008 C   FIELD 03w01 UDR (ro): Underrun flag This flag is set by hardware and reset by a software sequence. Refer to page 1385 for the software sequence. Note: This bit is not used in SPI mode.
0x40013008 C   FIELD 04w01 CRCERR (rw): CRC error flag Note: This flag is set by hardware and cleared by software writing 0. This bit is not used in I2S mode.
0x40013008 C   FIELD 05w01 MODF (ro): Mode fault This flag is set by hardware and reset by a software sequence. Refer to (MODF) on page 1359 for the software sequence. Note: This bit is not used in I2S mode.
0x40013008 C   FIELD 06w01 OVR (ro): Overrun flag This flag is set by hardware and reset by a software sequence. Refer to page 1385 for the software sequence.
0x40013008 C   FIELD 07w01 BSY (ro): Busy flag This flag is set and cleared by hardware. Note: The BSY flag must be used with caution: refer to and .
0x40013008 C   FIELD 08w01 FRE (ro): Frame format error This flag is used for SPI in TI slave mode and I2S slave mode. Refer to error flags and . This flag is set by hardware and reset when SPI_SR is read by software.
0x40013008 C   FIELD 09w02 FRLVL (ro): FIFO reception level These bits are set and cleared by hardware. Note: These bits are not used in ImS mode and in SPI receive-only mode while CRC calculation is enabled.
0x40013008 C   FIELD 11w02 FTLVL (ro): FIFO transmission level These bits are set and cleared by hardware. Note: This bit is not used in I2S mode.
0x4001300C B  REGISTER DR8 (rw): Direct 8-bit access to data register
0x4001300C B  REGISTER DR: SPI data register
0x4001300C C   FIELD 00w08 DR: Data register
0x4001300C C   FIELD 00w16 DR (rw): Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See ). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used.
0x40013010 B  REGISTER CRCPR: SPI CRC polynomial register
0x40013010 C   FIELD 00w16 CRCPOLY (rw): CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be configured as required.
0x40013014 B  REGISTER RXCRCR: SPI Rx CRC register
0x40013014 C   FIELD 00w16 RXCRC (ro): Rx CRC register When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPI_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY Flag is set could return an incorrect value. These bits are not used in I2S mode.
0x40013018 B  REGISTER TXCRCR: SPI Tx CRC register
0x40013018 C   FIELD 00w16 TXCRC (ro): Tx CRC register When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode.
0x4001301C B  REGISTER I2SCFGR: SPIx_I2S configuration register
0x4001301C C   FIELD 00w01 CHLEN (rw): Channel length (number of bits per audio channel) The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode.
0x4001301C C   FIELD 01w02 DATLEN (rw): Data length to be transferred Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode.
0x4001301C C   FIELD 03w01 CKPOL (rw): Inactive state clock polarity Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode. The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals.
0x4001301C C   FIELD 04w02 I2SSTD (rw): I2S standard selection For more details on I2S standards, refer to Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode.
0x4001301C C   FIELD 07w01 PCMSYNC (rw): PCM frame synchronization Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode.
0x4001301C C   FIELD 08w02 I2SCFG (rw): I2S configuration mode Note: These bits should be configured when the I2S is disabled. They are not used in SPI mode.
0x4001301C C   FIELD 10w01 I2SE (rw): I2S enable Note: This bit is not used in SPI mode.
0x4001301C C   FIELD 11w01 I2SMOD (rw): I2S mode selection Note: This bit should be configured when the SPI is disabled.
0x4001301C C   FIELD 12w01 ASTRTEN (rw): Asynchronous start enable. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. The appropriate level is a low level on WS signal when I2S Philips Standard is used, or a high level for other standards. Please refer to for additional information.
0x40013020 B  REGISTER I2SPR: SPI_I2S prescaler register
0x40013020 C   FIELD 00w08 I2SDIV (rw): I2S linear prescaler I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. Refer to . Note: These bits should be configured when the I2S is disabled. They are used only when the I2S is in master mode. They are not used in SPI mode.
0x40013020 C   FIELD 08w01 ODD (rw): Odd factor for the prescaler Refer to . Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. It is not used in SPI mode.
0x40013020 C   FIELD 09w01 MCKOE (rw): Master clock output enable Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. It is not used in SPI mode.
0x40013800 A PERIPHERAL USART1
0x40013800 B  REGISTER CR1: USART control register 1 [alternate]
0x40013800 C   FIELD 00w01 UE (rw): USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value.
0x40013800 C   FIELD 01w01 UESM (rw): USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985.
0x40013800 C   FIELD 02w01 RE (rw): Receiver enable This bit enables the receiver. It is set and cleared by software.
0x40013800 C   FIELD 03w01 TE (rw): Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.
0x40013800 C   FIELD 04w01 IDLEIE (rw): IDLE interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 05w01 RXNEIE (rw): RXFIFO not empty interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 06w01 TCIE (rw): Transmission complete interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 07w01 TXEIE (rw): TXFIFO not full interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 08w01 PEIE (rw): PE interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 09w01 PS (rw): Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0).
0x40013800 C   FIELD 10w01 PCE (rw): Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0).
0x40013800 C   FIELD 11w01 WAKE (rw): Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0).
0x40013800 C   FIELD 12w01 M0 (rw): Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0).
0x40013800 C   FIELD 13w01 MME (rw): Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software.
0x40013800 C   FIELD 14w01 CMIE (rw): Character match interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 15w01 OVER8 (rw): Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.
0x40013800 C   FIELD 16w05 DEDT (rw): Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013800 C   FIELD 21w05 DEAT (rw): Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013800 C   FIELD 26w01 RTOIE (rw): Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. .
0x40013800 C   FIELD 27w01 EOBIE (rw): End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40013800 C   FIELD 28w01 M1 (rw): Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00: 1 start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 start bit, 9 Data bits, n Stop bit M[1:0] = 10: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported.
0x40013800 C   FIELD 29w01 FIFOEN (rw): FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
0x40013800 C   FIELD 30w01 TXFEIE (rw): TXFIFO empty interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 31w01 RXFFIE (rw): RXFIFO Full interrupt enable This bit is set and cleared by software.
0x40013804 B  REGISTER CR2: USART control register 2
0x40013804 C   FIELD 00w01 SLVEN (rw): Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 03w01 DIS_NSS (rw): When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 04w01 ADDM7 (rw): 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively.
0x40013804 C   FIELD 05w01 LBDL (rw): LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 06w01 LBDIE (rw): LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 08w01 LBCL (rw): Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 09w01 CPHA (rw): Clock phase This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 10w01 CPOL (rw): Clock polarity This bit enables the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 11w01 CLKEN (rw): Clock enable This bit enables the user to enable the CK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1
0x40013804 C   FIELD 12w02 STOP (rw): stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0).
0x40013804 C   FIELD 14w01 LINEN (rw): LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 15w01 SWAP (rw): Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0).
0x40013804 C   FIELD 16w01 RXINV (rw): RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0).
0x40013804 C   FIELD 17w01 TXINV (rw): TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0).
0x40013804 C   FIELD 18w01 DATAINV (rw): Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0).
0x40013804 C   FIELD 19w01 MSBFIRST (rw): Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0).
0x40013804 C   FIELD 20w01 ABREN (rw): Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 21w02 ABRMOD (rw): Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 23w01 RTOEN (rw): Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 24w08 ADD (rw): Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0).
0x40013808 B  REGISTER CR3: USART control register 3
0x40013808 C   FIELD 00w01 EIE (rw): Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register).
0x40013808 C   FIELD 01w01 IREN (rw): IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 02w01 IRLP (rw): IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 03w01 HDSEL (rw): Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0).
0x40013808 C   FIELD 04w01 NACK (rw): Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 05w01 SCEN (rw): Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 06w01 DMAR (rw): DMA enable receiver This bit is set/reset by software
0x40013808 C   FIELD 07w01 DMAT (rw): DMA enable transmitter This bit is set/reset by software
0x40013808 C   FIELD 08w01 RTSE (rw): RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 09w01 CTSE (rw): CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 10w01 CTSIE (rw): CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 11w01 ONEBIT (rw): One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0).
0x40013808 C   FIELD 12w01 OVRDIS (rw): Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data
0x40013808 C   FIELD 13w01 DDRE (rw): DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error.
0x40013808 C   FIELD 14w01 DEM (rw): Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. .
0x40013808 C   FIELD 15w01 DEP (rw): Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 17w03 SCARCNT (rw): Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 20w02 WUS (rw): Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985.
0x40013808 C   FIELD 22w01 WUFIE (rw): Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985.
0x40013808 C   FIELD 23w01 TXFTIE (rw): TXFIFO threshold interrupt enable This bit is set and cleared by software.
0x40013808 C   FIELD 24w01 TCBGTIE (rw): Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 25w03 RXFTCFG (rw): Receive FIFO threshold configuration Remaining combinations: Reserved
0x40013808 C   FIELD 28w01 RXFTIE (rw): RXFIFO threshold interrupt enable This bit is set and cleared by software.
0x40013808 C   FIELD 29w03 TXFTCFG (rw): TXFIFO threshold configuration Remaining combinations: Reserved
0x4001380C B  REGISTER BRR: USART baud rate register
0x4001380C C   FIELD 00w16 BRR (rw): USART baud rate BRR[15:4] BRR[15:4] = USARTDIV[15:4] BRR[3:0] When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. When OVER8 = 1: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared.
0x40013810 B  REGISTER GTPR: USART guard time and prescaler register
0x40013810 C   FIELD 00w08 PSC (rw): Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... ... This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to 0 when the Smartcard and IrDA modes are not supported. Refer to .
0x40013810 C   FIELD 08w08 GT (rw): Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013814 B  REGISTER RTOR: USART receiver timeout register
0x40013814 C   FIELD 00w24 RTO (rw): Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character.
0x40013814 C   FIELD 24w08 BLEN (rw): Block Length This bitfield gives the Block length in Smartcard T = 1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0: 0 information characters + LEC BLEN = 1: 0 information characters + CRC BLEN = 255: 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE = 0 (TXFE = 0 in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE = 0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block.
0x40013818 B  REGISTER RQR: USART request register
0x40013818 C   FIELD 00w01 ABRRQ (wo): Auto baud rate request Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0x40013818 C   FIELD 01w01 SBKRQ (wo): Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit.
0x40013818 C   FIELD 02w01 MMRQ (wo): Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag.
0x40013818 C   FIELD 03w01 RXFRQ (wo): Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition.
0x40013818 C   FIELD 04w01 TXFRQ (wo): Transmit data flush request When FIFO mode is disabled, writing 1 to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register.
0x4001381C B  REGISTER ISR: USART interrupt and status register [alternate]
0x4001381C C   FIELD 00w01 PE (ro): Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
0x4001381C C   FIELD 01w01 FE (ro): Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
0x4001381C C   FIELD 02w01 NE (ro): Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 2012). This error is associated with the character in the USART_RDR.
0x4001381C C   FIELD 03w01 ORE (ro): Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE = 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register.
0x4001381C C   FIELD 04w01 IDLE (ro): Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set.
0x4001381C C   FIELD 05w01 RXFNE (ro): RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register.
0x4001381C C   FIELD 06w01 TC (ro): Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set.
0x4001381C C   FIELD 07w01 TXFNF (ro): TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission.
0x4001381C C   FIELD 08w01 LBDF (ro): LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to .
0x4001381C C   FIELD 09w01 CTSIF (ro): CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
0x4001381C C   FIELD 10w01 CTS (ro): CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
0x4001381C C   FIELD 11w01 RTOF (ro): Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value.
0x4001381C C   FIELD 12w01 EOBF (ro): End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to .
0x4001381C C   FIELD 13w01 UDR (ro): SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to .
0x4001381C C   FIELD 14w01 ABRE (ro): Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
0x4001381C C   FIELD 15w01 ABRF (ro): Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
0x4001381C C   FIELD 16w01 BUSY (ro): Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not).
0x4001381C C   FIELD 17w01 CMF (ro): Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register.
0x4001381C C   FIELD 18w01 SBKF (ro): Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission.
0x4001381C C   FIELD 19w01 RWU (ro): Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4001381C C   FIELD 20w01 WUF (ro): Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4001381C C   FIELD 21w01 TEACK (ro): Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period.
0x4001381C C   FIELD 22w01 REACK (ro): Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4001381C C   FIELD 23w01 TXFE (ro): TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the USART_CR1 register.
0x4001381C C   FIELD 24w01 RXFF (ro): RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit = 1 in the USART_CR1 register.
0x4001381C C   FIELD 25w01 TCBGT (ro): Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is 1. Refer to on page 1985.
0x4001381C C   FIELD 26w01 RXFT (ro): RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to 101, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data.
0x4001381C C   FIELD 27w01 TXFT (ro): TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit = 1 (bit 31) in the USART_CR3 register.
0x40013820 B  REGISTER ICR: USART interrupt flag clear register
0x40013820 C   FIELD 00w01 PECF (wo): Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register.
0x40013820 C   FIELD 01w01 FECF (wo): Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register.
0x40013820 C   FIELD 02w01 NECF (wo): Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register.
0x40013820 C   FIELD 03w01 ORECF (wo): Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register.
0x40013820 C   FIELD 04w01 IDLECF (wo): Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
0x40013820 C   FIELD 05w01 TXFECF (wo): TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register.
0x40013820 C   FIELD 06w01 TCCF (wo): Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register.
0x40013820 C   FIELD 07w01 TCBGTCF (wo): Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register.
0x40013820 C   FIELD 08w01 LBDCF (wo): LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013820 C   FIELD 09w01 CTSCF (wo): CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013820 C   FIELD 11w01 RTOCF (wo): Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 1985.
0x40013820 C   FIELD 12w01 EOBCF (wo): End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40013820 C   FIELD 13w01 UDRCF (wo): SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to
0x40013820 C   FIELD 17w01 CMCF (wo): Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register.
0x40013820 C   FIELD 20w01 WUCF (wo): Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985.
0x40013824 B  REGISTER RDR: USART receive data register
0x40013824 C   FIELD 00w09 RDR (ro): Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see ). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit.
0x40013828 B  REGISTER TDR: USART transmit data register
0x40013828 C   FIELD 00w09 TDR (rw): Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see ). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF = 1.
0x4001382C B  REGISTER PRESC: USART prescaler register
0x4001382C C   FIELD 00w04 PRESCALER (rw): Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256.
0x40014400 A PERIPHERAL TIM16
0x40014400 B  REGISTER CR1: TIM16 control register 1
0x40014400 C   FIELD 00w01 CEN (rw): Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
0x40014400 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
0x40014400 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
0x40014400 C   FIELD 03w01 OPM (rw): One pulse mode
0x40014400 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40014400 C   FIELD 08w02 CKD (rw): Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx),
0x40014400 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40014404 B  REGISTER CR2: TIM16 control register 2
0x40014404 C   FIELD 00w01 CCPC (rw): Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
0x40014404 C   FIELD 02w01 CCUS (rw): Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
0x40014404 C   FIELD 03w01 CCDS (rw): Capture/compare DMA selection
0x40014404 C   FIELD 08w01 OIS1 (rw): Output Idle state (OC1 output)
0x40014404 C   FIELD 09w01 OIS1N (rw): Output Idle state (OC1N output)
0x4001440C B  REGISTER DIER: TIM16 DMA/interrupt enable register
0x4001440C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x4001440C C   FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x4001440C C   FIELD 05w01 COMIE (rw): COM interrupt enable
0x4001440C C   FIELD 07w01 BIE (rw): Break interrupt enable
0x4001440C C   FIELD 08w01 UDE (rw): Update DMA request enable
0x4001440C C   FIELD 09w01 CC1DE (rw): Capture/Compare 1 DMA request enable
0x40014410 B  REGISTER SR: TIM16 status register
0x40014410 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register.
0x40014410 C   FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag
0x40014410 C   FIELD 05w01 COMIF (rw): COM interrupt flag
0x40014410 C   FIELD 07w01 BIF (rw): Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
0x40014410 C   FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag
0x40014414 B  REGISTER EGR: TIM16 event generation register
0x40014414 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40014414 C   FIELD 01w01 CC1G (wo): Capture/compare 1 generation
0x40014414 C   FIELD 05w01 COMG (wo): Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output.
0x40014414 C   FIELD 07w01 BG (wo): Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40014418 B  REGISTER CCMR1_Input: TIM16 capture/compare mode register 1 [alternate]
0x40014418 B  REGISTER CCMR1_Output: TIM16 capture/compare mode register 1 [alternate]
0x40014418 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
0x40014418 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40014418 C   FIELD 02w01 OC1FE (rw): Output compare 1 fast enable
0x40014418 C   FIELD 02w02 IC1PSC (rw): Input capture 1 prescaler
0x40014418 C   FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40014418 C   FIELD 04w03 OC1M (rw): Output compare 1 mode
0x40014418 C   FIELD 04w04 IC1F (rw): Input capture 1 filter
0x40014418 C   FIELD 16w01 OC1M_3 (rw): Output compare 1 mode, bit 3
0x40014420 B  REGISTER CCER: TIM16 capture/compare enable register
0x40014420 C   FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable
0x40014420 C   FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity
0x40014420 C   FIELD 02w01 CC1NE (rw): Capture/Compare 1 complementary output enable
0x40014420 C   FIELD 03w01 CC1NP (rw): Capture/Compare 1 output Polarity
0x40014424 B  REGISTER CNT: TIM16 counter
0x40014424 C   FIELD 00w16 CNT (rw): Counter value
0x40014424 C   FIELD 31w01 UIFCPY (ro): UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0.
0x40014428 B  REGISTER PSC: TIM16 prescaler
0x40014428 C   FIELD 00w16 PSC (rw): Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode).
0x4001442C B  REGISTER ARR: TIM16 auto-reload register
0x4001442C C   FIELD 00w16 ARR (rw): Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null.
0x40014430 B  REGISTER RCR: TIM16 repetition counter register
0x40014430 C   FIELD 00w08 REP (rw): Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode.
0x40014434 B  REGISTER CCR1: capture/compare register
0x40014434 C   FIELD 00w16 CCR (rw): Capture/Compare value
0x40014444 B  REGISTER BDTR: TIM16 break and dead-time register
0x40014444 C   FIELD 00w08 DTG (rw): Dead-time generator setup
0x40014444 C   FIELD 08w02 LOCK (rw): Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
0x40014444 C   FIELD 10w01 OSSI (rw): Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 1793). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014444 C   FIELD 11w01 OSSR (rw): Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 1793). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014444 C   FIELD 12w01 BKE (rw): Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014444 C   FIELD 13w01 BKP (rw): Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014444 C   FIELD 14w01 AOE (rw): Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014444 C   FIELD 15w01 MOE (rw): Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 1793).
0x40014444 C   FIELD 16w04 BKF (rw): Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014444 C   FIELD 26w01 BKDSRM (rw): Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014444 C   FIELD 28w01 BKBID (rw): Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014448 B  REGISTER DCR: TIM16 DMA control register
0x40014448 C   FIELD 00w05 DBA (rw): DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
0x40014448 C   FIELD 08w05 DBL (rw): DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ...
0x4001444C B  REGISTER DMAR: TIM16 DMA address for full transfer
0x4001444C C   FIELD 00w16 DMAB (rw): DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
0x40014460 B  REGISTER AF1: TIM16 alternate function register 1
0x40014460 C   FIELD 00w01 BKINE (rw): BRK BKIN input enable This bit enables the BKIN alternate function input for the timers BRK input. BKIN input is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014460 C   FIELD 09w01 BKINP (rw): BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014468 B  REGISTER TISEL: TIM16 input selection register
0x40014468 C   FIELD 00w04 TI1SEL (rw): selects TI1[0] to TI1[15] input Others: Reserved
0x40014800 A PERIPHERAL TIM17
0x40014800 B  REGISTER CR1 (=TIM16.CR1): TIM17 control register 1
0x40014804 B  REGISTER CR2 (=TIM16.CR2): TIM17 control register 2
0x4001480C B  REGISTER DIER (=TIM16.DIER): TIM17 DMA/interrupt enable register
0x40014810 B  REGISTER SR (=TIM16.SR): TIM17 status register
0x40014814 B  REGISTER EGR (=TIM16.EGR): TIM17 event generation register
0x40014818 B  REGISTER CCMR1_Input (=TIM16.CCMR1_Input): TIM17 capture/compare mode register 1 [alternate]
0x40014818 B  REGISTER CCMR1_Output (=TIM16.CCMR1_Output): TIM17 capture/compare mode register 1 [alternate]
0x40014820 B  REGISTER CCER (=TIM16.CCER): TIM17 capture/compare enable register
0x40014824 B  REGISTER CNT (=TIM16.CNT): TIM17 counter
0x40014828 B  REGISTER PSC (=TIM16.PSC): TIM17 prescaler
0x4001482C B  REGISTER ARR (=TIM16.ARR): TIM17 auto-reload register
0x40014830 B  REGISTER RCR (=TIM16.RCR): TIM17 repetition counter register
0x40014834 B  REGISTER CCR1 (=TIM16.CCR%s): capture/compare register
0x40014844 B  REGISTER BDTR (=TIM16.BDTR): TIM17 break and dead-time register
0x40014848 B  REGISTER DCR (=TIM16.DCR): TIM17 DMA control register
0x4001484C B  REGISTER DMAR (=TIM16.DMAR): TIM17 DMA address for full transfer
0x40014860 B  REGISTER AF1: TIM17 alternate function register 1
0x40014860 C   FIELD 00w01 BKINE (rw): BRK BKIN input enable This bit enables the BKIN alternate function input for the timers BRK input. BKIN input is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014860 C   FIELD 09w01 BKINP (rw): BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014868 B  REGISTER TISEL: TIM17 input selection register
0x40014868 C   FIELD 00w04 TI1SEL (rw): selects TI1[0] to TI1[15] input Others: Reserved
0x40015800 A PERIPHERAL DBG
0x40015800 B  REGISTER IDCODE: DBG device ID code register
0x40015800 C   FIELD 00w12 DEV_ID (ro): Device identifier This bitfield indicates the device ID.
0x40015800 C   FIELD 16w16 REV_ID (ro): Revision identifier This bitfield indicates the revision of the device.
0x40015804 B  REGISTER CR: DBG configuration register
0x40015804 C   FIELD 01w01 DBG_STOP (rw): Debug Stop mode
0x40015804 C   FIELD 02w01 DBG_STANDBY (rw): Debug Standby and Shutdown modes
0x40015808 B  REGISTER APB_FZ1: DBG APB freeze register 1
0x40015808 C   FIELD 01w01 DBG_TIM3_STOP (rw): Clocking of TIM3 counter when the core is halted This bit enables/disables the clock to the counter of TIM3 when the core is halted:
0x40015808 C   FIELD 10w01 DBG_RTC_STOP (rw): Clocking of RTC counter when the core is halted This bit enables/disables the clock to the counter of RTC when the core is halted:
0x40015808 C   FIELD 11w01 DBG_WWDG_STOP (rw): Clocking of WWDG counter when the core is halted This bit enables/disables the clock to the counter of WWDG when the core is halted:
0x40015808 C   FIELD 12w01 DBG_IWDG_STOP (rw): Clocking of IWDG counter when the core is halted This bit enables/disables the clock to the counter of IWDG when the core is halted:
0x40015808 C   FIELD 21w01 DBG_I2C1_SMBUS_TIMEOUT (rw): SMBUS timeout when core is halted
0x4001580C B  REGISTER APB_FZ2: DBG APB freeze register 2
0x4001580C C   FIELD 11w01 DBG_TIM1_STOP (rw): Clocking of TIM1 counter when the core is halted This bit enables/disables the clock to the counter of TIM1 when the core is halted:
0x4001580C C   FIELD 15w01 DBG_TIM14_STOP (rw): Clocking of TIM14 counter when the core is halted This bit enables/disables the clock to the counter of TIM14 when the core is halted:
0x4001580C C   FIELD 17w01 DBG_TIM16_STOP (rw): Clocking of TIM16 counter when the core is halted This bit enables/disables the clock to the counter of TIM16 when the core is halted:
0x4001580C C   FIELD 18w01 DBG_TIM17_STOP (rw): Clocking of TIM17 counter when the core is halted This bit enables/disables the clock to the counter of TIM17 when the core is halted:
0x40020000 A PERIPHERAL DMA
0x40020000 B  REGISTER ISR: DMA interrupt status register
0x40020000 C   FIELD 00w01 GIF1 (ro): Channel 1 Global interrupt flag
0x40020000 C   FIELD 01w01 TCIF1 (ro): Channel 1 Transfer Complete flag
0x40020000 C   FIELD 02w01 HTIF1 (ro): Channel 1 Half Transfer Complete flag
0x40020000 C   FIELD 03w01 TEIF1 (ro): Channel 1 Transfer Error flag
0x40020000 C   FIELD 04w01 GIF2 (ro): Channel 2 Global interrupt flag
0x40020000 C   FIELD 05w01 TCIF2 (ro): Channel 2 Transfer Complete flag
0x40020000 C   FIELD 06w01 HTIF2 (ro): Channel 2 Half Transfer Complete flag
0x40020000 C   FIELD 07w01 TEIF2 (ro): Channel 2 Transfer Error flag
0x40020000 C   FIELD 08w01 GIF3 (ro): Channel 3 Global interrupt flag
0x40020000 C   FIELD 09w01 TCIF3 (ro): Channel 3 Transfer Complete flag
0x40020000 C   FIELD 10w01 HTIF3 (ro): Channel 3 Half Transfer Complete flag
0x40020000 C   FIELD 11w01 TEIF3 (ro): Channel 3 Transfer Error flag
0x40020004 B  REGISTER IFCR: DMA interrupt flag clear register
0x40020004 C   FIELD 00w01 CGIF1 (wo): Channel 1 Global interrupt clear
0x40020004 C   FIELD 01w01 CTCIF1 (wo): Channel 1 Transfer Complete clear
0x40020004 C   FIELD 02w01 CHTIF1 (wo): Channel 1 Half Transfer clear
0x40020004 C   FIELD 03w01 CTEIF1 (wo): Channel 1 Transfer Error clear
0x40020004 C   FIELD 04w01 CGIF2 (wo): Channel 2 Global interrupt clear
0x40020004 C   FIELD 05w01 CTCIF2 (wo): Channel 2 Transfer Complete clear
0x40020004 C   FIELD 06w01 CHTIF2 (wo): Channel 2 Half Transfer clear
0x40020004 C   FIELD 07w01 CTEIF2 (wo): Channel 2 Transfer Error clear
0x40020004 C   FIELD 08w01 CGIF3 (wo): Channel 3 Global interrupt clear
0x40020004 C   FIELD 09w01 CTCIF3 (wo): Channel 3 Transfer Complete clear
0x40020004 C   FIELD 10w01 CHTIF3 (wo): Channel 3 Half Transfer clear
0x40020004 C   FIELD 11w01 CTEIF3 (wo): Channel 3 Transfer Error clear
0x40020008 B  CLUSTER CH1: Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
0x40020008 B  REGISTER CR1: DMA channel 1 configuration register
0x40020008 C   FIELD 00w01 EN (rw): channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.
0x40020008 C   FIELD 01w01 TCIE (rw): transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
0x40020008 C   FIELD 02w01 HTIE (rw): half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
0x40020008 C   FIELD 03w01 TEIE (rw): transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
0x40020008 C   FIELD 04w01 DIR (rw): data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x40020008 C   FIELD 05w01 CIRC (rw): circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
0x40020008 C   FIELD 06w01 PINC (rw): peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x40020008 C   FIELD 07w01 MINC (rw): memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x40020008 C   FIELD 08w02 PSIZE (rw): peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x40020008 C   FIELD 10w02 MSIZE (rw): memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x40020008 C   FIELD 12w02 PL (rw): priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x40020008 C   FIELD 14w01 MEM2MEM (rw): memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x4002000C B  REGISTER NDTR1: DMA channel 1 number of data to transfer register
0x4002000C C   FIELD 00w16 NDT (rw): number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x40020010 B  REGISTER PAR1: DMA channel 1 peripheral address register
0x40020010 C   FIELD 00w32 PA (rw): peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
0x40020014 B  REGISTER MAR1: DMA channel 1 memory address register
0x40020014 C   FIELD 00w32 MA (rw): peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
0x4002001C B  CLUSTER CH2: Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
0x4002001C B  REGISTER CR2: DMA channel 1 configuration register
0x4002001C C   FIELD 00w01 EN (rw): channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.
0x4002001C C   FIELD 01w01 TCIE (rw): transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
0x4002001C C   FIELD 02w01 HTIE (rw): half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
0x4002001C C   FIELD 03w01 TEIE (rw): transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
0x4002001C C   FIELD 04w01 DIR (rw): data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x4002001C C   FIELD 05w01 CIRC (rw): circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
0x4002001C C   FIELD 06w01 PINC (rw): peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x4002001C C   FIELD 07w01 MINC (rw): memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x4002001C C   FIELD 08w02 PSIZE (rw): peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x4002001C C   FIELD 10w02 MSIZE (rw): memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x4002001C C   FIELD 12w02 PL (rw): priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x4002001C C   FIELD 14w01 MEM2MEM (rw): memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x40020020 B  REGISTER NDTR2: DMA channel 1 number of data to transfer register
0x40020020 C   FIELD 00w16 NDT (rw): number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x40020024 B  REGISTER PAR2: DMA channel 1 peripheral address register
0x40020024 C   FIELD 00w32 PA (rw): peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
0x40020028 B  REGISTER MAR2: DMA channel 1 memory address register
0x40020028 C   FIELD 00w32 MA (rw): peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
0x40020030 B  CLUSTER CH3: Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
0x40020030 B  REGISTER CR3: DMA channel 1 configuration register
0x40020030 C   FIELD 00w01 EN (rw): channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.
0x40020030 C   FIELD 01w01 TCIE (rw): transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
0x40020030 C   FIELD 02w01 HTIE (rw): half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
0x40020030 C   FIELD 03w01 TEIE (rw): transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
0x40020030 C   FIELD 04w01 DIR (rw): data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x40020030 C   FIELD 05w01 CIRC (rw): circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
0x40020030 C   FIELD 06w01 PINC (rw): peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x40020030 C   FIELD 07w01 MINC (rw): memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x40020030 C   FIELD 08w02 PSIZE (rw): peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x40020030 C   FIELD 10w02 MSIZE (rw): memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x40020030 C   FIELD 12w02 PL (rw): priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x40020030 C   FIELD 14w01 MEM2MEM (rw): memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x40020034 B  REGISTER NDTR3: DMA channel 1 number of data to transfer register
0x40020034 C   FIELD 00w16 NDT (rw): number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
0x40020038 B  REGISTER PAR3: DMA channel 1 peripheral address register
0x40020038 C   FIELD 00w32 PA (rw): peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
0x4002003C B  REGISTER MAR3: DMA channel 1 memory address register
0x4002003C C   FIELD 00w32 MA (rw): peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
0x40020800 A PERIPHERAL DMAMUX
0x40020800 B  REGISTER CCR0: DMA Multiplexer Channel 0 Control register
0x40020800 C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x40020800 C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x40020800 C   FIELD 09w01 EGE (rw): Event generation enable
0x40020800 C   FIELD 16w01 SE (rw): Synchronization enable
0x40020800 C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x40020800 C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x40020800 C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources).
0x40020804 B  REGISTER CCR1: DMA Multiplexer Channel 1 Control register
0x40020804 C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x40020804 C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x40020804 C   FIELD 09w01 EGE (rw): Event generation enable
0x40020804 C   FIELD 16w01 SE (rw): Synchronization enable
0x40020804 C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x40020804 C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x40020804 C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources).
0x40020808 B  REGISTER CCR2: DMA Multiplexer Channel 2 Control register
0x40020808 C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x40020808 C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x40020808 C   FIELD 09w01 EGE (rw): Event generation enable
0x40020808 C   FIELD 16w01 SE (rw): Synchronization enable
0x40020808 C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x40020808 C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x40020808 C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources).
0x40020880 B  REGISTER CSR: DMAMUX request line multiplexer interrupt channel status register
0x40020880 C   FIELD 00w01 SOF0 (ro): Synchronization Overrun Flag 0
0x40020880 C   FIELD 01w01 SOF1 (ro): Synchronization Overrun Flag 1
0x40020880 C   FIELD 02w01 SOF2 (ro): Synchronization Overrun Flag 2
0x40020884 B  REGISTER CFR: DMAMUX request line multiplexer interrupt clear flag register
0x40020884 C   FIELD 00w01 CSOF0 (wo): Synchronization Clear Overrun Flag 0
0x40020884 C   FIELD 01w01 CSOF1 (wo): Synchronization Clear Overrun Flag 1
0x40020884 C   FIELD 02w01 CSOF2 (wo): Synchronization Clear Overrun Flag 2
0x40020900 B  REGISTER RGCR0: DMAMUX request generator channel 0 configuration register
0x40020900 C   FIELD 00w05 SIG_ID (rw): Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
0x40020900 C   FIELD 08w01 OIE (rw): Trigger overrun interrupt enable
0x40020900 C   FIELD 16w01 GE (rw): DMA request generator channel x enable
0x40020900 C   FIELD 17w02 GPOL (rw): DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
0x40020900 C   FIELD 19w05 GNBREQ (rw): Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field must be written only when GE bit is disabled.
0x40020904 B  REGISTER RGCR1: DMAMUX request generator channel 1 configuration register
0x40020904 C   FIELD 00w05 SIG_ID (rw): Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
0x40020904 C   FIELD 08w01 OIE (rw): Trigger overrun interrupt enable
0x40020904 C   FIELD 16w01 GE (rw): DMA request generator channel x enable
0x40020904 C   FIELD 17w02 GPOL (rw): DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
0x40020904 C   FIELD 19w05 GNBREQ (rw): Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field must be written only when GE bit is disabled.
0x40020908 B  REGISTER RGCR2: DMAMUX request generator channel 2 configuration register
0x40020908 C   FIELD 00w05 SIG_ID (rw): Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
0x40020908 C   FIELD 08w01 OIE (rw): Trigger overrun interrupt enable
0x40020908 C   FIELD 16w01 GE (rw): DMA request generator channel x enable
0x40020908 C   FIELD 17w02 GPOL (rw): DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
0x40020908 C   FIELD 19w05 GNBREQ (rw): Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field must be written only when GE bit is disabled.
0x4002090C B  REGISTER RGCR3: DMAMUX request generator channel 3 configuration register
0x4002090C C   FIELD 00w05 SIG_ID (rw): Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
0x4002090C C   FIELD 08w01 OIE (rw): Trigger overrun interrupt enable
0x4002090C C   FIELD 16w01 GE (rw): DMA request generator channel x enable
0x4002090C C   FIELD 17w02 GPOL (rw): DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
0x4002090C C   FIELD 19w05 GNBREQ (rw): Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field must be written only when GE bit is disabled.
0x40020940 B  REGISTER RGSR: DMAMUX request generator interrupt status register
0x40020940 C   FIELD 00w01 OF0 (ro): Generator Overrun Flag 0
0x40020940 C   FIELD 01w01 OF1 (ro): Generator Overrun Flag 1
0x40020940 C   FIELD 02w01 OF2 (ro): Generator Overrun Flag 2
0x40020940 C   FIELD 03w01 OF3 (ro): Generator Overrun Flag 3
0x40020944 B  REGISTER RGCFR: DMAMUX request generator interrupt clear flag register
0x40020944 C   FIELD 00w01 COF0 (wo): Generator Clear Overrun Flag 0
0x40020944 C   FIELD 01w01 COF1 (wo): Generator Clear Overrun Flag 1
0x40020944 C   FIELD 02w01 COF2 (wo): Generator Clear Overrun Flag 2
0x40020944 C   FIELD 03w01 COF3 (wo): Generator Clear Overrun Flag 3
0x40021000 A PERIPHERAL RCC
0x40021000 B  REGISTER CR: RCC clock control register
0x40021000 C   FIELD 02w03 SYSDIV (rw): System clock division factor This bitfield controlled by software sets the division factor of the system clock divider to produce SYSCLK clock:
0x40021000 C   FIELD 05w03 HSIKERDIV (rw): HSI48 kernel clock division factor This bitfield controlled by software sets the division factor of the kernel clock divider to produce HSIKER clock:
0x40021000 C   FIELD 08w01 HSION (rw): HSI48 clock enable Set and cleared by software and hardware, with hardware taking priority. Kept low by hardware as long as the device is in a low-power mode. Kept high by hardware as long as the system is clocked with a clock derived from HSI48. This includes the exit from low-power modes and the system clock fall-back to HSI48 upon failing HSE oscillator clock selected as system clock source.
0x40021000 C   FIELD 09w01 HSIKERON (rw): HSI48 always-enable for peripheral kernels. Set and cleared by software. Setting the bit activates the HSI48 oscillator in Run and Stop modes, regardless of the HSION bit state. The HSI48 clock can only feed USART1, USART2, and I2C1 peripherals configured with HSI48 as kernel clock. Note: Keeping the HSI48 active in Stop mode allows speeding up the serial interface communication as the HSI48 clock is ready immediately upon exiting Stop mode.
0x40021000 C   FIELD 10w01 HSIRDY (ro): HSI48 clock ready flag Set by hardware when the HSI48 oscillator is enabled through HSION and ready to use (stable). Note: Upon clearing HSION, HSIRDY goes low after six HSI48 clock cycles.
0x40021000 C   FIELD 11w03 HSIDIV (rw): HSI48 clock division factor This bitfield controlled by software sets the division factor of the HSI48 clock divider to produce HSISYS clock:
0x40021000 C   FIELD 16w01 HSEON (rw): HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, or Standby, or Shutdown mode. This bit cannot be cleared if the HSE oscillator is used directly or indirectly as the system clock.
0x40021000 C   FIELD 17w01 HSERDY (ro): HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable and ready for use. Note: Upon clearing HSEON, HSERDY goes low after six HSE clock cycles.
0x40021000 C   FIELD 18w01 HSEBYP (rw): HSE crystal oscillator bypass Set and cleared by software. When the bit is set, the internal HSE oscillator is bypassed for use of an external clock. The external clock must then be enabled with the HSEON bit set. Write access to the bit is only effective when the HSE oscillator is disabled.
0x40021000 C   FIELD 19w01 CSSON (rw): Clock security system enable Set by software to enable the clock security system. When the bit is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. The bit is cleared by hardware upon reset.
0x40021004 B  REGISTER ICSCR: RCC internal clock source calibration register
0x40021004 C   FIELD 00w08 HSICAL (ro): HSI48 clock calibration This bitfield directly acts on the HSI48 clock frequency. Its value is a sum of an internal factory-programmed number and the value of the HSITRIM[6:0] bitfield. In the factory, the internal number is set to calibrate the HSI48 clock frequency to 48 MHz (with HSITRIM[6:0] left at its reset value). Refer to the device datasheet for HSI48 calibration accuracy and for the frequency trimming granularity. Note: The trimming effect presents discontinuities at HSICAL[7:0] multiples of 64.
0x40021004 C   FIELD 08w07 HSITRIM (rw): HSI48 clock trimming The value of this bitfield contributes to the HSICAL[7:0] bitfield value. It allows HSI48 clock frequency user trimming. The HSI48 frequency accuracy as stated in the device datasheet applies when this bitfield is left at its reset value.
0x40021008 B  REGISTER CFGR: RCC clock configuration register
0x40021008 C   FIELD 00w03 SW (rw): System clock switch This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: Others: Reserved The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, or Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected.
0x40021008 C   FIELD 03w03 SWS (ro): System clock switch status This bitfield is controlled by hardware to indicate the clock source used as system clock: Others: Reserved
0x40021008 C   FIELD 08w04 HPRE (rw): AHB prescaler This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: 0xxx: 1
0x40021008 C   FIELD 12w03 PPRE (rw): APB prescaler This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: 0xx: 1
0x40021008 C   FIELD 16w04 MCO2SEL (rw): Microcontroller clock output 2 clock selector This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching.
0x40021008 C   FIELD 20w04 MCO2PRE (rw): Microcontroller clock output 2 prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: ... It is highly recommended to set this field before the MCO2 output is enabled.
0x40021008 C   FIELD 24w04 MCOSEL (rw): Microcontroller clock output clock selector This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. Any other value means no clock on MCO.
0x40021008 C   FIELD 28w04 MCOPRE (rw): Microcontroller clock output prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: ... It is highly recommended to set this field before the MCO output is enabled.
0x40021018 B  REGISTER CIER: RCC clock interrupt enable register
0x40021018 C   FIELD 00w01 LSIRDYIE (rw): LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization:
0x40021018 C   FIELD 01w01 LSERDYIE (rw): LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization:
0x40021018 C   FIELD 03w01 HSIRDYIE (rw): HSI16 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization:
0x40021018 C   FIELD 04w01 HSERDYIE (rw): HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization:
0x4002101C B  REGISTER CIFR: RCC clock interrupt flag register
0x4002101C C   FIELD 00w01 LSIRDYF (ro): LSI ready interrupt flag This flag indicates a pending interrupt upon LSE clock getting ready. Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit.
0x4002101C C   FIELD 01w01 LSERDYF (ro): LSE ready interrupt flag This flag indicates a pending interrupt upon LSE clock getting ready. Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit.
0x4002101C C   FIELD 03w01 HSIRDYF (ro): HSI16 ready interrupt flag This flag indicates a pending interrupt upon HSI16 clock getting ready. Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in response to setting the HSION (refer to ). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit.
0x4002101C C   FIELD 04w01 HSERDYF (ro): HSE ready interrupt flag This flag indicates a pending interrupt upon HSE clock getting ready. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit.
0x4002101C C   FIELD 08w01 CSSF (ro): HSE clock security system interrupt flag This flag indicates a pending interrupt upon HSE clock failure. Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit.
0x4002101C C   FIELD 09w01 LSECSSF (ro): LSE clock security system interrupt flag This flag indicates a pending interrupt upon LSE clock failure. Set by hardware when a failure is detected in the LSE oscillator. Cleared by software by setting the LSECSSC bit.
0x40021020 B  REGISTER CICR: RCC clock interrupt clear register
0x40021020 C   FIELD 00w01 LSIRDYC (wo): LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag.
0x40021020 C   FIELD 01w01 LSERDYC (wo): LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag.
0x40021020 C   FIELD 03w01 HSIRDYC (wo): HSI16 ready interrupt clear This bit is set software to clear the HSIRDYF flag.
0x40021020 C   FIELD 04w01 HSERDYC (wo): HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag.
0x40021020 C   FIELD 08w01 CSSC (wo): Clock security system interrupt clear This bit is set by software to clear the HSECSSF flag.
0x40021020 C   FIELD 09w01 LSECSSC (wo): LSE Clock security system interrupt clear This bit is set by software to clear the LSECSSF flag.
0x40021024 B  REGISTER IOPRSTR: RCC I/O port reset register
0x40021024 C   FIELD 00w01 GPIOARST (rw): I/O port A reset This bit is set and cleared by software.
0x40021024 C   FIELD 01w01 GPIOBRST (rw): I/O port B reset This bit is set and cleared by software.
0x40021024 C   FIELD 02w01 GPIOCRST (rw): I/O port C reset This bit is set and cleared by software.
0x40021024 C   FIELD 03w01 GPIODRST (rw): I/O port D reset This bit is set and cleared by software.
0x40021024 C   FIELD 05w01 GPIOFRST (rw): I/O port F reset This bit is set and cleared by software.
0x40021028 B  REGISTER AHBRSTR: RCC AHB peripheral reset register
0x40021028 C   FIELD 00w01 DMA1RST (rw): DMA1 and DMAMUX reset Set and cleared by software.
0x40021028 C   FIELD 08w01 FLASHRST (rw): Flash memory interface reset Set and cleared by software. This bit can only be set when the Flash memory is in power down mode.
0x40021028 C   FIELD 12w01 CRCRST (rw): CRC reset Set and cleared by software.
0x4002102C B  REGISTER APBRSTR1: RCC APB peripheral reset register 1
0x4002102C C   FIELD 01w01 TIM3RST (rw): TIM3 timer reset Set and cleared by software.
0x4002102C C   FIELD 17w01 USART2RST (rw): USART2 reset Set and cleared by software.
0x4002102C C   FIELD 21w01 I2C1RST (rw): I2C1 reset Set and cleared by software.
0x4002102C C   FIELD 27w01 DBGRST (rw): Debug support reset Set and cleared by software.
0x4002102C C   FIELD 28w01 PWRRST (rw): Power interface reset Set and cleared by software.
0x40021030 B  REGISTER APBRSTR2: RCC APB peripheral reset register 2
0x40021030 C   FIELD 00w01 SYSCFGRST (rw): SYSCFG reset Set and cleared by software.
0x40021030 C   FIELD 11w01 TIM1RST (rw): TIM1 timer reset Set and cleared by software.
0x40021030 C   FIELD 12w01 SPI1RST (rw): SPI1 reset Set and cleared by software.
0x40021030 C   FIELD 14w01 USART1RST (rw): USART1 reset Set and cleared by software.
0x40021030 C   FIELD 15w01 TIM14RST (rw): TIM14 timer reset Set and cleared by software.
0x40021030 C   FIELD 17w01 TIM16RST (rw): TIM16 timer reset Set and cleared by software.
0x40021030 C   FIELD 18w01 TIM17RST (rw): TIM16 timer reset Set and cleared by software.
0x40021030 C   FIELD 20w01 ADCRST (rw): ADC reset Set and cleared by software.
0x40021034 B  REGISTER IOPENR: RCC I/O port clock enable register
0x40021034 C   FIELD 00w01 GPIOAEN (rw): I/O port A clock enable This bit is set and cleared by software.
0x40021034 C   FIELD 01w01 GPIOBEN (rw): I/O port B clock enable This bit is set and cleared by software.
0x40021034 C   FIELD 02w01 GPIOCEN (rw): I/O port C clock enable This bit is set and cleared by software.
0x40021034 C   FIELD 03w01 GPIODEN (rw): I/O port D clock enable This bit is set and cleared by software.
0x40021034 C   FIELD 05w01 GPIOFEN (rw): I/O port F clock enable This bit is set and cleared by software.
0x40021038 B  REGISTER AHBENR: RCC AHB peripheral clock enable register
0x40021038 C   FIELD 00w01 DMA1EN (rw): DMA1 and DMAMUX clock enable Set and cleared by software. DMAMUX is enabled as long as at least one DMA peripheral is enabled.
0x40021038 C   FIELD 08w01 FLASHEN (rw): Flash memory interface clock enable Set and cleared by software. This bit can only be cleared when the Flash memory is in power down mode.
0x40021038 C   FIELD 12w01 CRCEN (rw): CRC clock enable Set and cleared by software.
0x4002103C B  REGISTER APBENR1: RCC APB peripheral clock enable register 1
0x4002103C C   FIELD 01w01 TIM3EN (rw): TIM3 timer clock enable Set and cleared by software.
0x4002103C C   FIELD 10w01 RTCAPBEN (rw): RTC APB clock enable Set and cleared by software.
0x4002103C C   FIELD 11w01 WWDGEN (rw): WWDG clock enable Set by software to enable the window watchdog clock. Cleared by hardware system reset This bit can also be set by hardware if the WWDG_SW option bit is 0.
0x4002103C C   FIELD 17w01 USART2EN (rw): USART2 clock enable Set and cleared by software.
0x4002103C C   FIELD 21w01 I2C1EN (rw): I2C1 clock enable Set and cleared by software.
0x4002103C C   FIELD 27w01 DBGEN (rw): Debug support clock enable Set and cleared by software.
0x4002103C C   FIELD 28w01 PWREN (rw): Power interface clock enable Set and cleared by software.
0x40021040 B  REGISTER APBENR2: RCC APB peripheral clock enable register 2
0x40021040 C   FIELD 00w01 SYSCFGEN (rw): SYSCFG clock enable Set and cleared by software.
0x40021040 C   FIELD 11w01 TIM1EN (rw): TIM1 timer clock enable Set and cleared by software.
0x40021040 C   FIELD 12w01 SPI1EN (rw): SPI1 clock enable Set and cleared by software.
0x40021040 C   FIELD 14w01 USART1EN (rw): USART1 clock enable Set and cleared by software.
0x40021040 C   FIELD 15w01 TIM14EN (rw): TIM14 timer clock enable Set and cleared by software.
0x40021040 C   FIELD 17w01 TIM16EN (rw): TIM16 timer clock enable Set and cleared by software.
0x40021040 C   FIELD 18w01 TIM17EN (rw): TIM16 timer clock enable Set and cleared by software.
0x40021040 C   FIELD 20w01 ADCEN (rw): ADC clock enable Set and cleared by software.
0x40021044 B  REGISTER IOPSMENR: RCC I/O port in Sleep mode clock enable register
0x40021044 C   FIELD 00w01 GPIOASMEN (rw): I/O port A clock enable during Sleep mode Set and cleared by software.
0x40021044 C   FIELD 01w01 GPIOBSMEN (rw): I/O port B clock enable during Sleep mode Set and cleared by software.
0x40021044 C   FIELD 02w01 GPIOCSMEN (rw): I/O port C clock enable during Sleep mode Set and cleared by software.
0x40021044 C   FIELD 03w01 GPIODSMEN (rw): I/O port D clock enable during Sleep mode Set and cleared by software.
0x40021044 C   FIELD 05w01 GPIOFSMEN (rw): I/O port F clock enable during Sleep mode Set and cleared by software.
0x40021048 B  REGISTER AHBSMENR: RCC AHB peripheral clock enable in Sleep/Stop mode register
0x40021048 C   FIELD 00w01 DMA1SMEN (rw): DMA1 and DMAMUX clock enable during Sleep mode Set and cleared by software. Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral.
0x40021048 C   FIELD 08w01 FLASHSMEN (rw): Flash memory interface clock enable during Sleep mode Set and cleared by software. This bit can be activated only when the Flash memory is in power down mode.
0x40021048 C   FIELD 09w01 SRAMSMEN (rw): SRAM clock enable during Sleep mode Set and cleared by software.
0x40021048 C   FIELD 12w01 CRCSMEN (rw): CRC clock enable during Sleep mode Set and cleared by software.
0x4002104C B  REGISTER APBSMENR1: RCC APB peripheral clock enable in Sleep/Stop mode register 1
0x4002104C C   FIELD 01w01 TIM3SMEN (rw): TIM3 timer clock enable during Sleep mode Set and cleared by software.
0x4002104C C   FIELD 10w01 RTCAPBSMEN (rw): RTC APB clock enable during Sleep mode Set and cleared by software.
0x4002104C C   FIELD 11w01 WWDGSMEN (rw): WWDG clock enable during Sleep and Stop modes Set and cleared by software.
0x4002104C C   FIELD 17w01 USART2SMEN (rw): USART2 clock enable during Sleep and Stop modes Set and cleared by software.
0x4002104C C   FIELD 21w01 I2C1SMEN (rw): I2C1 clock enable during Sleep and Stop modes Set and cleared by software.
0x4002104C C   FIELD 27w01 DBGSMEN (rw): Debug support clock enable during Sleep mode Set and cleared by software.
0x4002104C C   FIELD 28w01 PWRSMEN (rw): Power interface clock enable during Sleep mode Set and cleared by software.
0x40021050 B  REGISTER APBSMENR2: RCC APB peripheral clock enable in Sleep/Stop mode register 2
0x40021050 C   FIELD 00w01 SYSCFGSMEN (rw): SYSCFG clock enable during Sleep and Stop modes Set and cleared by software.
0x40021050 C   FIELD 11w01 TIM1SMEN (rw): TIM1 timer clock enable during Sleep mode Set and cleared by software.
0x40021050 C   FIELD 12w01 SPI1SMEN (rw): SPI1 clock enable during Sleep mode Set and cleared by software.
0x40021050 C   FIELD 14w01 USART1SMEN (rw): USART1 clock enable during Sleep and Stop modes Set and cleared by software.
0x40021050 C   FIELD 15w01 TIM14SMEN (rw): TIM14 timer clock enable during Sleep mode Set and cleared by software.
0x40021050 C   FIELD 17w01 TIM16SMEN (rw): TIM16 timer clock enable during Sleep mode Set and cleared by software.
0x40021050 C   FIELD 18w01 TIM17SMEN (rw): TIM16 timer clock enable during Sleep mode Set and cleared by software.
0x40021050 C   FIELD 20w01 ADCSMEN (rw): ADC clock enable during Sleep mode Set and cleared by software.
0x40021054 B  REGISTER CCIPR: RCC peripherals independent clock configuration register
0x40021054 C   FIELD 00w02 USART1SEL (rw): USART1 clock source selection This bitfield is controlled by software to select USART1 clock source as follows:
0x40021054 C   FIELD 12w02 I2C1SEL (rw): I2C1 clock source selection This bitfield is controlled by software to select I2C1 clock source as follows:
0x40021054 C   FIELD 14w02 I2S1SEL (rw): I2S1 clock source selection This bitfield is controlled by software to select I2S1 clock source as follows:
0x40021054 C   FIELD 30w02 ADCSEL (rw): ADCs clock source selection This bitfield is controlled by software to select the clock source for ADC:
0x4002105C B  REGISTER CSR1: RCC control/status register 1
0x4002105C C   FIELD 00w01 LSEON (rw): LSE oscillator enable Set and cleared by software to enable LSE oscillator:
0x4002105C C   FIELD 01w01 LSERDY (ro): LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable): After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles.
0x4002105C C   FIELD 02w01 LSEBYP (rw): LSE oscillator bypass Set and cleared by software to bypass the LSE oscillator (in debug mode). This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0).
0x4002105C C   FIELD 03w02 LSEDRV (rw): LSE oscillator drive capability Set by software to select the LSE oscillator drive capability as follows: Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode.
0x4002105C C   FIELD 05w01 LSECSSON (rw): CSS on LSE enable Set by software to enable the clock security system on LSE (32 kHz) oscillator as follows: LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software must disable the LSECSSON bit.
0x4002105C C   FIELD 06w01 LSECSSD (ro): CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the clock security system on the external 32 kHz oscillator (LSE):
0x4002105C C   FIELD 08w02 RTCSEL (rw): RTC clock source selection Set by software to select the clock source for the RTC as follows: Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The RTCRST bit can be used to reset this bitfield to 00.
0x4002105C C   FIELD 15w01 RTCEN (rw): RTC clock enable Set and cleared by software. The bit enables clock to RTC and TAMP.
0x4002105C C   FIELD 16w01 RTCRST (rw): RTC domain software reset Set and cleared by software to reset the RTC domain:
0x4002105C C   FIELD 24w01 LSCOEN (rw): Low-speed clock output (LSCO) enable Set and cleared by software.
0x4002105C C   FIELD 25w01 LSCOSEL (rw): Low-speed clock output selection Set and cleared by software to select the low-speed output clock:
0x40021060 B  REGISTER CSR2: RCC control/status register 2
0x40021060 C   FIELD 00w01 LSION (rw): LSI oscillator enable Set and cleared by software to enable/disable the LSI oscillator:
0x40021060 C   FIELD 01w01 LSIRDY (ro): LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is ready (stable): After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC.
0x40021060 C   FIELD 23w01 RMVF (rw): Remove reset flags Set by software to clear the reset flags.
0x40021060 C   FIELD 25w01 OBLRSTF (ro): Option byte loader reset flag Set by hardware when a reset from the Option byte loading occurs. Cleared by setting the RMVF bit.
0x40021060 C   FIELD 26w01 PINRSTF (ro): Pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by setting the RMVF bit.
0x40021060 C   FIELD 27w01 PWRRSTF (ro): BOR or POR/PDR flag Set by hardware when a BOR or POR/PDR occurs. Cleared by setting the RMVF bit.
0x40021060 C   FIELD 28w01 SFTRSTF (ro): Software reset flag Set by hardware when a software reset occurs. Cleared by setting the RMVF bit.
0x40021060 C   FIELD 29w01 IWDGRSTF (ro): Independent window watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by setting the RMVF bit.
0x40021060 C   FIELD 30w01 WWDGRSTF (ro): Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by setting the RMVF bit.
0x40021060 C   FIELD 31w01 LPWRRSTF (ro): Low-power reset flag Set by hardware when a reset occurs due to illegal Stop, or Standby, or Shutdown mode entry. Cleared by setting the RMVF bit. This operates only if nRST_STOP, or nRST_STDBY or nRST_SHDW option bits are cleared.
0x40021800 A PERIPHERAL EXTI
0x40021800 B  REGISTER RTSR1: EXTI rising trigger selection register
0x40021800 C   FIELD 00w01 RT0 (rw): Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line.
0x40021800 C   FIELD 01w01 RT1 (rw): Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line.
0x40021800 C   FIELD 02w01 RT2 (rw): Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line.
0x40021800 C   FIELD 03w01 RT3 (rw): Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line.
0x40021800 C   FIELD 04w01 RT4 (rw): Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line.
0x40021800 C   FIELD 05w01 RT5 (rw): Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line.
0x40021800 C   FIELD 06w01 RT6 (rw): Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line.
0x40021800 C   FIELD 07w01 RT7 (rw): Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line.
0x40021800 C   FIELD 08w01 RT8 (rw): Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line.
0x40021800 C   FIELD 09w01 RT9 (rw): Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line.
0x40021800 C   FIELD 10w01 RT10 (rw): Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line.
0x40021800 C   FIELD 11w01 RT11 (rw): Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line.
0x40021800 C   FIELD 12w01 RT12 (rw): Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line.
0x40021800 C   FIELD 13w01 RT13 (rw): Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line.
0x40021800 C   FIELD 14w01 RT14 (rw): Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line.
0x40021800 C   FIELD 15w01 RT15 (rw): Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line.
0x40021804 B  REGISTER FTSR1: EXTI falling trigger selection register 1
0x40021804 C   FIELD 00w01 FT0 (rw): Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
0x40021804 C   FIELD 01w01 FT1 (rw): Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
0x40021804 C   FIELD 02w01 FT2 (rw): Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
0x40021804 C   FIELD 03w01 FT3 (rw): Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
0x40021804 C   FIELD 04w01 FT4 (rw): Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
0x40021804 C   FIELD 05w01 FT5 (rw): Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
0x40021804 C   FIELD 06w01 FT6 (rw): Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
0x40021804 C   FIELD 07w01 FT7 (rw): Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
0x40021804 C   FIELD 08w01 FT8 (rw): Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
0x40021804 C   FIELD 09w01 FT9 (rw): Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
0x40021804 C   FIELD 10w01 FT10 (rw): Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
0x40021804 C   FIELD 11w01 FT11 (rw): Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
0x40021804 C   FIELD 12w01 FT12 (rw): Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
0x40021804 C   FIELD 13w01 FT13 (rw): Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
0x40021804 C   FIELD 14w01 FT14 (rw): Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
0x40021804 C   FIELD 15w01 FT15 (rw): Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
0x40021808 B  REGISTER SWIER1: EXTI software interrupt event register 1
0x40021808 C   FIELD 00w01 SWI0 (rw): Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0.
0x40021808 C   FIELD 01w01 SWI1 (rw): Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0.
0x40021808 C   FIELD 02w01 SWI2 (rw): Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0.
0x40021808 C   FIELD 03w01 SWI3 (rw): Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0.
0x40021808 C   FIELD 04w01 SWI4 (rw): Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0.
0x40021808 C   FIELD 05w01 SWI5 (rw): Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0.
0x40021808 C   FIELD 06w01 SWI6 (rw): Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0.
0x40021808 C   FIELD 07w01 SWI7 (rw): Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0.
0x40021808 C   FIELD 08w01 SWI8 (rw): Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0.
0x40021808 C   FIELD 09w01 SWI9 (rw): Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0.
0x40021808 C   FIELD 10w01 SWI10 (rw): Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0.
0x40021808 C   FIELD 11w01 SWI11 (rw): Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0.
0x40021808 C   FIELD 12w01 SWI12 (rw): Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0.
0x40021808 C   FIELD 13w01 SWI13 (rw): Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0.
0x40021808 C   FIELD 14w01 SWI14 (rw): Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0.
0x40021808 C   FIELD 15w01 SWI15 (rw): Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0.
0x4002180C B  REGISTER RPR1: EXTI rising edge pending register 1
0x4002180C C   FIELD 00w01 RPIF0 (rw): Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x4002180C C   FIELD 01w01 RPIF1 (rw): Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x4002180C C   FIELD 02w01 RPIF2 (rw): Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x4002180C C   FIELD 03w01 RPIF3 (rw): Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x4002180C C   FIELD 04w01 RPIF4 (rw): Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x4002180C C   FIELD 05w01 RPIF5 (rw): Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x4002180C C   FIELD 06w01 RPIF6 (rw): Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x4002180C C   FIELD 07w01 RPIF7 (rw): Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x4002180C C   FIELD 08w01 RPIF8 (rw): Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x4002180C C   FIELD 09w01 RPIF9 (rw): Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x4002180C C   FIELD 10w01 RPIF10 (rw): Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x4002180C C   FIELD 11w01 RPIF11 (rw): Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x4002180C C   FIELD 12w01 RPIF12 (rw): Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x4002180C C   FIELD 13w01 RPIF13 (rw): Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x4002180C C   FIELD 14w01 RPIF14 (rw): Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x4002180C C   FIELD 15w01 RPIF15 (rw): Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x40021810 B  REGISTER FPR1: EXTI falling edge pending register 1
0x40021810 C   FIELD 00w01 FPIF0 (rw): Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x40021810 C   FIELD 01w01 FPIF1 (rw): Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x40021810 C   FIELD 02w01 FPIF2 (rw): Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x40021810 C   FIELD 03w01 FPIF3 (rw): Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x40021810 C   FIELD 04w01 FPIF4 (rw): Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x40021810 C   FIELD 05w01 FPIF5 (rw): Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x40021810 C   FIELD 06w01 FPIF6 (rw): Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x40021810 C   FIELD 07w01 FPIF7 (rw): Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x40021810 C   FIELD 08w01 FPIF8 (rw): Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x40021810 C   FIELD 09w01 FPIF9 (rw): Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x40021810 C   FIELD 10w01 FPIF10 (rw): Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x40021810 C   FIELD 11w01 FPIF11 (rw): Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x40021810 C   FIELD 12w01 FPIF12 (rw): Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x40021810 C   FIELD 13w01 FPIF13 (rw): Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x40021810 C   FIELD 14w01 FPIF14 (rw): Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x40021810 C   FIELD 15w01 FPIF15 (rw): Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0x40021860 B  REGISTER EXTICR1: EXTI external interrupt selection register
0x40021860 C   FIELD 00w08 EXTI0 (rw): EXTIm GPIO port selection (m = 4 * (x - 1)) These bits are written by software to select the source input for EXTIm external interrupt. Other: reserved
0x40021860 C   FIELD 08w08 EXTI1 (rw): 
0x40021860 C   FIELD 16w08 EXTI2 (rw): 
0x40021860 C   FIELD 24w08 EXTI3 (rw): 
0x40021864 B  REGISTER EXTICR2: EXTI external interrupt selection register
0x40021864 C   FIELD 00w08 EXTI0 (rw): EXTIm GPIO port selection (m = 4 * (x - 1)) These bits are written by software to select the source input for EXTIm external interrupt. Other: reserved
0x40021864 C   FIELD 08w08 EXTI1 (rw): 
0x40021864 C   FIELD 16w08 EXTI2 (rw): 
0x40021864 C   FIELD 24w08 EXTI3 (rw): 
0x40021868 B  REGISTER EXTICR3: EXTI external interrupt selection register
0x40021868 C   FIELD 00w08 EXTI0 (rw): EXTIm GPIO port selection (m = 4 * (x - 1)) These bits are written by software to select the source input for EXTIm external interrupt. Other: reserved
0x40021868 C   FIELD 08w08 EXTI1 (rw): 
0x40021868 C   FIELD 16w08 EXTI2 (rw): 
0x40021868 C   FIELD 24w08 EXTI3 (rw): 
0x4002186C B  REGISTER EXTICR4: EXTI external interrupt selection register
0x4002186C C   FIELD 00w08 EXTI0 (rw): EXTIm GPIO port selection (m = 4 * (x - 1)) These bits are written by software to select the source input for EXTIm external interrupt. Other: reserved
0x4002186C C   FIELD 08w08 EXTI1 (rw): 
0x4002186C C   FIELD 16w08 EXTI2 (rw): 
0x4002186C C   FIELD 24w08 EXTI3 (rw): 
0x40021880 B  REGISTER IMR1: EXTI CPU wakeup with interrupt mask register
0x40021880 C   FIELD 00w16 IM (rw): CPU wakeup with interrupt mask
0x40021880 C   FIELD 19w01 IM19 (rw): IM19
0x40021880 C   FIELD 23w01 IM23 (rw): IM23
0x40021880 C   FIELD 25w01 IM25 (rw): IM25
0x40021880 C   FIELD 31w01 IM31 (rw): IM31
0x40021884 B  REGISTER EMR1: EXTI CPU wakeup with event mask register
0x40021884 C   FIELD 00w16 EM (rw): CPU wakeup with event generation mask
0x40021884 C   FIELD 19w01 EM19 (rw): EM19
0x40021884 C   FIELD 23w01 EM23 (rw): EM23
0x40021884 C   FIELD 25w01 EM25 (rw): EM25
0x40021884 C   FIELD 31w01 EM31 (rw): EM31
0x40022000 A PERIPHERAL FLASH
0x40022000 B  REGISTER ACR (rw): FLASH access control register
0x40022000 C   FIELD 00w03 LATENCY (rw): Flash memory access latency The value in this bitfield represents the number of CPU wait states when accessing the flash memory. Other: Reserved A new write into the bitfield becomes effective when it returns the same value upon read.
0x40022000 C   FIELD 08w01 PRFTEN (rw): CPU Prefetch enable
0x40022000 C   FIELD 09w01 ICEN (rw): CPU Instruction cache enable
0x40022000 C   FIELD 11w01 ICRST (rw): CPU Instruction cache reset This bit can be written only when the instruction cache is disabled.
0x40022000 C   FIELD 16w01 EMPTY (rw): Main flash memory area empty This bit indicates whether the first location of the Main flash memory area was read as erased or as programmed during OBL. It is not affected by the system reset. Software may need to change this bit value after a flash memory program or erase operation. The bit can be set and reset by software.
0x40022000 C   FIELD 18w01 DBG_SWEN (rw): Debug access software enable Software may use this bit to enable/disable the debugger read access.
0x40022008 B  REGISTER KEYR (wo): FLASH key register
0x40022008 C   FIELD 00w32 KEY (wo): FLASH key The following values must be written consecutively to unlock the FLASH control register (FLASH_CR), thus enabling programming/erasing operations: KEY1: 0x4567 0123 KEY2: 0xCDEF 89AB
0x4002200C B  REGISTER OPTKEYR (wo): FLASH option key register
0x4002200C C   FIELD 00w32 OPTKEY (wo): Option byte key The following values must be written consecutively to unlock the flash memory option registers, enabling option byte programming/erasing operations: KEY1: 0x0819 2A3B KEY2: 0x4C5D 6E7F
0x40022010 B  REGISTER SR (rw): FLASH status register
0x40022010 C   FIELD 00w01 EOP (rw): End of operation Set by hardware when one or more flash memory operation (programming / erase) has been completed successfully. This bit is set only if the end of operation interrupts are enabled (EOPIE=1). Cleared by writing 1.
0x40022010 C   FIELD 01w01 OPERR (rw): Operation error Set by hardware when a flash memory operation (program / erase) completes unsuccessfully. This bit is set only if error interrupts are enabled (ERRIE=1). Cleared by writing 1 .
0x40022010 C   FIELD 03w01 PROGERR (rw): Programming error Set by hardware when a double-word address to be programmed contains a value different from '0xFFFF FFFF' before programming, except if the data to write is '0x0000 0000'. Cleared by writing 1.
0x40022010 C   FIELD 04w01 WRPERR (rw): Write protection error Set by hardware when an address to be erased/programmed belongs to a write-protected part (by WRP, PCROP or RDP Level 1) of the flash memory. Cleared by writing 1.
0x40022010 C   FIELD 05w01 PGAERR (rw): Programming alignment error Set by hardware when the data to program cannot be contained in the same double word (64-bit) flash memory in case of standard programming, or if there is a change of page during fast programming. Cleared by writing 1.
0x40022010 C   FIELD 06w01 SIZERR (rw): Size error Set by hardware when the size of the access is a byte or half-word during a program or a fast program sequence. Only double word programming is allowed (consequently: word access). Cleared by writing 1.
0x40022010 C   FIELD 07w01 PGSERR (rw): Programming sequence error Set by hardware when a write access to the flash memory is performed by the code while PG or FSTPG have not been set previously. Set also by hardware when PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous programming error. Cleared by writing 1.
0x40022010 C   FIELD 08w01 MISSERR (rw): Fast programming data miss error In Fast programming mode, 16 double words (128 bytes) must be sent to flash memory successively, and the new data must be sent to the logic control before the current data is fully programmed. MISSERR is set by hardware when the new data is not present in time. Cleared by writing 1.
0x40022010 C   FIELD 09w01 FASTERR (rw): Fast programming error Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted due to an error (alignment, size, write protection or data miss). The corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time. Cleared by writing 1.
0x40022010 C   FIELD 14w01 RDERR (rw): PCROP read error Set by hardware when an address to be read belongs to a read protected area of the flash memory (PCROP protection). An interrupt is generated if RDERRIE is set in FLASH_CR. Cleared by writing 1.
0x40022010 C   FIELD 15w01 OPTVERR (rw): Option and Engineering bits loading validity error
0x40022010 C   FIELD 16w01 BSY1 (ro): Busy This flag indicates that a flash memory operation requested by FLASH control register (FLASH_CR) is in progress. This bit is set at the beginning of the flash memory operation, and cleared when the operation finishes or when an error occurs.
0x40022010 C   FIELD 18w01 CFGBSY (ro): Programming or erase configuration busy. This flag is set and reset by hardware. For flash program operation, it is set when the first word is sent, and cleared after the second word is sent when the operation completes or ends with an error. For flash erase operation, it is set when setting the STRT bit of the FLASH_CR register and cleared when the operation completes or ends with an error. When set, a programming or erase operation is ongoing and the corresponding settings in the FLASH control register (FLASH_CR) are used (busy) and cannot be changed. Any other flash operation launch must be postponed. When cleared, the programming and erase settings in the FLASH control register (FLASH_CR) can be modified. Note: The CFGBSY bit is also set when attempting to write locked flash memory (with the first byte sent). When the CFGBSY bit is set, writing into the FLASH_CR register causes HardFault.To clear the CFGBSY bit, send a double word to the flash memory and wait until the access is finished (otherwise the CFGBSY bit remains set).
0x40022014 B  REGISTER CR (rw): FLASH control register
0x40022014 C   FIELD 00w01 PG (rw): Flash memory programming enable
0x40022014 C   FIELD 01w01 PER (rw): Page erase enable
0x40022014 C   FIELD 02w01 MER1 (rw): Mass erase When set, this bit triggers the mass erase, that is, all user pages.
0x40022014 C   FIELD 03w04 PNB (rw): Page number selection These bits select the page to erase: ... Note: Values corresponding to addresses outside the Main memory are not allowed. See Table 6 and Table 7.
0x40022014 C   FIELD 16w01 STRT (rw): Start erase operation This bit triggers an erase operation when set. This bit is possible to set only by software and to clear only by hardware. The hardware clears it when one of BSY1 and BSY2 flags in the FLASH_SR register transits to zero.
0x40022014 C   FIELD 17w01 OPTSTRT (rw): Start of modification of option bytes This bit triggers an options operation when set. This bit is set only by software, and is cleared when the BSY1 bit is cleared in FLASH_SR.
0x40022014 C   FIELD 18w01 FSTPG (rw): Fast programming enable
0x40022014 C   FIELD 24w01 EOPIE (rw): End-of-operation interrupt enable This bit enables the interrupt generation upon setting the EOP flag in the FLASH_SR register.
0x40022014 C   FIELD 25w01 ERRIE (rw): Error interrupt enable This bit enables the interrupt generation upon setting the OPERR flag in the FLASH_SR register.
0x40022014 C   FIELD 26w01 RDERRIE (rw): PCROP read error interrupt enable This bit enables the interrupt generation upon setting the RDERR flag in the FLASH_SR register.
0x40022014 C   FIELD 27w01 OBL_LAUNCH (rw): Option byte load launch When set, this bit triggers the load of option bytes into option registers. It is automatically cleared upon the completion of the load. The high state of the bit indicates pending option byte load. The bit cannot be cleared by software. It cannot be written as long as OPTLOCK is set.
0x40022014 C   FIELD 28w01 SEC_PROT (rw): Securable memory area protection enable This bit enables the protection on securable area, provided that a non-null securable memory area size (SEC_SIZE[4:0]) is defined in option bytes. This bit is possible to set only by software and to clear only through a system reset.
0x40022014 C   FIELD 30w01 OPTLOCK (rw): Options Lock This bit is set only. When set, all bits concerning user option in FLASH_CR register and so option page are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit must be cleared before doing the unlock sequence for OPTLOCK bit. In case of an unsuccessful unlock operation, this bit remains set until the next reset.
0x40022014 C   FIELD 31w01 LOCK (rw): FLASH_CR Lock This bit is set only. When set, the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence. In case of an unsuccessful unlock operation, this bit remains set until the next system reset.
0x40022020 B  REGISTER OPTR (rw): FLASH option register
0x40022020 C   FIELD 00w08 RDP (rw): Read protection level Other: Level 1, memories read protection active
0x40022020 C   FIELD 08w01 BOR_EN (rw): Brown out reset enable
0x40022020 C   FIELD 09w02 BORR_LEV (rw): BOR threshold at falling VDD supply Falling VDD crossings this threshold activates the reset signal.
0x40022020 C   FIELD 11w02 BORF_LEV (rw): BOR threshold at falling VDD supply Falling VDD crossings this threshold activates the reset signal.
0x40022020 C   FIELD 13w01 NRST_STOP (rw): None
0x40022020 C   FIELD 14w01 NRST_STDBY (rw): None
0x40022020 C   FIELD 15w01 NRST_SHDW (rw): None
0x40022020 C   FIELD 16w01 IWDG_SW (rw): None
0x40022020 C   FIELD 17w01 IWDG_STOP (rw): Independent watchdog counter freeze in Stop mode
0x40022020 C   FIELD 18w01 IWGD_STDBY (rw): None
0x40022020 C   FIELD 19w01 WWDG_SW (rw): Window watchdog selection
0x40022020 C   FIELD 21w01 HSE_NOT_REMAPPED (rw): HSE remapping enable/disable When cleared, the bit remaps the HSE clock source from PF0-OSC_IN/PF1-OSC_OUT pins to PC14-OSCX_IN/PC15-OSCX_OUT. Thus PC14-OSCX_IN/PC15-OSCX_OUT are shared by both LSE and HSE and the two clock sources cannot be use simultaneously. On packages with less than 48 pins, the remapping is always enabled (PF0-OSC_IN/PF1-OSC_OUT are not available), regardless of this bit. As all STM32C011xx packages have less than 48 pins, this bit is only applicable to STM32C031xx. Note: On 48 pins packages, when HSE_NOT_REMAPPED is reset, HSE cannot be used in bypass mode. Refer to product errata sheet for more details.
0x40022020 C   FIELD 22w01 RAM_PARITY_CHECK (rw): SRAM parity check control enable/disable
0x40022020 C   FIELD 23w01 SECURE_MUXING_EN (rw): Multiple-bonding security The bit allows enabling automatic I/O configuration to prevent conflicts on I/Os connected (bonded) onto the same pin. If the software sets one of the I/Os connected to the same pin as active by configuring the SYSCFG_CFGR3 register, enabling this bit automatically forces the other I/Os in digital input mode, regardless of their software configuration. When the bit is disabled, the SYSCFG_CFGR3 register setting is ignored, all GPIOs linked to a given pin are active and can be set in the mode specified by the corresponding GPIOx_MODER register. The user software must ensure that there is no conflict between GPIOs.
0x40022020 C   FIELD 24w01 NBOOT_SEL (rw): BOOT0 signal source selection This option bit defines the source of the BOOT0 signal.
0x40022020 C   FIELD 25w01 NBOOT1 (rw): Boot configuration Together with the BOOT0 pin or option bit nBOOT0 (depending on nBOOT_SEL option bit configuration), this bit selects boot mode from the Main flash memory, SRAM or the System memory. Refer to Section 3: Boot configuration.
0x40022020 C   FIELD 26w01 NBOOT0 (rw): nBOOT0 option bit
0x40022020 C   FIELD 27w02 NRST_MODE (rw): NRST pin configuration
0x40022020 C   FIELD 29w01 IRHEN (rw): Internal reset holder enable bit
0x40022024 B  REGISTER PCROP1ASR (rw): FLASH PCROP area A start address register
0x40022024 C   FIELD 00w06 PCROP1A_STRT (rw): PCROP1A area start offset Contains the offset of the first subpage of the PCROP1A area. Note: The number of effective bits depends on the size of the flash memory in the device.
0x40022028 B  REGISTER PCROP1AER (rw): FLASH PCROP area A end address register
0x40022028 C   FIELD 00w06 PCROP1A_END (rw): PCROP1A area end offset Contains the offset of the last subpage of the PCROP1A area. Note: The number of effective bits depends on the size of the flash memory in the device.
0x40022028 C   FIELD 31w01 PCROP_RDP (rw): PCROP area erase upon RDP level regression This bit determines whether the PCROP area (and the totality of the PCROP area boundary pages) is erased by the mass erase triggered by the RDP level regression from Level 1 to Level 0: The software can only set this bit. It is automatically reset upon mass erase following the RDP regression from Level 1 to Level 0.
0x4002202C B  REGISTER WRP1AR (rw): FLASH WRP area A address register
0x4002202C C   FIELD 00w04 WRP1A_STRT (rw): WRP area A start offset This bitfield contains the offset of the first page of the WRP area A. Note: The number of effective bits depends on the size of the flash memory in the device.
0x4002202C C   FIELD 16w04 WRP1A_END (rw): WRP area A end offset This bitfield contains the offset of the last page of the WRP area A. Note: The number of effective bits depends on the size of the flash memory in the device.
0x40022030 B  REGISTER WRP1BR (rw): FLASH WRP area B address register
0x40022030 C   FIELD 00w04 WRP1B_STRT (rw): WRP area B start offset This bitfield contains the offset of the first page of the WRP area B. Note: The number of effective bits depends on the size of the flash memory in the device.
0x40022030 C   FIELD 16w04 WRP1B_END (rw): WRP area B end offset This bitfield contains the offset of the last page of the WRP area B. Note: The number of effective bits depends on the size of the flash memory in the device.
0x40022034 B  REGISTER PCROP1BSR (rw): FLASH PCROP area B start address register
0x40022034 C   FIELD 00w06 PCROP1B_STRT (rw): PCROP1B area start offset Contains the offset of the first subpage of the PCROP1B area. Note: The number of effective bits depends on the size of the flash memory in the device.
0x40022038 B  REGISTER PCROP1BER (rw): FLASH PCROP area B end address register
0x40022038 C   FIELD 00w06 PCROP1B_END (rw): PCROP1B area end offset Contains the offset of the last subpage of the PCROP1B area. Note: The number of effective bits depends on the size of the flash memory in the device.
0x40022080 B  REGISTER SECR (rw): FLASH security register
0x40022080 C   FIELD 00w05 SEC_SIZE (rw): Securable memory area size Contains the number of securable flash memory pages. Note: The number of effective bits depends on the size of the flash memory in the device.
0x40022080 C   FIELD 16w01 BOOT_LOCK (rw): used to force boot from user area If the bit is set in association with RDP level 1, the debug capabilities are disabled, except in the case of a bad OBL (mismatch).
0x40023000 A PERIPHERAL CRC
0x40023000 B  REGISTER DR: CRC data register
0x40023000 C   FIELD 00w32 DR (rw): Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value.
0x40023004 B  REGISTER IDR: CRC independent data register
0x40023004 C   FIELD 00w32 GPDR (rw): General-purpose 32-bit data register bits These bits can be used as a temporary storage location for four bytes. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register
0x40023008 B  REGISTER CR: CRC control register
0x40023008 C   FIELD 00w01 RESET (rw): RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware
0x40023008 C   FIELD 03w02 POLYSIZE (rw): Polynomial size These bits control the size of the polynomial.
0x40023008 C   FIELD 05w02 REV_IN (rw): Reverse input data These bits control the reversal of the bit order of the input data
0x40023008 C   FIELD 07w01 REV_OUT (rw): Reverse output data This bit controls the reversal of the bit order of the output data.
0x40023010 B  REGISTER INIT: CRC initial value
0x40023010 C   FIELD 00w32 CRC_INIT (rw): Programmable initial CRC value This register is used to write the CRC initial value.
0x40023014 B  REGISTER POL: CRC polynomial
0x40023014 C   FIELD 00w32 POL (rw): Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value.
0x50000000 A PERIPHERAL GPIOA
0x50000000 B  REGISTER MODER: GPIO port mode register
0x50000000 C   FIELD 00w02 MODE0 (rw): Port x configuration pin 0
0x50000000 C   FIELD 02w02 MODE1 (rw): Port x configuration pin 1
0x50000000 C   FIELD 04w02 MODE2 (rw): Port x configuration pin 2
0x50000000 C   FIELD 06w02 MODE3 (rw): Port x configuration pin 3
0x50000000 C   FIELD 08w02 MODE4 (rw): Port x configuration pin 4
0x50000000 C   FIELD 10w02 MODE5 (rw): Port x configuration pin 5
0x50000000 C   FIELD 12w02 MODE6 (rw): Port x configuration pin 6
0x50000000 C   FIELD 14w02 MODE7 (rw): Port x configuration pin 7
0x50000000 C   FIELD 16w02 MODE8 (rw): Port x configuration pin 8
0x50000000 C   FIELD 18w02 MODE9 (rw): Port x configuration pin 9
0x50000000 C   FIELD 20w02 MODE10 (rw): Port x configuration pin 10
0x50000000 C   FIELD 22w02 MODE11 (rw): Port x configuration pin 11
0x50000000 C   FIELD 24w02 MODE12 (rw): Port x configuration pin 12
0x50000000 C   FIELD 26w02 MODE13 (rw): Port x configuration pin 13
0x50000000 C   FIELD 28w02 MODE14 (rw): Port x configuration pin 14
0x50000000 C   FIELD 30w02 MODE15 (rw): Port x configuration pin 15
0x50000004 B  REGISTER OTYPER: GPIO port output type register
0x50000004 C   FIELD 00w01 OT0 (rw): Port x configuration pin 0
0x50000004 C   FIELD 01w01 OT1 (rw): Port x configuration pin 1
0x50000004 C   FIELD 02w01 OT2 (rw): Port x configuration pin 2
0x50000004 C   FIELD 03w01 OT3 (rw): Port x configuration pin 3
0x50000004 C   FIELD 04w01 OT4 (rw): Port x configuration pin 4
0x50000004 C   FIELD 05w01 OT5 (rw): Port x configuration pin 5
0x50000004 C   FIELD 06w01 OT6 (rw): Port x configuration pin 6
0x50000004 C   FIELD 07w01 OT7 (rw): Port x configuration pin 7
0x50000004 C   FIELD 08w01 OT8 (rw): Port x configuration pin 8
0x50000004 C   FIELD 09w01 OT9 (rw): Port x configuration pin 9
0x50000004 C   FIELD 10w01 OT10 (rw): Port x configuration pin 10
0x50000004 C   FIELD 11w01 OT11 (rw): Port x configuration pin 11
0x50000004 C   FIELD 12w01 OT12 (rw): Port x configuration pin 12
0x50000004 C   FIELD 13w01 OT13 (rw): Port x configuration pin 13
0x50000004 C   FIELD 14w01 OT14 (rw): Port x configuration pin 14
0x50000004 C   FIELD 15w01 OT15 (rw): Port x configuration pin 15
0x50000008 B  REGISTER OSPEEDR: GPIO port output speed register
0x50000008 C   FIELD 00w02 OSPEED0 (rw): Port x configuration pin 0
0x50000008 C   FIELD 02w02 OSPEED1 (rw): Port x configuration pin 1
0x50000008 C   FIELD 04w02 OSPEED2 (rw): Port x configuration pin 2
0x50000008 C   FIELD 06w02 OSPEED3 (rw): Port x configuration pin 3
0x50000008 C   FIELD 08w02 OSPEED4 (rw): Port x configuration pin 4
0x50000008 C   FIELD 10w02 OSPEED5 (rw): Port x configuration pin 5
0x50000008 C   FIELD 12w02 OSPEED6 (rw): Port x configuration pin 6
0x50000008 C   FIELD 14w02 OSPEED7 (rw): Port x configuration pin 7
0x50000008 C   FIELD 16w02 OSPEED8 (rw): Port x configuration pin 8
0x50000008 C   FIELD 18w02 OSPEED9 (rw): Port x configuration pin 9
0x50000008 C   FIELD 20w02 OSPEED10 (rw): Port x configuration pin 10
0x50000008 C   FIELD 22w02 OSPEED11 (rw): Port x configuration pin 11
0x50000008 C   FIELD 24w02 OSPEED12 (rw): Port x configuration pin 12
0x50000008 C   FIELD 26w02 OSPEED13 (rw): Port x configuration pin 13
0x50000008 C   FIELD 28w02 OSPEED14 (rw): Port x configuration pin 14
0x50000008 C   FIELD 30w02 OSPEED15 (rw): Port x configuration pin 15
0x5000000C B  REGISTER PUPDR: GPIO port pull-up/pull-down register
0x5000000C C   FIELD 00w02 PUPD0 (rw): Port x configuration pin 0
0x5000000C C   FIELD 02w02 PUPD1 (rw): Port x configuration pin 1
0x5000000C C   FIELD 04w02 PUPD2 (rw): Port x configuration pin 2
0x5000000C C   FIELD 06w02 PUPD3 (rw): Port x configuration pin 3
0x5000000C C   FIELD 08w02 PUPD4 (rw): Port x configuration pin 4
0x5000000C C   FIELD 10w02 PUPD5 (rw): Port x configuration pin 5
0x5000000C C   FIELD 12w02 PUPD6 (rw): Port x configuration pin 6
0x5000000C C   FIELD 14w02 PUPD7 (rw): Port x configuration pin 7
0x5000000C C   FIELD 16w02 PUPD8 (rw): Port x configuration pin 8
0x5000000C C   FIELD 18w02 PUPD9 (rw): Port x configuration pin 9
0x5000000C C   FIELD 20w02 PUPD10 (rw): Port x configuration pin 10
0x5000000C C   FIELD 22w02 PUPD11 (rw): Port x configuration pin 11
0x5000000C C   FIELD 24w02 PUPD12 (rw): Port x configuration pin 12
0x5000000C C   FIELD 26w02 PUPD13 (rw): Port x configuration pin 13
0x5000000C C   FIELD 28w02 PUPD14 (rw): Port x configuration pin 14
0x5000000C C   FIELD 30w02 PUPD15 (rw): Port x configuration pin 15
0x50000010 B  REGISTER IDR: GPIO port input data register
0x50000010 C   FIELD 00w01 ID0 (ro): Port input data pin 0
0x50000010 C   FIELD 01w01 ID1 (ro): Port input data pin 1
0x50000010 C   FIELD 02w01 ID2 (ro): Port input data pin 2
0x50000010 C   FIELD 03w01 ID3 (ro): Port input data pin 3
0x50000010 C   FIELD 04w01 ID4 (ro): Port input data pin 4
0x50000010 C   FIELD 05w01 ID5 (ro): Port input data pin 5
0x50000010 C   FIELD 06w01 ID6 (ro): Port input data pin 6
0x50000010 C   FIELD 07w01 ID7 (ro): Port input data pin 7
0x50000010 C   FIELD 08w01 ID8 (ro): Port input data pin 8
0x50000010 C   FIELD 09w01 ID9 (ro): Port input data pin 9
0x50000010 C   FIELD 10w01 ID10 (ro): Port input data pin 10
0x50000010 C   FIELD 11w01 ID11 (ro): Port input data pin 11
0x50000010 C   FIELD 12w01 ID12 (ro): Port input data pin 12
0x50000010 C   FIELD 13w01 ID13 (ro): Port input data pin 13
0x50000010 C   FIELD 14w01 ID14 (ro): Port input data pin 14
0x50000010 C   FIELD 15w01 ID15 (ro): Port input data pin 15
0x50000014 B  REGISTER ODR: GPIO port output data register
0x50000014 C   FIELD 00w01 OD0 (rw): Port output data pin 0
0x50000014 C   FIELD 01w01 OD1 (rw): Port output data pin 1
0x50000014 C   FIELD 02w01 OD2 (rw): Port output data pin 2
0x50000014 C   FIELD 03w01 OD3 (rw): Port output data pin 3
0x50000014 C   FIELD 04w01 OD4 (rw): Port output data pin 4
0x50000014 C   FIELD 05w01 OD5 (rw): Port output data pin 5
0x50000014 C   FIELD 06w01 OD6 (rw): Port output data pin 6
0x50000014 C   FIELD 07w01 OD7 (rw): Port output data pin 7
0x50000014 C   FIELD 08w01 OD8 (rw): Port output data pin 8
0x50000014 C   FIELD 09w01 OD9 (rw): Port output data pin 9
0x50000014 C   FIELD 10w01 OD10 (rw): Port output data pin 10
0x50000014 C   FIELD 11w01 OD11 (rw): Port output data pin 11
0x50000014 C   FIELD 12w01 OD12 (rw): Port output data pin 12
0x50000014 C   FIELD 13w01 OD13 (rw): Port output data pin 13
0x50000014 C   FIELD 14w01 OD14 (rw): Port output data pin 14
0x50000014 C   FIELD 15w01 OD15 (rw): Port output data pin 15
0x50000018 B  REGISTER BSRR: GPIO port bit set/reset register
0x50000018 C   FIELD 00w01 BS0 (wo): Port x set pin 0
0x50000018 C   FIELD 01w01 BS1 (wo): Port x set pin 1
0x50000018 C   FIELD 02w01 BS2 (wo): Port x set pin 2
0x50000018 C   FIELD 03w01 BS3 (wo): Port x set pin 3
0x50000018 C   FIELD 04w01 BS4 (wo): Port x set pin 4
0x50000018 C   FIELD 05w01 BS5 (wo): Port x set pin 5
0x50000018 C   FIELD 06w01 BS6 (wo): Port x set pin 6
0x50000018 C   FIELD 07w01 BS7 (wo): Port x set pin 7
0x50000018 C   FIELD 08w01 BS8 (wo): Port x set pin 8
0x50000018 C   FIELD 09w01 BS9 (wo): Port x set pin 9
0x50000018 C   FIELD 10w01 BS10 (wo): Port x set pin 10
0x50000018 C   FIELD 11w01 BS11 (wo): Port x set pin 11
0x50000018 C   FIELD 12w01 BS12 (wo): Port x set pin 12
0x50000018 C   FIELD 13w01 BS13 (wo): Port x set pin 13
0x50000018 C   FIELD 14w01 BS14 (wo): Port x set pin 14
0x50000018 C   FIELD 15w01 BS15 (wo): Port x set pin 15
0x50000018 C   FIELD 16w01 BR0 (wo): Port x reset pin 0
0x50000018 C   FIELD 17w01 BR1 (wo): Port x reset pin 1
0x50000018 C   FIELD 18w01 BR2 (wo): Port x reset pin 2
0x50000018 C   FIELD 19w01 BR3 (wo): Port x reset pin 3
0x50000018 C   FIELD 20w01 BR4 (wo): Port x reset pin 4
0x50000018 C   FIELD 21w01 BR5 (wo): Port x reset pin 5
0x50000018 C   FIELD 22w01 BR6 (wo): Port x reset pin 6
0x50000018 C   FIELD 23w01 BR7 (wo): Port x reset pin 7
0x50000018 C   FIELD 24w01 BR8 (wo): Port x reset pin 8
0x50000018 C   FIELD 25w01 BR9 (wo): Port x reset pin 9
0x50000018 C   FIELD 26w01 BR10 (wo): Port x reset pin 10
0x50000018 C   FIELD 27w01 BR11 (wo): Port x reset pin 11
0x50000018 C   FIELD 28w01 BR12 (wo): Port x reset pin 12
0x50000018 C   FIELD 29w01 BR13 (wo): Port x reset pin 13
0x50000018 C   FIELD 30w01 BR14 (wo): Port x reset pin 14
0x50000018 C   FIELD 31w01 BR15 (wo): Port x reset pin 15
0x5000001C B  REGISTER LCKR: GPIO port configuration lock register
0x5000001C C   FIELD 00w01 LCK0 (rw): Port x lock pin 0
0x5000001C C   FIELD 01w01 LCK1 (rw): Port x lock pin 1
0x5000001C C   FIELD 02w01 LCK2 (rw): Port x lock pin 2
0x5000001C C   FIELD 03w01 LCK3 (rw): Port x lock pin 3
0x5000001C C   FIELD 04w01 LCK4 (rw): Port x lock pin 4
0x5000001C C   FIELD 05w01 LCK5 (rw): Port x lock pin 5
0x5000001C C   FIELD 06w01 LCK6 (rw): Port x lock pin 6
0x5000001C C   FIELD 07w01 LCK7 (rw): Port x lock pin 7
0x5000001C C   FIELD 08w01 LCK8 (rw): Port x lock pin 8
0x5000001C C   FIELD 09w01 LCK9 (rw): Port x lock pin 9
0x5000001C C   FIELD 10w01 LCK10 (rw): Port x lock pin 10
0x5000001C C   FIELD 11w01 LCK11 (rw): Port x lock pin 11
0x5000001C C   FIELD 12w01 LCK12 (rw): Port x lock pin 12
0x5000001C C   FIELD 13w01 LCK13 (rw): Port x lock pin 13
0x5000001C C   FIELD 14w01 LCK14 (rw): Port x lock pin 14
0x5000001C C   FIELD 15w01 LCK15 (rw): Port x lock pin 15
0x5000001C C   FIELD 16w01 LCKK (rw): Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset.
0x50000020 B  REGISTER AFRL: GPIO alternate function low register
0x50000020 C   FIELD 00w04 AFREL0 (rw): Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os
0x50000020 C   FIELD 04w04 AFREL1 (rw): Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os
0x50000020 C   FIELD 08w04 AFREL2 (rw): Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os
0x50000020 C   FIELD 12w04 AFREL3 (rw): Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os
0x50000020 C   FIELD 16w04 AFREL4 (rw): Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os
0x50000020 C   FIELD 20w04 AFREL5 (rw): Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os
0x50000020 C   FIELD 24w04 AFREL6 (rw): Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os
0x50000020 C   FIELD 28w04 AFREL7 (rw): Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os
0x50000024 B  REGISTER AFRH: GPIO alternate function high register
0x50000024 C   FIELD 00w04 AFREL8 (=GPIOA.AFRL.AFR%s) (rw): Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os
0x50000024 C   FIELD 04w04 AFREL9 (=GPIOA.AFRL.AFR%s) (rw): Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os
0x50000024 C   FIELD 08w04 AFREL10 (=GPIOA.AFRL.AFR%s) (rw): Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os
0x50000024 C   FIELD 12w04 AFREL11 (=GPIOA.AFRL.AFR%s) (rw): Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os
0x50000024 C   FIELD 16w04 AFREL12 (=GPIOA.AFRL.AFR%s) (rw): Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os
0x50000024 C   FIELD 20w04 AFREL13 (=GPIOA.AFRL.AFR%s) (rw): Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os
0x50000024 C   FIELD 24w04 AFREL14 (=GPIOA.AFRL.AFR%s) (rw): Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os
0x50000024 C   FIELD 28w04 AFREL15 (=GPIOA.AFRL.AFR%s) (rw): Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os
0x50000028 B  REGISTER BRR: GPIO port bit reset register
0x50000028 C   FIELD 00w01 BR0 (wo): Port x reset pin 0
0x50000028 C   FIELD 01w01 BR1 (wo): Port x reset pin 1
0x50000028 C   FIELD 02w01 BR2 (wo): Port x reset pin 2
0x50000028 C   FIELD 03w01 BR3 (wo): Port x reset pin 3
0x50000028 C   FIELD 04w01 BR4 (wo): Port x reset pin 4
0x50000028 C   FIELD 05w01 BR5 (wo): Port x reset pin 5
0x50000028 C   FIELD 06w01 BR6 (wo): Port x reset pin 6
0x50000028 C   FIELD 07w01 BR7 (wo): Port x reset pin 7
0x50000028 C   FIELD 08w01 BR8 (wo): Port x reset pin 8
0x50000028 C   FIELD 09w01 BR9 (wo): Port x reset pin 9
0x50000028 C   FIELD 10w01 BR10 (wo): Port x reset pin 10
0x50000028 C   FIELD 11w01 BR11 (wo): Port x reset pin 11
0x50000028 C   FIELD 12w01 BR12 (wo): Port x reset pin 12
0x50000028 C   FIELD 13w01 BR13 (wo): Port x reset pin 13
0x50000028 C   FIELD 14w01 BR14 (wo): Port x reset pin 14
0x50000028 C   FIELD 15w01 BR15 (wo): Port x reset pin 15
0x50000400 A PERIPHERAL GPIOB
0x50000400 B  REGISTER MODER: GPIO port mode register
0x50000400 C   FIELD 00w02 MODE0 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 0
0x50000400 C   FIELD 02w02 MODE1 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 1
0x50000400 C   FIELD 04w02 MODE2 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 2
0x50000400 C   FIELD 06w02 MODE3 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 3
0x50000400 C   FIELD 08w02 MODE4 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 4
0x50000400 C   FIELD 10w02 MODE5 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 5
0x50000400 C   FIELD 12w02 MODE6 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 6
0x50000400 C   FIELD 14w02 MODE7 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 7
0x50000400 C   FIELD 16w02 MODE8 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 8
0x50000400 C   FIELD 18w02 MODE9 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 9
0x50000400 C   FIELD 20w02 MODE10 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 10
0x50000400 C   FIELD 22w02 MODE11 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 11
0x50000400 C   FIELD 24w02 MODE12 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 12
0x50000400 C   FIELD 26w02 MODE13 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 13
0x50000400 C   FIELD 28w02 MODE14 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 14
0x50000400 C   FIELD 30w02 MODE15 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 15
0x50000404 B  REGISTER OTYPER (=GPIOA.OTYPER): GPIO port output type register
0x50000408 B  REGISTER OSPEEDR: GPIO port output speed register
0x50000408 C   FIELD 00w02 OSPEED0 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 0
0x50000408 C   FIELD 02w02 OSPEED1 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 1
0x50000408 C   FIELD 04w02 OSPEED2 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 2
0x50000408 C   FIELD 06w02 OSPEED3 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 3
0x50000408 C   FIELD 08w02 OSPEED4 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 4
0x50000408 C   FIELD 10w02 OSPEED5 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 5
0x50000408 C   FIELD 12w02 OSPEED6 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 6
0x50000408 C   FIELD 14w02 OSPEED7 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 7
0x50000408 C   FIELD 16w02 OSPEED8 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 8
0x50000408 C   FIELD 18w02 OSPEED9 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 9
0x50000408 C   FIELD 20w02 OSPEED10 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 10
0x50000408 C   FIELD 22w02 OSPEED11 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 11
0x50000408 C   FIELD 24w02 OSPEED12 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 12
0x50000408 C   FIELD 26w02 OSPEED13 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 13
0x50000408 C   FIELD 28w02 OSPEED14 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 14
0x50000408 C   FIELD 30w02 OSPEED15 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 15
0x5000040C B  REGISTER PUPDR: GPIO port pull-up/pull-down register
0x5000040C C   FIELD 00w02 PUPD0 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 0
0x5000040C C   FIELD 02w02 PUPD1 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 1
0x5000040C C   FIELD 04w02 PUPD2 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 2
0x5000040C C   FIELD 06w02 PUPD3 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 3
0x5000040C C   FIELD 08w02 PUPD4 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 4
0x5000040C C   FIELD 10w02 PUPD5 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 5
0x5000040C C   FIELD 12w02 PUPD6 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 6
0x5000040C C   FIELD 14w02 PUPD7 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 7
0x5000040C C   FIELD 16w02 PUPD8 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 8
0x5000040C C   FIELD 18w02 PUPD9 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 9
0x5000040C C   FIELD 20w02 PUPD10 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 10
0x5000040C C   FIELD 22w02 PUPD11 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 11
0x5000040C C   FIELD 24w02 PUPD12 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 12
0x5000040C C   FIELD 26w02 PUPD13 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 13
0x5000040C C   FIELD 28w02 PUPD14 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 14
0x5000040C C   FIELD 30w02 PUPD15 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 15
0x50000410 B  REGISTER IDR (=GPIOA.IDR): GPIO port input data register
0x50000414 B  REGISTER ODR (=GPIOA.ODR): GPIO port output data register
0x50000418 B  REGISTER BSRR (=GPIOA.BSRR): GPIO port bit set/reset register
0x5000041C B  REGISTER LCKR (=GPIOA.LCKR): GPIO port configuration lock register
0x50000420 B  REGISTER AFRL (=GPIOA.AFRL): GPIO alternate function low register
0x50000424 B  REGISTER AFRH (=GPIOA.AFRH): GPIO alternate function high register
0x50000428 B  REGISTER BRR (=GPIOA.BRR): GPIO port bit reset register
0x50000800 A PERIPHERAL GPIOC
0x50000800 B  REGISTER MODER: GPIO port mode register
0x50000800 C   FIELD 00w02 MODE0 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 0
0x50000800 C   FIELD 02w02 MODE1 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 1
0x50000800 C   FIELD 04w02 MODE2 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 2
0x50000800 C   FIELD 06w02 MODE3 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 3
0x50000800 C   FIELD 08w02 MODE4 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 4
0x50000800 C   FIELD 10w02 MODE5 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 5
0x50000800 C   FIELD 12w02 MODE6 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 6
0x50000800 C   FIELD 14w02 MODE7 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 7
0x50000800 C   FIELD 16w02 MODE8 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 8
0x50000800 C   FIELD 18w02 MODE9 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 9
0x50000800 C   FIELD 20w02 MODE10 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 10
0x50000800 C   FIELD 22w02 MODE11 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 11
0x50000800 C   FIELD 24w02 MODE12 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 12
0x50000800 C   FIELD 26w02 MODE13 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 13
0x50000800 C   FIELD 28w02 MODE14 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 14
0x50000800 C   FIELD 30w02 MODE15 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 15
0x50000804 B  REGISTER OTYPER (=GPIOA.OTYPER): GPIO port output type register
0x50000808 B  REGISTER OSPEEDR: GPIO port output speed register
0x50000808 C   FIELD 00w02 OSPEED0 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 0
0x50000808 C   FIELD 02w02 OSPEED1 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 1
0x50000808 C   FIELD 04w02 OSPEED2 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 2
0x50000808 C   FIELD 06w02 OSPEED3 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 3
0x50000808 C   FIELD 08w02 OSPEED4 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 4
0x50000808 C   FIELD 10w02 OSPEED5 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 5
0x50000808 C   FIELD 12w02 OSPEED6 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 6
0x50000808 C   FIELD 14w02 OSPEED7 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 7
0x50000808 C   FIELD 16w02 OSPEED8 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 8
0x50000808 C   FIELD 18w02 OSPEED9 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 9
0x50000808 C   FIELD 20w02 OSPEED10 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 10
0x50000808 C   FIELD 22w02 OSPEED11 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 11
0x50000808 C   FIELD 24w02 OSPEED12 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 12
0x50000808 C   FIELD 26w02 OSPEED13 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 13
0x50000808 C   FIELD 28w02 OSPEED14 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 14
0x50000808 C   FIELD 30w02 OSPEED15 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 15
0x5000080C B  REGISTER PUPDR: GPIO port pull-up/pull-down register
0x5000080C C   FIELD 00w02 PUPD0 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 0
0x5000080C C   FIELD 02w02 PUPD1 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 1
0x5000080C C   FIELD 04w02 PUPD2 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 2
0x5000080C C   FIELD 06w02 PUPD3 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 3
0x5000080C C   FIELD 08w02 PUPD4 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 4
0x5000080C C   FIELD 10w02 PUPD5 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 5
0x5000080C C   FIELD 12w02 PUPD6 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 6
0x5000080C C   FIELD 14w02 PUPD7 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 7
0x5000080C C   FIELD 16w02 PUPD8 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 8
0x5000080C C   FIELD 18w02 PUPD9 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 9
0x5000080C C   FIELD 20w02 PUPD10 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 10
0x5000080C C   FIELD 22w02 PUPD11 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 11
0x5000080C C   FIELD 24w02 PUPD12 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 12
0x5000080C C   FIELD 26w02 PUPD13 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 13
0x5000080C C   FIELD 28w02 PUPD14 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 14
0x5000080C C   FIELD 30w02 PUPD15 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 15
0x50000810 B  REGISTER IDR (=GPIOA.IDR): GPIO port input data register
0x50000814 B  REGISTER ODR (=GPIOA.ODR): GPIO port output data register
0x50000818 B  REGISTER BSRR (=GPIOA.BSRR): GPIO port bit set/reset register
0x5000081C B  REGISTER LCKR (=GPIOA.LCKR): GPIO port configuration lock register
0x50000820 B  REGISTER AFRL (=GPIOA.AFRL): GPIO alternate function low register
0x50000824 B  REGISTER AFRH (=GPIOA.AFRH): GPIO alternate function high register
0x50000828 B  REGISTER BRR (=GPIOA.BRR): GPIO port bit reset register
0x50000C00 A PERIPHERAL GPIOD
0x50000C00 B  REGISTER MODER: GPIO port mode register
0x50000C00 C   FIELD 00w02 MODE0 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 0
0x50000C00 C   FIELD 02w02 MODE1 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 1
0x50000C00 C   FIELD 04w02 MODE2 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 2
0x50000C00 C   FIELD 06w02 MODE3 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 3
0x50000C00 C   FIELD 08w02 MODE4 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 4
0x50000C00 C   FIELD 10w02 MODE5 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 5
0x50000C00 C   FIELD 12w02 MODE6 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 6
0x50000C00 C   FIELD 14w02 MODE7 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 7
0x50000C00 C   FIELD 16w02 MODE8 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 8
0x50000C00 C   FIELD 18w02 MODE9 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 9
0x50000C00 C   FIELD 20w02 MODE10 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 10
0x50000C00 C   FIELD 22w02 MODE11 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 11
0x50000C00 C   FIELD 24w02 MODE12 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 12
0x50000C00 C   FIELD 26w02 MODE13 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 13
0x50000C00 C   FIELD 28w02 MODE14 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 14
0x50000C00 C   FIELD 30w02 MODE15 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 15
0x50000C04 B  REGISTER OTYPER (=GPIOA.OTYPER): GPIO port output type register
0x50000C08 B  REGISTER OSPEEDR: GPIO port output speed register
0x50000C08 C   FIELD 00w02 OSPEED0 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 0
0x50000C08 C   FIELD 02w02 OSPEED1 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 1
0x50000C08 C   FIELD 04w02 OSPEED2 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 2
0x50000C08 C   FIELD 06w02 OSPEED3 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 3
0x50000C08 C   FIELD 08w02 OSPEED4 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 4
0x50000C08 C   FIELD 10w02 OSPEED5 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 5
0x50000C08 C   FIELD 12w02 OSPEED6 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 6
0x50000C08 C   FIELD 14w02 OSPEED7 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 7
0x50000C08 C   FIELD 16w02 OSPEED8 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 8
0x50000C08 C   FIELD 18w02 OSPEED9 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 9
0x50000C08 C   FIELD 20w02 OSPEED10 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 10
0x50000C08 C   FIELD 22w02 OSPEED11 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 11
0x50000C08 C   FIELD 24w02 OSPEED12 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 12
0x50000C08 C   FIELD 26w02 OSPEED13 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 13
0x50000C08 C   FIELD 28w02 OSPEED14 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 14
0x50000C08 C   FIELD 30w02 OSPEED15 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 15
0x50000C0C B  REGISTER PUPDR: GPIO port pull-up/pull-down register
0x50000C0C C   FIELD 00w02 PUPD0 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 0
0x50000C0C C   FIELD 02w02 PUPD1 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 1
0x50000C0C C   FIELD 04w02 PUPD2 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 2
0x50000C0C C   FIELD 06w02 PUPD3 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 3
0x50000C0C C   FIELD 08w02 PUPD4 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 4
0x50000C0C C   FIELD 10w02 PUPD5 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 5
0x50000C0C C   FIELD 12w02 PUPD6 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 6
0x50000C0C C   FIELD 14w02 PUPD7 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 7
0x50000C0C C   FIELD 16w02 PUPD8 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 8
0x50000C0C C   FIELD 18w02 PUPD9 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 9
0x50000C0C C   FIELD 20w02 PUPD10 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 10
0x50000C0C C   FIELD 22w02 PUPD11 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 11
0x50000C0C C   FIELD 24w02 PUPD12 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 12
0x50000C0C C   FIELD 26w02 PUPD13 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 13
0x50000C0C C   FIELD 28w02 PUPD14 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 14
0x50000C0C C   FIELD 30w02 PUPD15 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 15
0x50000C10 B  REGISTER IDR (=GPIOA.IDR): GPIO port input data register
0x50000C14 B  REGISTER ODR (=GPIOA.ODR): GPIO port output data register
0x50000C18 B  REGISTER BSRR (=GPIOA.BSRR): GPIO port bit set/reset register
0x50000C1C B  REGISTER LCKR (=GPIOA.LCKR): GPIO port configuration lock register
0x50000C20 B  REGISTER AFRL (=GPIOA.AFRL): GPIO alternate function low register
0x50000C24 B  REGISTER AFRH (=GPIOA.AFRH): GPIO alternate function high register
0x50000C28 B  REGISTER BRR (=GPIOA.BRR): GPIO port bit reset register
0x50001400 A PERIPHERAL GPIOF
0x50001400 B  REGISTER MODER: GPIO port mode register
0x50001400 C   FIELD 00w02 MODE0 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 0
0x50001400 C   FIELD 02w02 MODE1 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 1
0x50001400 C   FIELD 04w02 MODE2 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 2
0x50001400 C   FIELD 06w02 MODE3 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 3
0x50001400 C   FIELD 08w02 MODE4 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 4
0x50001400 C   FIELD 10w02 MODE5 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 5
0x50001400 C   FIELD 12w02 MODE6 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 6
0x50001400 C   FIELD 14w02 MODE7 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 7
0x50001400 C   FIELD 16w02 MODE8 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 8
0x50001400 C   FIELD 18w02 MODE9 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 9
0x50001400 C   FIELD 20w02 MODE10 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 10
0x50001400 C   FIELD 22w02 MODE11 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 11
0x50001400 C   FIELD 24w02 MODE12 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 12
0x50001400 C   FIELD 26w02 MODE13 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 13
0x50001400 C   FIELD 28w02 MODE14 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 14
0x50001400 C   FIELD 30w02 MODE15 (=GPIOA.MODER.MODE%s) (rw): Port x configuration pin 15
0x50001404 B  REGISTER OTYPER (=GPIOA.OTYPER): GPIO port output type register
0x50001408 B  REGISTER OSPEEDR: GPIO port output speed register
0x50001408 C   FIELD 00w02 OSPEED0 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 0
0x50001408 C   FIELD 02w02 OSPEED1 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 1
0x50001408 C   FIELD 04w02 OSPEED2 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 2
0x50001408 C   FIELD 06w02 OSPEED3 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 3
0x50001408 C   FIELD 08w02 OSPEED4 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 4
0x50001408 C   FIELD 10w02 OSPEED5 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 5
0x50001408 C   FIELD 12w02 OSPEED6 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 6
0x50001408 C   FIELD 14w02 OSPEED7 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 7
0x50001408 C   FIELD 16w02 OSPEED8 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 8
0x50001408 C   FIELD 18w02 OSPEED9 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 9
0x50001408 C   FIELD 20w02 OSPEED10 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 10
0x50001408 C   FIELD 22w02 OSPEED11 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 11
0x50001408 C   FIELD 24w02 OSPEED12 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 12
0x50001408 C   FIELD 26w02 OSPEED13 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 13
0x50001408 C   FIELD 28w02 OSPEED14 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 14
0x50001408 C   FIELD 30w02 OSPEED15 (=GPIOA.OSPEEDR.OSPEED%s) (rw): Port x configuration pin 15
0x5000140C B  REGISTER PUPDR: GPIO port pull-up/pull-down register
0x5000140C C   FIELD 00w02 PUPD0 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 0
0x5000140C C   FIELD 02w02 PUPD1 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 1
0x5000140C C   FIELD 04w02 PUPD2 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 2
0x5000140C C   FIELD 06w02 PUPD3 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 3
0x5000140C C   FIELD 08w02 PUPD4 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 4
0x5000140C C   FIELD 10w02 PUPD5 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 5
0x5000140C C   FIELD 12w02 PUPD6 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 6
0x5000140C C   FIELD 14w02 PUPD7 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 7
0x5000140C C   FIELD 16w02 PUPD8 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 8
0x5000140C C   FIELD 18w02 PUPD9 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 9
0x5000140C C   FIELD 20w02 PUPD10 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 10
0x5000140C C   FIELD 22w02 PUPD11 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 11
0x5000140C C   FIELD 24w02 PUPD12 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 12
0x5000140C C   FIELD 26w02 PUPD13 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 13
0x5000140C C   FIELD 28w02 PUPD14 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 14
0x5000140C C   FIELD 30w02 PUPD15 (=GPIOA.PUPDR.PUPD%s) (rw): Port x configuration pin 15
0x50001410 B  REGISTER IDR (=GPIOA.IDR): GPIO port input data register
0x50001414 B  REGISTER ODR (=GPIOA.ODR): GPIO port output data register
0x50001418 B  REGISTER BSRR (=GPIOA.BSRR): GPIO port bit set/reset register
0x5000141C B  REGISTER LCKR (=GPIOA.LCKR): GPIO port configuration lock register
0x50001420 B  REGISTER AFRL (=GPIOA.AFRL): GPIO alternate function low register
0x50001424 B  REGISTER AFRH (=GPIOA.AFRH): GPIO alternate function high register
0x50001428 B  REGISTER BRR (=GPIOA.BRR): GPIO port bit reset register
INTERRUPT 000: WWDG (WWDG): Window watchdog interrupt
INTERRUPT 001: PVM (EXTI): VDDIO2 monitor interrupt (EXTI line 34
INTERRUPT 002: RTC (RTC): RTC interrupts (EXTI lines 19)
INTERRUPT 003: FLASH (FLASH): Flash global interrupt
INTERRUPT 004: RCC (RCC): RCC global interrupt
INTERRUPT 005: EXTI0_1 (EXTI): EXTI line 0 and 1 interrupt
INTERRUPT 006: EXTI2_3 (EXTI): EXTI line 2 and 3 interrupt
INTERRUPT 007: EXTI4_15 (EXTI): EXTI line 4 and 15 interrupt
INTERRUPT 009: DMA1_Channel1 (DMA): DMA1 channel 1 interrupt
INTERRUPT 010: DMA1_Channel2_3 (DMA): DMA1 channel 2 and 3 interrupts
INTERRUPT 011: DMAMUX_DMA1_Channel4_5 (DMAMUX): DMAMUX and DMA1 channel 4 and 5 interrupts
INTERRUPT 012: ADC (ADC): ADC interrupt
INTERRUPT 013: TIM1_BRK_UP_TRG_COM (TIM1): TIM1 break, update, trigger and commutation interrupts
INTERRUPT 014: TIM1_CC (TIM1): TIM1 Capture Compare interrupt
INTERRUPT 016: TIM3 (TIM3): TIM3 gloabal interrupt
INTERRUPT 019: TIM14 (TIM14): TIM14 gloabal interrupt
INTERRUPT 021: TIM16 (TIM16): TIM16 global interrupt
INTERRUPT 022: TIM17 (TIM17): TIM17 global interrupt
INTERRUPT 023: I2C1 (I2C1): global interrupt (combined with EXTI 23)
INTERRUPT 025: SPI1 (SPI1): SPI1/I2S1 global interrupt
INTERRUPT 027: USART1 (USART1): USART1 global interrupt (combined with EXTI 25)
INTERRUPT 028: USART2 (USART2): USART2 global interrupt (combined with EXTI 25)