Update GDB settings to enable ITM, add example

Author: maxekman

.cargo/config

@@ -1,5 +1,8 @@
-[target.thumbv7em-none-eabihf]
-runner = 'arm-none-eabi-gdb'
+[target.thumbv7m-none-eabi]
+
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+runner = "arm-none-eabi-gdb -q -x openocd.gdb"
+
 rustflags = [
   "-C", "link-arg=-Tlink.x",
 ]

.gdbinit

@@ -5,3 +5,4 @@ Cargo.lock
 **.bk
 **.sw*
 bloat_log*
+itm.txt

.gitignore

@@ -35,6 +35,7 @@ version = "0.6"
 ssd1306 = "0.2"
 nb = "0.1"
 panic-halt = "0.2"
+panic-itm = "0.4"
 
 [profile.dev]
 debug = true

Cargo.toml

@@ -0,0 +1,34 @@
+//! Sends "Hello, world!" through the ITM port 0
+//!
+//! ITM is much faster than semihosting. Like 4 orders of magnitude or so.
+//!
+//! **NOTE** Cortex-M0 chips don't support ITM.
+//!
+//! You'll have to connect the microcontroller's SWO pin to the SWD interface. Note that some
+//! development boards don't provide this option.
+//!
+//! You'll need [`itmdump`] to receive the message on the host plus you'll need to uncomment two
+//! `monitor` commands in the `.gdbinit` file.
+//!
+//! [`itmdump`]: https://docs.rs/itm/0.2.1/itm/
+//!
+//! ---
+
+#![no_main]
+#![no_std]
+
+extern crate panic_itm;
+extern crate stm32f407g_disc;
+
+use cortex_m::{iprintln, Peripherals};
+use cortex_m_rt::entry;
+
+#[entry]
+fn main() -> ! {
+    let mut p = Peripherals::take().unwrap();
+    let stim = &mut p.ITM.stim[0];
+
+    iprintln!(stim, "Hello, world!");
+
+    loop {}
+}

examples/itm.rs

@@ -0,0 +1,41 @@
+target extended-remote :3333
+
+# print demangled symbols
+set print asm-demangle on
+
+# set backtrace limit to not have infinite backtrace loops
+set backtrace limit 32
+
+# detect unhandled exceptions, hard faults and panics
+break DefaultHandler
+break HardFault
+break rust_begin_unwind
+# # run the next few lines so the panic message is printed immediately
+# # the number needs to be adjusted for your panic handler
+# commands $bpnum
+# next 4
+# end
+
+# *try* to stop at the user entry point (it might be gone due to inlining)
+break main
+
+set mem inaccessible-by-default off
+
+# monitor arm semihosting enable
+
+# # send captured ITM to the file itm.fifo
+# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
+# # 16000000 must match the core clock frequency
+# monitor tpiu config internal itm.txt uart off 16000000
+
+# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
+# # 8000000 is the frequency of the SWO pin
+# monitor tpiu config external uart off 8000000 2000000
+
+# # enable ITM port 0
+monitor itm port 0 on
+
+load
+
+# start the process but immediately halt the processor
+stepi

discovery.cfg renamed to openocd.cfg

@@ -5,4 +5,4 @@ if (( $# != 1 )); then
         exit 1
 fi
 
-openocd -f discovery.cfg -c "init" -c "targets" -c "reset halt" -c "program $1 verify reset exit"
+openocd -c "init" -c "targets" -c "reset halt" -c "program $1 verify reset exit"