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burrbullburrbull
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both embedded-hals for Delay
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6 files changed

+344
-240
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‎src/delay/hal_02.rs

+143
Original file line numberDiff line numberDiff line change
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//! Delay implementation based on general-purpose 32 bit timers and System timer (SysTick).
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//!
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//! TIM2 and TIM5 are a general purpose 32-bit auto-reload up/downcounter with
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//! a 16-bit prescaler.
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use cast::{u16, u32};
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use cortex_m::peripheral::SYST;
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use embedded_hal::blocking::delay::{DelayMs, DelayUs};
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use super::{Delay, Wait};
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impl DelayUs<u32> for Delay<SYST> {
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fn delay_us(&mut self, us: u32) {
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// The SysTick Reload Value register supports values between 1 and 0x00FFFFFF.
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const MAX_RVR: u32 = 0x00FF_FFFF;
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let mut total_rvr = us * (self.clk.0 / 8_000_000);
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while total_rvr != 0 {
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let current_rvr = if total_rvr <= MAX_RVR {
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total_rvr
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} else {
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MAX_RVR
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};
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self.tim.set_reload(current_rvr);
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self.tim.clear_current();
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self.tim.enable_counter();
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// Update the tracking variable while we are waiting...
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total_rvr -= current_rvr;
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while !self.tim.has_wrapped() {}
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self.tim.disable_counter();
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}
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}
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}
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impl DelayMs<u32> for Delay<SYST> {
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fn delay_ms(&mut self, ms: u32) {
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self.delay_us(ms * 1_000);
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}
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}
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impl DelayUs<u16> for Delay<SYST> {
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fn delay_us(&mut self, us: u16) {
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self.delay_us(u32(us))
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}
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}
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impl DelayMs<u16> for Delay<SYST> {
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fn delay_ms(&mut self, ms: u16) {
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self.delay_ms(u32(ms));
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}
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}
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impl DelayUs<u8> for Delay<SYST> {
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fn delay_us(&mut self, us: u8) {
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self.delay_us(u32(us))
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}
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}
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impl DelayMs<u8> for Delay<SYST> {
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fn delay_ms(&mut self, ms: u8) {
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self.delay_ms(u32(ms));
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}
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}
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impl<TIM> DelayUs<u32> for Delay<TIM>
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where
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Self: Wait,
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{
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/// Sleep for up to 2^32-1 microseconds (~71 minutes).
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fn delay_us(&mut self, us: u32) {
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// Set up prescaler so that a tick takes exactly 1 µs.
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//
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// For example, if the clock is set to 48 MHz, with a prescaler of 48
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// we'll get ticks that are 1 µs long. This means that we can write the
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// delay value directly to the auto-reload register (ARR).
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let psc = u16(self.clk.0 / 1_000_000).expect("Prescaler does not fit in u16");
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let arr = us;
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self.wait(psc, arr);
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}
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}
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impl<TIM> DelayMs<u32> for Delay<TIM>
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where
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Self: Wait,
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{
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/// Sleep for up to (2^32)/2-1 milliseconds (~24 days).
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/// If the `ms` value is larger than 2147483647, the code will panic.
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fn delay_ms(&mut self, ms: u32) {
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// See next section for explanation why the usable range is reduced.
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assert!(ms <= 2_147_483_647); // (2^32)/2-1
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// Set up prescaler so that a tick takes exactly 0.5 ms.
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//
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// For example, if the clock is set to 48 MHz, with a prescaler of 24'000
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// we'll get ticks that are 0.5 ms long. This means that we can write the
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// delay value multipled by two to the auto-reload register (ARR).
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//
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// Note that we cannot simply use a prescaler value where the tick corresponds
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// to 1 ms, because then a clock of 100 MHz would correspond to a prescaler
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// value of 100'000, which doesn't fit in the 16-bit PSC register.
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//
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// Unfortunately this means that only one half of the full 32-bit range
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// can be used, but 24 days should be plenty of usable delay time.
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let psc = u16(self.clk.0 / 1000 / 2).expect("Prescaler does not fit in u16");
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// Since PSC = 0.5 ms, double the value for the ARR
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let arr = ms << 1;
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self.wait(psc, arr);
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}
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}
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impl<TIM> DelayUs<u16> for Delay<TIM>
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where
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Self: Wait,
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{
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/// Sleep for up to 2^16-1 microseconds (~65 milliseconds).
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fn delay_us(&mut self, us: u16) {
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// See DelayUs<u32> for explanations.
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let psc = u16(self.clk.0 / 1_000_000).expect("Prescaler does not fit in u16");
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let arr = u32(us);
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self.wait(psc, arr);
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}
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}
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impl<TIM> DelayMs<u16> for Delay<TIM>
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where
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Self: Wait,
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{
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/// Sleep for up to (2^16)-1 milliseconds (~65 seconds).
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fn delay_ms(&mut self, ms: u16) {
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// See DelayMs<u32> for explanations. Since the value range is only 16 bit,
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// we don't need an assert here.
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let psc = u16(self.clk.0 / 1000 / 2).expect("Prescaler does not fit in u16");
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let arr = u32(ms) << 1;
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self.wait(psc, arr);
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}
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}

‎src/delay/hal_1.rs

+96
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,96 @@
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//! Delay implementation based on general-purpose 32 bit timers and System timer (SysTick).
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//!
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//! TIM2 and TIM5 are a general purpose 32-bit auto-reload up/downcounter with
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//! a 16-bit prescaler.
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use cast::u16;
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use core::convert::Infallible;
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use cortex_m::peripheral::SYST;
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use embedded_hal_one::delay::blocking::DelayUs;
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use super::{Delay, Wait};
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impl DelayUs for Delay<SYST> {
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type Error = Infallible;
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fn delay_us(&mut self, us: u32) -> Result<(), Self::Error> {
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// The SysTick Reload Value register supports values between 1 and 0x00FFFFFF.
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const MAX_RVR: u32 = 0x00FF_FFFF;
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let mut total_rvr = us * (self.clk.0 / 8_000_000);
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while total_rvr != 0 {
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let current_rvr = if total_rvr <= MAX_RVR {
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total_rvr
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} else {
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MAX_RVR
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};
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self.tim.set_reload(current_rvr);
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self.tim.clear_current();
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self.tim.enable_counter();
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// Update the tracking variable while we are waiting...
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total_rvr -= current_rvr;
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while !self.tim.has_wrapped() {}
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self.tim.disable_counter();
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}
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Ok(())
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}
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fn delay_ms(&mut self, ms: u32) -> Result<(), Self::Error> {
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self.delay_us(ms * 1_000)
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}
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}
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impl<TIM> DelayUs for Delay<TIM>
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where
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Self: Wait,
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{
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type Error = Infallible;
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/// Sleep for up to 2^32-1 microseconds (~71 minutes).
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fn delay_us(&mut self, us: u32) -> Result<(), Self::Error> {
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// Set up prescaler so that a tick takes exactly 1 µs.
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//
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// For example, if the clock is set to 48 MHz, with a prescaler of 48
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// we'll get ticks that are 1 µs long. This means that we can write the
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// delay value directly to the auto-reload register (ARR).
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let psc = u16(self.clk.0 / 1_000_000).expect("Prescaler does not fit in u16");
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let arr = us;
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self.wait(psc, arr);
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Ok(())
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}
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/// Sleep for up to (2^32)/2-1 milliseconds (~24 days).
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/// If the `ms` value is larger than 2147483647, the code will panic.
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fn delay_ms(&mut self, ms: u32) -> Result<(), Self::Error> {
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// See next section for explanation why the usable range is reduced.
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assert!(ms <= 2_147_483_647); // (2^32)/2-1
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// Set up prescaler so that a tick takes exactly 0.5 ms.
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//
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// For example, if the clock is set to 48 MHz, with a prescaler of 24'000
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// we'll get ticks that are 0.5 ms long. This means that we can write the
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// delay value multipled by two to the auto-reload register (ARR).
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//
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// Note that we cannot simply use a prescaler value where the tick corresponds
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// to 1 ms, because then a clock of 100 MHz would correspond to a prescaler
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// value of 100'000, which doesn't fit in the 16-bit PSC register.
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//
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// Unfortunately this means that only one half of the full 32-bit range
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// can be used, but 24 days should be plenty of usable delay time.
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let psc = u16(self.clk.0 / 1000 / 2).expect("Prescaler does not fit in u16");
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// Since PSC = 0.5 ms, double the value for the ARR
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let arr = ms << 1;
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self.wait(psc, arr);
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Ok(())
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}
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}

‎src/delay/mod.rs

+83-2
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,15 @@
11
//! Delays
22
3-
mod syst;
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mod hal_02;
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mod hal_1;
45

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use crate::{
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pac,
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rcc::Clocks,
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timer::{General, Timer},
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};
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use core::cmp::max;
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use cortex_m::peripheral::syst::SystClkSource;
513
use cortex_m::peripheral::SYST;
614

715
use crate::time::Hertz;
@@ -19,4 +27,77 @@ impl<T> Delay<T> {
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}
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}
2129

22-
mod timer;
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impl Delay<SYST> {
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/// Configures the system timer (SysTick) as a delay provider
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pub fn new(mut tim: SYST, clocks: &Clocks) -> Self {
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tim.set_clock_source(SystClkSource::External);
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Self {
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tim,
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clk: clocks.hclk(),
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}
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}
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}
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mod sealed {
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pub trait Wait {
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fn wait(&mut self, prescaler: u16, auto_reload_register: u32);
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}
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}
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use sealed::Wait;
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macro_rules! hal {
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($($TIM:ty: ($tim:ident),)+) => {
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$(
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impl Timer<$TIM> {
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pub fn delay(self) -> Delay<$TIM> {
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let Self { tim, clk } = self;
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// Enable one-pulse mode (counter stops counting at the next update
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// event, clearing the CEN bit)
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tim.cr1.modify(|_, w| w.opm().enabled());
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Delay { tim, clk }
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}
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}
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impl Delay<$TIM> {
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/// Configures the timer as a delay provider
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pub fn $tim(tim: $TIM, clocks: &Clocks) -> Self {
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Timer::new(tim, clocks).delay()
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}
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}
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impl Wait for Delay<$TIM> {
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fn wait(&mut self, prescaler: u16, auto_reload_register: u32) {
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// Write Prescaler (PSC)
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self.tim.set_prescaler(prescaler);
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// Write Auto-Reload Register (ARR)
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// Note: Make it impossible to set the ARR value to 0, since this
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// would cause an infinite loop.
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self.tim.set_auto_reload(max(1, auto_reload_register)).unwrap();
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// Trigger update event (UEV) in the event generation register (EGR)
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// in order to immediately apply the config
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self.tim.trigger_update();
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// Configure the counter in one-pulse mode (counter stops counting at
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// the next updateevent, clearing the CEN bit) and enable the counter.
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self.tim.cr1.write(|w| w.opm().set_bit().cen().set_bit());
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// Wait for CEN bit to clear
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while self.tim.is_counter_enabled() { /* wait */ }
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}
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}
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)+
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}
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}
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hal! {
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pac::TIM5: (tim5),
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}
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#[cfg(feature = "tim2")]
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hal! {
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pac::TIM2: (tim2),
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}

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