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burrbullburrbull
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both embedded-hals for I2C
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4 files changed

+309
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‎src/fmpi2c.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@ use crate::rcc::{Enable, Reset};
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use crate::time::{Hertz, U32Ext};
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mod hal_02;
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mod hal_1;
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/// I2C FastMode+ abstraction
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pub struct FMPI2c<I2C, PINS> {

‎src/fmpi2c/hal_1.rs

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@@ -0,0 +1,143 @@
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mod blocking {
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use super::super::{fmpi2c1, Error, FMPI2c};
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use core::ops::Deref;
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use embedded_hal_one::i2c::blocking::{Read, Write, WriteRead};
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impl<I2C, PINS> WriteRead for FMPI2c<I2C, PINS>
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where
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I2C: Deref<Target = fmpi2c1::RegisterBlock>,
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{
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type Error = Error;
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fn write_read(&mut self, addr: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> {
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// Set up current slave address for writing and disable autoending
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self.i2c.cr2.modify(|_, w| {
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w.sadd()
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.bits(u16::from(addr) << 1)
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.nbytes()
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.bits(bytes.len() as u8)
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.rd_wrn()
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.clear_bit()
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.autoend()
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.clear_bit()
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});
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// Send a START condition
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self.i2c.cr2.modify(|_, w| w.start().set_bit());
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// Wait until the transmit buffer is empty and there hasn't been any error condition
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while {
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let isr = self.i2c.isr.read();
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self.check_and_clear_error_flags(&isr)?;
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isr.txis().bit_is_clear() && isr.tc().bit_is_clear()
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} {}
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// Send out all individual bytes
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for c in bytes {
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self.send_byte(*c)?;
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}
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// Wait until data was sent
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while {
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let isr = self.i2c.isr.read();
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self.check_and_clear_error_flags(&isr)?;
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isr.tc().bit_is_clear()
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} {}
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// Set up current address for reading
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self.i2c.cr2.modify(|_, w| {
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w.sadd()
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.bits(u16::from(addr) << 1)
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.nbytes()
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.bits(buffer.len() as u8)
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.rd_wrn()
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.set_bit()
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});
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// Send another START condition
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self.i2c.cr2.modify(|_, w| w.start().set_bit());
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// Send the autoend after setting the start to get a restart
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self.i2c.cr2.modify(|_, w| w.autoend().set_bit());
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// Now read in all bytes
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for c in buffer.iter_mut() {
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*c = self.recv_byte()?;
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}
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// Check and clear flags if they somehow ended up set
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self.check_and_clear_error_flags(&self.i2c.isr.read())?;
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Ok(())
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}
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}
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impl<I2C, PINS> Read for FMPI2c<I2C, PINS>
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where
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I2C: Deref<Target = fmpi2c1::RegisterBlock>,
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{
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type Error = Error;
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fn read(&mut self, addr: u8, buffer: &mut [u8]) -> Result<(), Error> {
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// Set up current address for reading
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self.i2c.cr2.modify(|_, w| {
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w.sadd()
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.bits(u16::from(addr) << 1)
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.nbytes()
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.bits(buffer.len() as u8)
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.rd_wrn()
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.set_bit()
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});
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// Send a START condition
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self.i2c.cr2.modify(|_, w| w.start().set_bit());
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// Send the autoend after setting the start to get a restart
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self.i2c.cr2.modify(|_, w| w.autoend().set_bit());
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// Now read in all bytes
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for c in buffer.iter_mut() {
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*c = self.recv_byte()?;
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}
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// Check and clear flags if they somehow ended up set
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self.check_and_clear_error_flags(&self.i2c.isr.read())?;
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Ok(())
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}
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}
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impl<I2C, PINS> Write for FMPI2c<I2C, PINS>
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where
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I2C: Deref<Target = fmpi2c1::RegisterBlock>,
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{
114+
type Error = Error;
115+
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fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Error> {
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// Set up current slave address for writing and enable autoending
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self.i2c.cr2.modify(|_, w| {
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w.sadd()
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.bits(u16::from(addr) << 1)
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.nbytes()
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.bits(bytes.len() as u8)
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.rd_wrn()
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.clear_bit()
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.autoend()
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.set_bit()
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});
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// Send a START condition
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self.i2c.cr2.modify(|_, w| w.start().set_bit());
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// Send out all individual bytes
133+
for c in bytes {
134+
self.send_byte(*c)?;
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}
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// Check and clear flags if they somehow ended up set
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self.check_and_clear_error_flags(&self.i2c.isr.read())?;
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Ok(())
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}
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}
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}

‎src/i2c.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@ use crate::rcc::Clocks;
1818
use crate::time::{Hertz, U32Ext};
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2020
mod hal_02;
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mod hal_1;
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2223
#[derive(Debug, Eq, PartialEq)]
2324
pub enum DutyCycle {

‎src/i2c/hal_1.rs

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,164 @@
1+
use embedded_hal_one::i2c::{Error, ErrorKind, NoAcknowledgeSource};
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3+
impl Error for super::Error {
4+
fn kind(&self) -> ErrorKind {
5+
match self {
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Self::OVERRUN => ErrorKind::Overrun,
7+
Self::BUS => ErrorKind::Bus,
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Self::ARBITRATION => ErrorKind::ArbitrationLoss,
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Self::NACK => ErrorKind::NoAcknowledge(NoAcknowledgeSource::Unknown),
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Self::CRC | Self::TIMEOUT => ErrorKind::Other,
11+
}
12+
}
13+
}
14+
15+
mod blocking {
16+
use super::super::{Error, I2c, I2cCommon, Instance};
17+
use embedded_hal_one::i2c::blocking::{Read, Write, WriteIter, WriteIterRead, WriteRead};
18+
19+
impl<I2C, PINS> WriteRead for I2c<I2C, PINS>
20+
where
21+
I2C: Instance,
22+
{
23+
type Error = Error;
24+
25+
fn write_read(
26+
&mut self,
27+
addr: u8,
28+
bytes: &[u8],
29+
buffer: &mut [u8],
30+
) -> Result<(), Self::Error> {
31+
self.write_bytes(addr, bytes.iter().cloned())?;
32+
self.read(addr, buffer)?;
33+
34+
Ok(())
35+
}
36+
}
37+
38+
impl<I2C, PINS> WriteIterRead for I2c<I2C, PINS>
39+
where
40+
I2C: Instance,
41+
{
42+
type Error = Error;
43+
44+
fn write_iter_read<B>(
45+
&mut self,
46+
addr: u8,
47+
bytes: B,
48+
buffer: &mut [u8],
49+
) -> Result<(), Self::Error>
50+
where
51+
B: IntoIterator<Item = u8>,
52+
{
53+
self.write_bytes(addr, bytes.into_iter())?;
54+
self.read(addr, buffer)?;
55+
56+
Ok(())
57+
}
58+
}
59+
60+
impl<I2C, PINS> Write for I2c<I2C, PINS>
61+
where
62+
I2C: Instance,
63+
{
64+
type Error = Error;
65+
66+
fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Self::Error> {
67+
self.write_bytes(addr, bytes.iter().cloned())?;
68+
69+
// Send a STOP condition
70+
self.i2c.cr1.modify(|_, w| w.stop().set_bit());
71+
72+
// Wait for STOP condition to transmit.
73+
while self.i2c.cr1.read().stop().bit_is_set() {}
74+
75+
// Fallthrough is success
76+
Ok(())
77+
}
78+
}
79+
80+
impl<I2C, PINS> WriteIter for I2c<I2C, PINS>
81+
where
82+
I2C: Instance,
83+
{
84+
type Error = Error;
85+
86+
fn write_iter<B>(&mut self, addr: u8, bytes: B) -> Result<(), Self::Error>
87+
where
88+
B: IntoIterator<Item = u8>,
89+
{
90+
self.write_bytes(addr, bytes.into_iter())?;
91+
92+
// Send a STOP condition
93+
self.i2c.cr1.modify(|_, w| w.stop().set_bit());
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95+
// Wait for STOP condition to transmit.
96+
while self.i2c.cr1.read().stop().bit_is_set() {}
97+
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// Fallthrough is success
99+
Ok(())
100+
}
101+
}
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103+
impl<I2C, PINS> Read for I2c<I2C, PINS>
104+
where
105+
I2C: Instance,
106+
{
107+
type Error = Error;
108+
109+
fn read(&mut self, addr: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
110+
if let Some((last, buffer)) = buffer.split_last_mut() {
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// Send a START condition and set ACK bit
112+
self.i2c
113+
.cr1
114+
.modify(|_, w| w.start().set_bit().ack().set_bit());
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// Wait until START condition was generated
117+
while self.i2c.sr1.read().sb().bit_is_clear() {}
118+
119+
// Also wait until signalled we're master and everything is waiting for us
120+
while {
121+
let sr2 = self.i2c.sr2.read();
122+
sr2.msl().bit_is_clear() && sr2.busy().bit_is_clear()
123+
} {}
124+
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// Set up current address, we're trying to talk to
126+
self.i2c
127+
.dr
128+
.write(|w| unsafe { w.bits((u32::from(addr) << 1) + 1) });
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// Wait until address was sent
131+
loop {
132+
self.check_and_clear_error_flags()?;
133+
if self.i2c.sr1.read().addr().bit_is_set() {
134+
break;
135+
}
136+
}
137+
138+
// Clear condition by reading SR2
139+
self.i2c.sr2.read();
140+
141+
// Receive bytes into buffer
142+
for c in buffer {
143+
*c = self.recv_byte()?;
144+
}
145+
146+
// Prepare to send NACK then STOP after next byte
147+
self.i2c
148+
.cr1
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.modify(|_, w| w.ack().clear_bit().stop().set_bit());
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// Receive last byte
152+
*last = self.recv_byte()?;
153+
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// Wait for the STOP to be sent.
155+
while self.i2c.cr1.read().stop().bit_is_set() {}
156+
157+
// Fallthrough is success
158+
Ok(())
159+
} else {
160+
Err(Error::OVERRUN)
161+
}
162+
}
163+
}
164+
}

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