Merge #403

403: qei cleanups r=therealprof a=burrbull



Co-authored-by: Andrey Zgarbul <[email protected]>

Author: bors[bot]

CHANGELOG.md

@@ -26,6 +26,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
+- Qei macro cleanups  [#403]
 - Update RTIC to 1.0 [#401]
 - Finish SDIO data transmission before querying card status in `write_block` [#395]
 - SDIO: Rewrite loop conditions to silence clippy
@@ -50,6 +51,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 [#393]: https://github.com/stm32-rs/stm32f4xx-hal/pull/393
 [#395]: https://github.com/stm32-rs/stm32f4xx-hal/pull/395
 [#401]: https://github.com/stm32-rs/stm32f4xx-hal/pull/401
+[#401]: https://github.com/stm32-rs/stm32f4xx-hal/pull/403
 
 ## [v0.10.1] - 2021-10-26
 

src/delay/timer.rs

@@ -133,24 +133,7 @@ hal! {
     pac::TIM5: (tim5, wait_tim5),
 }
 
-#[cfg(any(
-    feature = "stm32f401",
-    feature = "stm32f405",
-    feature = "stm32f407",
-    feature = "stm32f411",
-    feature = "stm32f412",
-    feature = "stm32f413",
-    feature = "stm32f415",
-    feature = "stm32f417",
-    feature = "stm32f423",
-    feature = "stm32f427",
-    feature = "stm32f429",
-    feature = "stm32f437",
-    feature = "stm32f439",
-    feature = "stm32f446",
-    feature = "stm32f469",
-    feature = "stm32f479"
-))]
+#[cfg(feature = "tim2")]
 hal! {
     pac::TIM2: (tim2, wait_tim2),
 }

src/qei.rs

@@ -3,6 +3,7 @@ use crate::{
     hal::{self, Direction},
     pac::RCC,
     rcc,
+    timer::General,
 };
 
 pub trait Pins<TIM> {}
@@ -48,7 +49,7 @@ impl<TIM: Instance, PINS> Qei<TIM, PINS> {
 }
 
 impl<TIM: Instance, PINS> hal::Qei for Qei<TIM, PINS> {
-    type Count = TIM::Count;
+    type Count = TIM::Width;
 
     fn count(&self) -> Self::Count {
         self.tim.read_count() as Self::Count
@@ -63,23 +64,22 @@ impl<TIM: Instance, PINS> hal::Qei for Qei<TIM, PINS> {
     }
 }
 
-pub trait Instance: crate::Sealed + rcc::Enable + rcc::Reset {
-    type Count;
-
+pub trait Instance: crate::Sealed + rcc::Enable + rcc::Reset + General {
     fn setup_qei(&mut self);
-    fn read_count(&self) -> Self::Count;
+
     fn read_direction(&self) -> bool;
 }
 
 macro_rules! hal {
-    ($($TIM:ty: ($bits:ident),)+) => {
+    ($($TIM:ty,)+) => {
         $(
             impl Instance for $TIM {
-                type Count = $bits;
-
                 fn setup_qei(&mut self) {
                     // Configure TxC1 and TxC2 as captures
-                    self.ccmr1_output()
+                    #[cfg(not(feature = "stm32f410"))]
+                    self.ccmr1_input().write(|w| w.cc1s().ti1().cc2s().ti2());
+                    #[cfg(feature = "stm32f410")]
+                    self.ccmr1_input()
                         .write(|w| unsafe { w.cc1s().bits(0b01).cc2s().bits(0b01) });
                     // enable and configure to capture on rising edge
                     self.ccer.write(|w| {
@@ -92,19 +92,14 @@ macro_rules! hal {
                             .cc2p()
                             .clear_bit()
                     });
-                    // configure as quadrature encoder
-                    // some chip variants declare `.bits()` as unsafe, some don't
-                    #[allow(unused_unsafe)]
+                    #[cfg(not(feature = "stm32f410"))]
+                    self.smcr.write(|w| w.sms().encoder_mode_3());
+                    #[cfg(feature = "stm32f410")]
                     self.smcr.write(|w| unsafe { w.sms().bits(3) });
-                    #[allow(unused_unsafe)]
-                    self.arr.write(|w| unsafe { w.bits($bits::MAX as u32) });
+                    self.set_auto_reload(<$TIM as General>::Width::MAX as u32).unwrap();
                     self.cr1.write(|w| w.cen().set_bit());
                 }
 
-                fn read_count(&self) -> Self::Count {
-                    self.cnt.read().bits() as Self::Count
-                }
-
                 fn read_direction(&self) -> bool {
                     self.cr1.read().dir().bit_is_clear()
                 }
@@ -114,18 +109,18 @@ macro_rules! hal {
 }
 
 hal! {
-    crate::pac::TIM1: (u16),
-    crate::pac::TIM5: (u32),
+    crate::pac::TIM1,
+    crate::pac::TIM5,
 }
 
 #[cfg(feature = "tim2")]
 hal! {
-    crate::pac::TIM2: (u32),
-    crate::pac::TIM3: (u16),
-    crate::pac::TIM4: (u16),
+    crate::pac::TIM2,
+    crate::pac::TIM3,
+    crate::pac::TIM4,
 }
 
 #[cfg(feature = "tim8")]
 hal! {
-    crate::pac::TIM8: (u16),
+    crate::pac::TIM8,
 }

src/rcc/enable.rs

@@ -132,16 +132,8 @@ impl RccBus for crate::pac::FSMC {
     type Bus = AHB3;
 }
 #[cfg(feature = "fsmc")]
-#[cfg(any(feature = "stm32f427", feature = "stm32f437"))]
 bus_enable!(FSMC => 0);
 #[cfg(feature = "fsmc")]
-#[cfg(not(any(feature = "stm32f427", feature = "stm32f437")))]
-bus_enable!(FSMC => 0);
-#[cfg(feature = "fsmc")]
-#[cfg(any(feature = "stm32f427", feature = "stm32f437"))]
-bus_reset!(FSMC => 0);
-#[cfg(feature = "fsmc")]
-#[cfg(not(any(feature = "stm32f427", feature = "stm32f437")))]
 bus_reset!(FSMC => 0);
 
 bus! {

src/timer.rs

@@ -190,7 +190,7 @@ impl Instant {
 
 mod sealed {
     pub trait General {
-        type Width;
+        type Width: Into<u32>;
         fn enable_counter(&mut self);
         fn disable_counter(&mut self);
         fn is_counter_enabled(&self) -> bool;
@@ -201,6 +201,8 @@ mod sealed {
         fn clear_update_interrupt_flag(&mut self);
         fn listen_update_interrupt(&mut self, b: bool);
         fn get_update_interrupt_flag(&self) -> bool;
+        fn read_count(&self) -> Self::Width;
+        fn read_auto_reload(&self) -> Self::Width;
     }
 }
 pub(crate) use sealed::General;
@@ -285,6 +287,14 @@ macro_rules! hal {
                 fn get_update_interrupt_flag(&self) -> bool {
                     self.sr.read().uif().bit_is_clear()
                 }
+                #[inline(always)]
+                fn read_count(&self) -> Self::Width {
+                    self.cnt.read().bits() as Self::Width
+                }
+                #[inline(always)]
+                fn read_auto_reload(&self) -> Self::Width {
+                    self.arr.read().bits() as Self::Width
+                }
             }
         )+
     }