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Merge pull request #1343 from fpistm/updateF7
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Update STM32F7 HAL and CMSIS drivers
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@fpistm
fpistm authored Mar 30, 2021
2 parents dad10ca + 24cbbc8 commit c18cc58
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Showing 151 changed files with 15,008 additions and 6,817 deletions.
32 changes: 31 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f745xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -475,7 +475,8 @@ typedef struct
__IO uint32_t PTPTTLR;
__IO uint32_t RESERVED8;
__IO uint32_t PTPTSSR;
uint32_t RESERVED9[565];
__IO uint32_t PTPPPSCR;
uint32_t RESERVED9[564];
__IO uint32_t DMABMR;
__IO uint32_t DMATPDR;
__IO uint32_t DMARPDR;
Expand Down Expand Up @@ -12899,6 +12900,30 @@ typedef struct
#define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */

/****************** Bit definition for SYSCFG_PMC register ******************/
#define SYSCFG_PMC_I2C1_FMP_Pos (0U)
#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */
#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */
#define SYSCFG_PMC_I2C2_FMP_Pos (1U)
#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */
#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */
#define SYSCFG_PMC_I2C3_FMP_Pos (2U)
#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */
#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */
#define SYSCFG_PMC_I2C4_FMP_Pos (3U)
#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */
#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */
#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)
#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */
#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)
#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */
#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)
#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */
#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)
#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */

#define SYSCFG_PMC_ADCxDC2_Pos (16U)
#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
Expand Down Expand Up @@ -15221,6 +15246,11 @@ typedef struct
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */

/* Bit definition for Ethernet PTP PPS Control Register */
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */

/******************************************************************************/
/* Ethernet DMA Registers bits definition */
/******************************************************************************/
Expand Down
32 changes: 31 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -477,7 +477,8 @@ typedef struct
__IO uint32_t PTPTTLR;
__IO uint32_t RESERVED8;
__IO uint32_t PTPTSSR;
uint32_t RESERVED9[565];
__IO uint32_t PTPPPSCR;
uint32_t RESERVED9[564];
__IO uint32_t DMABMR;
__IO uint32_t DMATPDR;
__IO uint32_t DMARPDR;
Expand Down Expand Up @@ -13247,6 +13248,30 @@ typedef struct
#define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */

/****************** Bit definition for SYSCFG_PMC register ******************/
#define SYSCFG_PMC_I2C1_FMP_Pos (0U)
#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */
#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */
#define SYSCFG_PMC_I2C2_FMP_Pos (1U)
#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */
#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */
#define SYSCFG_PMC_I2C3_FMP_Pos (2U)
#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */
#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */
#define SYSCFG_PMC_I2C4_FMP_Pos (3U)
#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */
#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */
#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)
#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */
#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)
#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */
#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)
#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */
#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)
#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */

#define SYSCFG_PMC_ADCxDC2_Pos (16U)
#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
Expand Down Expand Up @@ -15569,6 +15594,11 @@ typedef struct
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */

/* Bit definition for Ethernet PTP PPS Control Register */
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */

/******************************************************************************/
/* Ethernet DMA Registers bits definition */
/******************************************************************************/
Expand Down
32 changes: 31 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f750xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -478,7 +478,8 @@ typedef struct
__IO uint32_t PTPTTLR;
__IO uint32_t RESERVED8;
__IO uint32_t PTPTSSR;
uint32_t RESERVED9[565];
__IO uint32_t PTPPPSCR;
uint32_t RESERVED9[564];
__IO uint32_t DMABMR;
__IO uint32_t DMATPDR;
__IO uint32_t DMARPDR;
Expand Down Expand Up @@ -13540,6 +13541,30 @@ typedef struct
#define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */

/****************** Bit definition for SYSCFG_PMC register ******************/
#define SYSCFG_PMC_I2C1_FMP_Pos (0U)
#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */
#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */
#define SYSCFG_PMC_I2C2_FMP_Pos (1U)
#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */
#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */
#define SYSCFG_PMC_I2C3_FMP_Pos (2U)
#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */
#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */
#define SYSCFG_PMC_I2C4_FMP_Pos (3U)
#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */
#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */
#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)
#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */
#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)
#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */
#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)
#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */
#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)
#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */

#define SYSCFG_PMC_ADCxDC2_Pos (16U)
#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
Expand Down Expand Up @@ -15862,6 +15887,11 @@ typedef struct
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */

/* Bit definition for Ethernet PTP PPS Control Register */
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */

/******************************************************************************/
/* Ethernet DMA Registers bits definition */
/******************************************************************************/
Expand Down
32 changes: 31 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f756xx.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -478,7 +478,8 @@ typedef struct
__IO uint32_t PTPTTLR;
__IO uint32_t RESERVED8;
__IO uint32_t PTPTSSR;
uint32_t RESERVED9[565];
__IO uint32_t PTPPPSCR;
uint32_t RESERVED9[564];
__IO uint32_t DMABMR;
__IO uint32_t DMATPDR;
__IO uint32_t DMARPDR;
Expand Down Expand Up @@ -13540,6 +13541,30 @@ typedef struct
#define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */

/****************** Bit definition for SYSCFG_PMC register ******************/
#define SYSCFG_PMC_I2C1_FMP_Pos (0U)
#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */
#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */
#define SYSCFG_PMC_I2C2_FMP_Pos (1U)
#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */
#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */
#define SYSCFG_PMC_I2C3_FMP_Pos (2U)
#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */
#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */
#define SYSCFG_PMC_I2C4_FMP_Pos (3U)
#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */
#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */
#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)
#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */
#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)
#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */
#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)
#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */
#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)
#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */

#define SYSCFG_PMC_ADCxDC2_Pos (16U)
#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
Expand Down Expand Up @@ -15862,6 +15887,11 @@ typedef struct
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */

/* Bit definition for Ethernet PTP PPS Control Register */
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */

/******************************************************************************/
/* Ethernet DMA Registers bits definition */
/******************************************************************************/
Expand Down
8 changes: 7 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f765xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -519,7 +519,8 @@ typedef struct
__IO uint32_t PTPTTLR;
__IO uint32_t RESERVED8;
__IO uint32_t PTPTSSR;
uint32_t RESERVED9[565];
__IO uint32_t PTPPPSCR;
uint32_t RESERVED9[564];
__IO uint32_t DMABMR;
__IO uint32_t DMATPDR;
__IO uint32_t DMARPDR;
Expand Down Expand Up @@ -15879,6 +15880,11 @@ typedef struct
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */

/* Bit definition for Ethernet PTP PPS Control Register */
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */

/******************************************************************************/
/* Ethernet DMA Registers bits definition */
/******************************************************************************/
Expand Down
8 changes: 7 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -522,7 +522,8 @@ typedef struct
__IO uint32_t PTPTTLR;
__IO uint32_t RESERVED8;
__IO uint32_t PTPTSSR;
uint32_t RESERVED9[565];
__IO uint32_t PTPPPSCR;
uint32_t RESERVED9[564];
__IO uint32_t DMABMR;
__IO uint32_t DMATPDR;
__IO uint32_t DMARPDR;
Expand Down Expand Up @@ -16273,6 +16274,11 @@ typedef struct
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */

/* Bit definition for Ethernet PTP PPS Control Register */
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */

/******************************************************************************/
/* Ethernet DMA Registers bits definition */
/******************************************************************************/
Expand Down
8 changes: 7 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f769xx.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -523,7 +523,8 @@ typedef struct
__IO uint32_t PTPTTLR;
__IO uint32_t RESERVED8;
__IO uint32_t PTPTSSR;
uint32_t RESERVED9[565];
__IO uint32_t PTPPPSCR;
uint32_t RESERVED9[564];
__IO uint32_t DMABMR;
__IO uint32_t DMATPDR;
__IO uint32_t DMARPDR;
Expand Down Expand Up @@ -16368,6 +16369,11 @@ typedef struct
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */

/* Bit definition for Ethernet PTP PPS Control Register */
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */

/******************************************************************************/
/* Ethernet DMA Registers bits definition */
/******************************************************************************/
Expand Down
8 changes: 7 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f777xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -523,7 +523,8 @@ typedef struct
__IO uint32_t PTPTTLR;
__IO uint32_t RESERVED8;
__IO uint32_t PTPTSSR;
uint32_t RESERVED9[565];
__IO uint32_t PTPPPSCR;
uint32_t RESERVED9[564];
__IO uint32_t DMABMR;
__IO uint32_t DMATPDR;
__IO uint32_t DMARPDR;
Expand Down Expand Up @@ -16566,6 +16567,11 @@ typedef struct
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */

/* Bit definition for Ethernet PTP PPS Control Register */
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */

/******************************************************************************/
/* Ethernet DMA Registers bits definition */
/******************************************************************************/
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8 changes: 7 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f779xx.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -524,7 +524,8 @@ typedef struct
__IO uint32_t PTPTTLR;
__IO uint32_t RESERVED8;
__IO uint32_t PTPTSSR;
uint32_t RESERVED9[565];
__IO uint32_t PTPPPSCR;
uint32_t RESERVED9[564];
__IO uint32_t DMABMR;
__IO uint32_t DMATPDR;
__IO uint32_t DMARPDR;
Expand Down Expand Up @@ -16661,6 +16662,11 @@ typedef struct
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */

/* Bit definition for Ethernet PTP PPS Control Register */
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */

/******************************************************************************/
/* Ethernet DMA Registers bits definition */
/******************************************************************************/
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