@@ -124,17 +124,17 @@ Nucleo_144.menu.pnum.NUCLEO_L496ZG.build.variant=Nucleo_144/NUCLEO_L496ZG
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Nucleo_144.menu.pnum.NUCLEO_L496ZG.build.cmsis_lib_gcc=arm_cortexM4lf_math
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# NUCLEO_L496ZG-P board
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- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P =Nucleo L496ZG-P
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- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .node=NODE_L496ZG
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- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .upload.maximum_size=1048576
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- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .upload.maximum_data_size=327680
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- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .build.mcu=cortex-m4
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- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .build.flags.fp=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
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- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .build.board=NUCLEO_L496ZG_P
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- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .build.series=STM32L4xx
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- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .build.product_line=STM32L496xx
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- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .build.variant=Nucleo_144/NUCLEO_L496ZG
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- Nucleo_144.menu.pnum.NUCLEO_L496ZG-P .build.cmsis_lib_gcc=arm_cortexM4lf_math
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+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P =Nucleo L496ZG-P
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+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .node=NODE_L496ZG
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+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .upload.maximum_size=1048576
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+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .upload.maximum_data_size=327680
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+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .build.mcu=cortex-m4
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+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .build.flags.fp=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
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+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .build.board=NUCLEO_L496ZG_P
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+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .build.series=STM32L4xx
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+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .build.product_line=STM32L496xx
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+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .build.variant=Nucleo_144/NUCLEO_L496ZG
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+ Nucleo_144.menu.pnum.NUCLEO_L496ZG_P .build.cmsis_lib_gcc=arm_cortexM4lf_math
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# NUCLEO_L4R5ZI board
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Nucleo_144.menu.pnum.NUCLEO_L4R5ZI=Nucleo L4R5ZI
@@ -150,17 +150,17 @@ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.build.variant=Nucleo_144/NUCLEO_L4R5ZI
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Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.build.cmsis_lib_gcc=arm_cortexM4lf_math
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# NUCLEO_L4R5ZI-P board
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- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P =Nucleo L4R5ZI-P
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- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .node=NODE_L4R5ZI
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- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .upload.maximum_size=2097152
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- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .upload.maximum_data_size=655360
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- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .build.mcu=cortex-m4
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- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .build.flags.fp=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
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- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .build.board=NUCLEO_L4R5ZI_P
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- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .build.series=STM32L4xx
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- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .build.product_line=STM32L4R5xx
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- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .build.variant=Nucleo_144/NUCLEO_L4R5ZI
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- Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P .build.cmsis_lib_gcc=arm_cortexM4lf_math
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+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P =Nucleo L4R5ZI-P
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+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .node=NODE_L4R5ZI
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+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .upload.maximum_size=2097152
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+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .upload.maximum_data_size=655360
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+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .build.mcu=cortex-m4
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+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .build.flags.fp=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
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+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .build.board=NUCLEO_L4R5ZI_P
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+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .build.series=STM32L4xx
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+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .build.product_line=STM32L4R5xx
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+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .build.variant=Nucleo_144/NUCLEO_L4R5ZI
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+ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P .build.cmsis_lib_gcc=arm_cortexM4lf_math
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# Upload menu
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Nucleo_144.menu.upload_method.MassStorage=Mass Storage
@@ -408,17 +408,17 @@ Nucleo_64.menu.pnum.NUCLEO_L452RE.build.variant=Nucleo_64/NUCLEO_L452RE
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Nucleo_64.menu.pnum.NUCLEO_L452RE.build.cmsis_lib_gcc=arm_cortexM4lf_math
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# NUCLEO_L452RE-P board
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- Nucleo_64.menu.pnum.NUCLEO_L452REP =Nucleo L452RE-P
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- Nucleo_64.menu.pnum.NUCLEO_L452REP .node=NODE_L452RE
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- Nucleo_64.menu.pnum.NUCLEO_L452REP .upload.maximum_size=524288
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- Nucleo_64.menu.pnum.NUCLEO_L452REP .upload.maximum_data_size=163840
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- Nucleo_64.menu.pnum.NUCLEO_L452REP .build.mcu=cortex-m4
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- Nucleo_64.menu.pnum.NUCLEO_L452REP .build.flags.fp=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
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- Nucleo_64.menu.pnum.NUCLEO_L452REP .build.board=NUCLEO_L452RE_P
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- Nucleo_64.menu.pnum.NUCLEO_L452REP .build.series=STM32L4xx
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- Nucleo_64.menu.pnum.NUCLEO_L452REP .build.product_line=STM32L452xx
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- Nucleo_64.menu.pnum.NUCLEO_L452REP .build.variant=Nucleo_64/NUCLEO_L452RE
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- Nucleo_64.menu.pnum.NUCLEO_L452REP .build.cmsis_lib_gcc=arm_cortexM4lf_math
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+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P =Nucleo L452RE-P
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+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .node=NODE_L452RE
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+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .upload.maximum_size=524288
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+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .upload.maximum_data_size=163840
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+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .build.mcu=cortex-m4
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+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .build.flags.fp=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
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+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .build.board=NUCLEO_L452RE_P
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+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .build.series=STM32L4xx
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+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .build.product_line=STM32L452xx
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+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .build.variant=Nucleo_64/NUCLEO_L452RE
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+ Nucleo_64.menu.pnum.NUCLEO_L452RE_P .build.cmsis_lib_gcc=arm_cortexM4lf_math
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# NUCLEO_L476RG board
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# Support: Serial1 (USART1 on PA10, PA9)
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