Improved handling of non-sequential subregister errors that do not affect all targets.

sysprogs · sysprogs · commit f2131e013054 · 2018-07-03T19:37:19.000-07:00
Updated STM32 BSP to pass the new validation logic.
diff --git a/DebugPackages/ESP8266DebugPackage/Properties/AssemblyInfo.cs b/DebugPackages/ESP8266DebugPackage/Properties/AssemblyInfo.cs
@@ -16,5 +16,5 @@
 [assembly: AssemblyCulture("")]
 [assembly: ComVisible(false)]
 
-[assembly: AssemblyVersion("2.0.1535.0")]
-[assembly: AssemblyFileVersion("2.0.1535.0")]
+[assembly: AssemblyVersion("2.0.1569.0")]
+[assembly: AssemblyFileVersion("2.0.1569.0")]
diff --git a/DebugPackages/RISCVDebugPackage/Properties/AssemblyInfo.cs b/DebugPackages/RISCVDebugPackage/Properties/AssemblyInfo.cs
@@ -32,5 +32,5 @@
 // You can specify all the values or you can default the Build and Revision Numbers
 // by using the '*' as shown below:
 // [assembly: AssemblyVersion("1.0.*")]
-[assembly: AssemblyVersion("1.0.1124.0")]
-[assembly: AssemblyFileVersion("1.0.1124.0")]
+[assembly: AssemblyVersion("1.0.1158.0")]
+[assembly: AssemblyFileVersion("1.0.1158.0")]
diff --git a/generators/stm32/PeripheralRegisterGenerator.cs b/generators/stm32/PeripheralRegisterGenerator.cs
@@ -41,6 +41,7 @@ public override string ToString()
     public class RegisterParserConfiguration
     {
         Dictionary<string, bool> _IgnoredSubregisters = new Dictionary<string, bool>();
+        Dictionary<string, bool> _PotentiallyNotSequentialRegisters = new Dictionary<string, bool>();
         string[] _IgnoredSubregisterPrefixes;
         string[] _IgnoredSubregisterSuffixes;
         Regex[] _IgnoredSubregisterRegexes;
@@ -271,6 +272,20 @@ public string IgnoredSubregisters
             }
         }
 
+        //Those registers might be non-sequential for some devices, but not all. We will only ignore the actual non-sequential instances of them.
+        public bool IsKnownNonSequentialRegister(string register) => _PotentiallyNotSequentialRegisters.ContainsKey(register);
+
+
+        public string PotentiallyNotSequentialRegisters
+        {
+            get => throw new NotImplementedException();
+            set
+            {
+                foreach (var r in value.Split(';'))
+                    _PotentiallyNotSequentialRegisters[r] = true;
+            }
+        }
+
         public string IgnoredSubregisterPrefixes
         {
             get
@@ -1518,9 +1533,14 @@ private static Dictionary<string, List<HardwareSubRegister>> ProcessSubregisters
                         {
                             ExtractFirstBitAndSize(ParseHex(address_offset), out size, out offset);
                         }
-                        catch(Exception ex)
+                        catch
                         {
-                            errors.AddError(new RegisterParserErrors.BitmaskNotSequential { FileName = fileName, LineContents = line, LineNumber = nextLine - 1 });
+                            if (cfg.IsKnownNonSequentialRegister(subreg_name))
+                            {
+                                //Nothing to do - ignore the error.
+                            }
+                            else
+                                errors.AddError(new RegisterParserErrors.BitmaskNotSequential { FileName = fileName, LineContents = line, LineNumber = nextLine - 1 });
                             continue;
                         }
 
diff --git a/generators/stm32/rules/Families/stm32f0.xml b/generators/stm32/rules/Families/stm32f0.xml
@@ -212,6 +212,7 @@
 		<Framework>
 			<Name>STM32F0 Legacy Peripheral Library</Name>
 			<ID>com.sysprogs.arm.stm32.f0_stdperiph</ID>
+			<ClassID>com.sysprogs.arm.stm32.stdperiph</ClassID>
 			<IncompatibleFrameworks>
 				<string>com.sysprogs.arm.stm32.f0_hal</string>
 			</IncompatibleFrameworks>
diff --git a/generators/stm32/rules/Families/stm32f1.xml b/generators/stm32/rules/Families/stm32f1.xml
@@ -191,6 +191,7 @@
 		<Framework>
 			<Name>STM32F1 Legacy Peripheral Library</Name>
 			<ID>com.sysprogs.arm.stm32.f1_stdperiph</ID>
+			<ClassID>com.sysprogs.arm.stm32.stdperiph</ClassID>
 			<IncompatibleFrameworks>
 				<string>com.sysprogs.arm.stm32.f1_hal</string>
 			</IncompatibleFrameworks>
diff --git a/generators/stm32/rules/Families/stm32f2.xml b/generators/stm32/rules/Families/stm32f2.xml
@@ -82,6 +82,7 @@
 		<Framework>
 			<Name>STM32F2 Legacy Peripheral Library</Name>
 			<ID>com.sysprogs.arm.stm32.f2_stdperiph</ID>
+			<ClassID>com.sysprogs.arm.stm32.stdperiph</ClassID>
 			<IncompatibleFrameworks>
 				<string>com.sysprogs.arm.stm32.f2_hal</string>
 			</IncompatibleFrameworks>
diff --git a/generators/stm32/rules/Families/stm32f4.xml b/generators/stm32/rules/Families/stm32f4.xml
@@ -172,6 +172,7 @@
 		<Framework>
 			<Name>STM32F4 Legacy Peripheral Library</Name>
 			<ID>com.sysprogs.arm.stm32.f4_stdperiph</ID>
+			<ClassID>com.sysprogs.arm.stm32.stdperiph</ClassID>
 			<IncompatibleFrameworks>
 				<string>com.sysprogs.arm.stm32.f4_hal</string>
 			</IncompatibleFrameworks>
diff --git a/generators/stm32/rules/Families/stm32f7.xml b/generators/stm32/rules/Families/stm32f7.xml
@@ -77,6 +77,7 @@
 		<Framework>
 			<Name>STM32746G-Discovery drivers</Name>
 			<ID>com.sysprogs.arm.stm32.bspdrv.stm2746g-discovery</ID>
+			<ClassID>com.sysprogs.arm.stm32.bspdrv</ClassID>
 			<RequiredFrameworks>
 				<string>com.sysprogs.arm.stm32.f7_hal</string>
 			</RequiredFrameworks>
@@ -129,6 +130,7 @@
 			<RequiredFrameworks>
 				<string>com.sysprogs.arm.stm32.f7_hal</string>
 			</RequiredFrameworks>
+			<ClassID>com.sysprogs.arm.stm32.bspdrv</ClassID>
 			<IncompatibleFrameworks>
 				<string>com.sysprogs.arm.stm32.stm2746g-discovery</string>
 			</IncompatibleFrameworks>
diff --git a/generators/stm32/rules/Families/stm32h7.xml b/generators/stm32/rules/Families/stm32h7.xml
@@ -70,6 +70,7 @@
 		<Framework>
 			<Name>STM32H743I_EVAL drivers</Name>
 			<ID>com.sysprogs.arm.stm32.bspdrv.stm32h743i_eval</ID>
+			<ClassID>com.sysprogs.arm.stm32.bspdrv</ClassID>
 			<RequiredFrameworks>
 				<string>com.sysprogs.arm.stm32.h7_hal</string>
 			</RequiredFrameworks>
@@ -119,6 +120,7 @@
 		<Framework>
 			<Name>STM32H7xx_Nucleo_144</Name>
 			<ID>com.sysprogs.arm.stm32.bspdrv.nucleo144</ID>
+			<ClassID>com.sysprogs.arm.stm32.bspdrv</ClassID>
 			<RequiredFrameworks>
 				<string>com.sysprogs.arm.stm32.h7_hal</string>
 			</RequiredFrameworks>
diff --git a/generators/stm32/rules/Families/stm32l1.xml b/generators/stm32/rules/Families/stm32l1.xml
@@ -189,6 +189,7 @@
 		<Framework>
 			<Name>STM32L1 Legacy Peripheral Library</Name>
 			<ID>com.sysprogs.arm.stm32.l1_stdperiph</ID>
+			<ClassID>com.sysprogs.arm.stm32.stdperiph</ClassID>
 			<IncompatibleFrameworks>
 				<string>com.sysprogs.arm.stm32.l1_hal</string>
 			</IncompatibleFrameworks>
diff --git a/generators/stm32/rules/PeripheralRegisters.xml b/generators/stm32/rules/PeripheralRegisters.xml
@@ -1,12 +1,13 @@
 <?xml version="1.0"?>
 <RegisterParserConfiguration xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2001/XMLSchema">
-	<IgnoredSubregisters>USB_HS_PHYC_PLL1_PLLSEL_12MHZ;EXTI_EMR2_EM;EXTI_IMR2_IM;TIM_SMCR_TS;ETH_DMACCR_DSL_0BIT;ETH_MACHWF0R_ACTPHYSEL_MII;ETH_MACPFR_PCF_BLOCKALL;CRYP_CR_ALGOMODE_AES_CCM;EXTI_IMR1_IM;RI_ASCR2_GR6;SYSCFG_VREFINT_ADC_RDYF;SYSCFG_SWP_FSMC;RTC_BKP_NUMBER;EXTI_IMR_IM;DSI_VR;AFIO_MAPR_PD01_REMAP;AFIO_MAPR_TIM5CH4_IREMAP;AFIO_MAPR_ADC1_ETRGINJ_REMAP;AFIO_MAPR_ADC1_ETRGREG_REMAP;AFIO_MAPR_ADC2_ETRGINJ_REMAP;AFIO_MAPR_ADC2_ETRGREG_REMAP;ADC_CFGR2_TOVS;AFIO_MAPR_SWJ_CFG_RESET;AFIO_MAPR_SWJ_CFG_NOJNTRST;AFIO_MAPR_SWJ_CFG_JTAGDISABLE;AFIO_MAPR_SWJ_CFG_DISABLE;AFIO_MAPR_ETH_REMAP;AFIO_MAPR_CAN2_REMAP;AFIO_MAPR_MII_RMII_SEL;AFIO_MAPR_SPI3_REMAP;AFIO_MAPR_TIM2ITR1_IREMAP;AFIO_MAPR_PTP_PPS_REMAP;AFIO_MAPR2_TIM15_REMAP;AFIO_MAPR2_TIM16_REMAP;AFIO_MAPR2_TIM17_REMAP;AFIO_MAPR2_CEC_REMAP;AFIO_MAPR2_TIM1_DMA_REMAP;AFIO_MAPR2_TIM13_REMAP;AFIO_MAPR2_TIM14_REMAP;AFIO_MAPR2_FSMC_NADV_REMAP;AFIO_MAPR2_TIM67_DAC_DMA_REMAP;AFIO_MAPR2_TIM12_REMAP;AFIO_MAPR2_MISC_REMAP;AFIO_MAPR2_TIM9_REMAP;AFIO_MAPR2_TIM10_REMAP;AFIO_MAPR2_TIM11_REMAP;CRYP_CR_ALGOMODE;CRYP_CR_ALGOMODE_TDES_ECB;CRYP_CR_ALGOMODE_TDES_CBC;CRYP_CR_ALGOMODE_DES_ECB;CRYP_CR_ALGOMODE_DES_CBC;CRYP_CR_ALGOMODE_AES_ECB;CRYP_CR_ALGOMODE_AES_CBC;CRYP_CR_ALGOMODE_AES_CTR;CRYP_CR_ALGOMODE_AES_KEY;FLASH_FKEY1;FLASH_FKEY2;FLASH_OPTKEY1;FLASH_OPTKEY2;FLASH_OBR_USER;FLASH_OBR_RDPRT;FLASH_ACR_BYTE0_ADDRESS;FLASH_ACR_BYTE2_ADDRESS;FLASH_ACR_LATENCY_0;RDP_KEY;FLASH_KEY1;FLASH_KEY2;GPIO_CRL_MODE;GPIO_CRL_CNF;GPIO_CRH_MODE;GPIO_CRH_CNF;HASH_CR_ALGO;OB_USER_USER;OB_USER_nUSER;OB_WRP1_WRP1;OB_WRP1_nWRP1;OB_WRP3_WRP3;OB_WRP3_nWRP3;FLASH_USER_USER;FLASH_USER_nUSER;FLASH_Data1_Data1;FLASH_Data1_nData1;FLASH_Rsvd0_Rsvd0;FLASH_Rsvd0_nRsvd0;FLASH_Rsvd2_Rsvd2;FLASH_Rsvd2_nRsvd2;RCC_CFGR_SW_HSI;RCC_CFGR_SW_HSE;RCC_CFGR_SW_PLL;RCC_CFGR_SW_MSI;RCC_CFGR_SW_HSI48;RCC_CFGR_SWS_HSI;RCC_CFGR_SWS_HSE;RCC_CFGR_SWS_PLL;RCC_CFGR_SWS_MSI;RCC_CFGR_SWS_HSI48;RCC_CFGR_PLLSRC_HSE;RCC_CFGR_PLLSRC_HSI;RCC_CFGR_PLLSRC_PREDIV1;RCC_CFGR_PLLSRC_HSI_DIV2;RCC_CFGR_PLLSRC_HSI_PREDIV;RCC_CFGR_PLLSRC_HSE_PREDIV;RCC_CFGR_PLLSRC_HSI48_PREDIV;RCC_CFGR_PLLXTPRE_PREDIV1;RCC_CFGR_PLLXTPRE_HSE;RCC_CFGR_PLLXTPRE_HSE_Div2;RCC_CFGR_PLLXTPRE_PREDIV1_Div2;RCC_CFGR_MCO_NOCLOCK;RCC_CFGR_MCO_PLLCLK_Div2;RCC_CFGR_MCO_PLL2CLK;RCC_CFGR_MCO_PLL3CLK_Div2;RCC_CFGR_MCO_PLL3CLK;RCC_CFGR_PLLSRC_HSI_Div2;RCC_CFGR_MCO_Ext_HSE;RCC_CFGR_MCO_HSI14;RCC_CFGR_MCO_LSI;RCC_CFGR_MCO_MSI;RCC_CFGR_MCO_LSE;RCC_CFGR_MCO_SYSCLK;RCC_CFGR_MCO_HSI;RCC_CFGR_MCO_HSE;RCC_CFGR_MCO_PLL;RCC_CFGR_MCO_HSI48;RCC_CFGR2_ADCPRE12_NO;RCC_CFGR2_ADCPRE34_NO;RCC_CFGR2_PREDIV1SRC;RCC_CFGR2_PREDIV1SRC_PLL2;RCC_CFGR2_PREDIV1SRC_HSE;RCC_CFGR2_I2S2SRC;RCC_CFGR2_I2S3SRC;RCC_CSR_RTCSEL_NOCLOCK;RCC_CSR_RTCSEL_LSE;RCC_CSR_RTCSEL_LSI;RCC_CSR_RTCSEL_HSE;RCC_BDCR_RTCSEL_NOCLOCK;RCC_BDCR_RTCSEL_LSE;RCC_BDCR_RTCSEL_LSI;RCC_BDCR_RTCSEL_HSE;RCC_PLLCFGR_PLLSRC_HSE;RCC_PLLCFGR_PLLSRC_HSI;RI_ASCR1_CH;TIM_IMR_RSVD;TIM_SMCR_SMS;TIM_CCMR1_OC1M;TIM_CCMR1_OC2M;USART_CR1_M;SPDIFRX_DIR_THI;RCC_CFGR_MCO_EXT_HSE;FLASH_OPTKEYR_OPTKEYR2;FLASH_AR_FAR2;SYSCFG_CFGR1_DMA_RMP;RCC_CFGR2_ADC1PRES_NO;LPTIM_CR_SNGSTRT;TIM9_OR_ITR1_RMP;TIM2_OR_ITR1_RMP;TIM3_OR_ITR2_RMP;RCC_PLLCFGR_PLLSRC_MSI;SYSCFG_SKR_KEY;AES_CR_CHMOD;DAC_SR_BWST1;I2C_OAR2_OA2NOMASK</IgnoredSubregisters>
+	<IgnoredSubregisters>USB_HS_PHYC_PLL1_PLLSEL_12MHZ;EXTI_EMR2_EM;EXTI_IMR2_IM;ETH_DMACCR_DSL_0BIT;ETH_MACHWF0R_ACTPHYSEL_MII;ETH_MACPFR_PCF_BLOCKALL;CRYP_CR_ALGOMODE_AES_CCM;EXTI_IMR1_IM;RI_ASCR2_GR6;SYSCFG_VREFINT_ADC_RDYF;SYSCFG_SWP_FSMC;RTC_BKP_NUMBER;EXTI_IMR_IM;DSI_VR;AFIO_MAPR_PD01_REMAP;AFIO_MAPR_TIM5CH4_IREMAP;AFIO_MAPR_ADC1_ETRGINJ_REMAP;AFIO_MAPR_ADC1_ETRGREG_REMAP;AFIO_MAPR_ADC2_ETRGINJ_REMAP;AFIO_MAPR_ADC2_ETRGREG_REMAP;ADC_CFGR2_TOVS;AFIO_MAPR_SWJ_CFG_RESET;AFIO_MAPR_SWJ_CFG_NOJNTRST;AFIO_MAPR_SWJ_CFG_JTAGDISABLE;AFIO_MAPR_SWJ_CFG_DISABLE;AFIO_MAPR_ETH_REMAP;AFIO_MAPR_CAN2_REMAP;AFIO_MAPR_MII_RMII_SEL;AFIO_MAPR_SPI3_REMAP;AFIO_MAPR_TIM2ITR1_IREMAP;AFIO_MAPR_PTP_PPS_REMAP;AFIO_MAPR2_TIM15_REMAP;AFIO_MAPR2_TIM16_REMAP;AFIO_MAPR2_TIM17_REMAP;AFIO_MAPR2_CEC_REMAP;AFIO_MAPR2_TIM1_DMA_REMAP;AFIO_MAPR2_TIM13_REMAP;AFIO_MAPR2_TIM14_REMAP;AFIO_MAPR2_FSMC_NADV_REMAP;AFIO_MAPR2_TIM67_DAC_DMA_REMAP;AFIO_MAPR2_TIM12_REMAP;AFIO_MAPR2_MISC_REMAP;AFIO_MAPR2_TIM9_REMAP;AFIO_MAPR2_TIM10_REMAP;AFIO_MAPR2_TIM11_REMAP;CRYP_CR_ALGOMODE;CRYP_CR_ALGOMODE_TDES_ECB;CRYP_CR_ALGOMODE_TDES_CBC;CRYP_CR_ALGOMODE_DES_ECB;CRYP_CR_ALGOMODE_DES_CBC;CRYP_CR_ALGOMODE_AES_ECB;CRYP_CR_ALGOMODE_AES_CBC;CRYP_CR_ALGOMODE_AES_CTR;CRYP_CR_ALGOMODE_AES_KEY;FLASH_FKEY1;FLASH_FKEY2;FLASH_OPTKEY1;FLASH_OPTKEY2;FLASH_OBR_USER;FLASH_OBR_RDPRT;FLASH_ACR_BYTE0_ADDRESS;FLASH_ACR_BYTE2_ADDRESS;FLASH_ACR_LATENCY_0;RDP_KEY;FLASH_KEY1;FLASH_KEY2;GPIO_CRL_MODE;GPIO_CRL_CNF;GPIO_CRH_MODE;GPIO_CRH_CNF;HASH_CR_ALGO;OB_USER_USER;OB_USER_nUSER;OB_WRP1_WRP1;OB_WRP1_nWRP1;OB_WRP3_WRP3;OB_WRP3_nWRP3;FLASH_USER_USER;FLASH_USER_nUSER;FLASH_Data1_Data1;FLASH_Data1_nData1;FLASH_Rsvd0_Rsvd0;FLASH_Rsvd0_nRsvd0;FLASH_Rsvd2_Rsvd2;FLASH_Rsvd2_nRsvd2;RCC_CFGR_SW_HSI;RCC_CFGR_SW_HSE;RCC_CFGR_SW_PLL;RCC_CFGR_SW_MSI;RCC_CFGR_SW_HSI48;RCC_CFGR_SWS_HSI;RCC_CFGR_SWS_HSE;RCC_CFGR_SWS_PLL;RCC_CFGR_SWS_MSI;RCC_CFGR_SWS_HSI48;RCC_CFGR_PLLSRC_HSE;RCC_CFGR_PLLSRC_HSI;RCC_CFGR_PLLSRC_PREDIV1;RCC_CFGR_PLLSRC_HSI_DIV2;RCC_CFGR_PLLSRC_HSI_PREDIV;RCC_CFGR_PLLSRC_HSE_PREDIV;RCC_CFGR_PLLSRC_HSI48_PREDIV;RCC_CFGR_PLLXTPRE_PREDIV1;RCC_CFGR_PLLXTPRE_HSE;RCC_CFGR_PLLXTPRE_HSE_Div2;RCC_CFGR_PLLXTPRE_PREDIV1_Div2;RCC_CFGR_MCO_NOCLOCK;RCC_CFGR_MCO_PLLCLK_Div2;RCC_CFGR_MCO_PLL2CLK;RCC_CFGR_MCO_PLL3CLK_Div2;RCC_CFGR_MCO_PLL3CLK;RCC_CFGR_PLLSRC_HSI_Div2;RCC_CFGR_MCO_Ext_HSE;RCC_CFGR_MCO_HSI14;RCC_CFGR_MCO_LSI;RCC_CFGR_MCO_MSI;RCC_CFGR_MCO_LSE;RCC_CFGR_MCO_SYSCLK;RCC_CFGR_MCO_HSI;RCC_CFGR_MCO_HSE;RCC_CFGR_MCO_PLL;RCC_CFGR_MCO_HSI48;RCC_CFGR2_ADCPRE12_NO;RCC_CFGR2_ADCPRE34_NO;RCC_CFGR2_PREDIV1SRC;RCC_CFGR2_PREDIV1SRC_PLL2;RCC_CFGR2_PREDIV1SRC_HSE;RCC_CFGR2_I2S2SRC;RCC_CFGR2_I2S3SRC;RCC_CSR_RTCSEL_NOCLOCK;RCC_CSR_RTCSEL_LSE;RCC_CSR_RTCSEL_LSI;RCC_CSR_RTCSEL_HSE;RCC_BDCR_RTCSEL_NOCLOCK;RCC_BDCR_RTCSEL_LSE;RCC_BDCR_RTCSEL_LSI;RCC_BDCR_RTCSEL_HSE;RCC_PLLCFGR_PLLSRC_HSE;RCC_PLLCFGR_PLLSRC_HSI;RI_ASCR1_CH;TIM_IMR_RSVD;TIM_CCMR1_OC1M;TIM_CCMR1_OC2M;USART_CR1_M;SPDIFRX_DIR_THI;RCC_CFGR_MCO_EXT_HSE;FLASH_OPTKEYR_OPTKEYR2;FLASH_AR_FAR2;SYSCFG_CFGR1_DMA_RMP;RCC_CFGR2_ADC1PRES_NO;LPTIM_CR_SNGSTRT;TIM9_OR_ITR1_RMP;TIM2_OR_ITR1_RMP;TIM3_OR_ITR2_RMP;RCC_PLLCFGR_PLLSRC_MSI;SYSCFG_SKR_KEY;AES_CR_CHMOD;DAC_SR_BWST1;I2C_OAR2_OA2NOMASK</IgnoredSubregisters>
 	<IgnoredSubregisterPrefixes>PWR_CR1_ALS_LEV;FLASH_CRCCR_CRC_BURST_;FLASH_OPTCR_RDP_;FLASH_ACR_WRHIGHFREQ_;FLASH_CR_SNB_;ETH_DMADSR;ETH_DMAMR_PR_;ETH_MACWTR_WTO;ETH_MACCR_;RTC_CAL_;DCMI_MISR_;DCMI_RISR_;DMA2D_IFSR_;GPIO_OTYPER_ODR_;GPIO_OTYPER_IDR_;RCC_CFGR_MCOSEL_;GPIO_BSRR_BS_;GPIO_BSRR_BR_;AFIO_EVCR_PIN_PX;AFIO_EVCR_PORT_P;AFIO_EXTICR1_EXTI0_;COMP_CSR_COMP2SPEED;AFIO_EXTICR1_EXTI1_;AFIO_EXTICR1_EXTI2_;AFIO_EXTICR1_EXTI3_;COMP_CSR_COMPx;AFIO_EXTICR2_EXTI4_;AFIO_EXTICR2_EXTI5_;AFIO_EXTICR2_EXTI6_;AFIO_EXTICR2_EXTI7_;AFIO_EXTICR3_EXTI8_;AFIO_EXTICR3_EXTI9_;AFIO_EXTICR3_EXTI10_;AFIO_EXTICR3_EXTI11_;AFIO_EXTICR4_EXTI12_;AFIO_EXTICR4_EXTI13_;AFIO_EXTICR4_EXTI14_;AFIO_EXTICR4_EXTI15_;ETH_MACCR_IFG_;ETH_MACCR_BL_;ETH_MACFFR_PCF_;ETH_MACMIIAR_CR_;ETH_MACFCR_PLT_;ETH_MACA1HR_MBC_;ETH_MACA2HR_MBC_;ETH_MACA3HR_MBC_;ETH_DMABMR_RDP_;ETH_DMABMR_RTPR_;ETH_DMABMR_PBL_;ETH_DMASR_EBS_;ETH_DMASR_TPS_;ETH_DMAOMR_RTC_;ETH_DMAOMR_TTC_;ETH_DMASR_RPS_;ETH_DMASR_RPS_;PWR_CR_PLS_LEV;PWR_CR_PLS_2V;RCC_CFGR_HPRE_DIV;RCC_CFGR_PPRE_DIV;RCC_CFGR_PPRE1_DIV;RCC_CFGR_PPRE2_DIV;RCC_CFGR2_PREDIV1_DIV;RCC_CFGR2_PPRE2_DIV;RCC_CFGR_ADCPRE_DIV;RCC_CFGR2_ADCPRE12_DIV;RCC_CFGR2_ADCPRE34_DIV;RCC_CFGR_MCO_DIV;RCC_CFGR_MCO_PRE_;RCC_CFGR2_PREDIV1_DIV;RCC_CFGR2_PREDIV2_DIV;RCC_CFGR_SDADCPRE_DIV;RCC_ICSCR_MSIRANGE_;SYSCFG_EXTICR1_EXTI0_;SYSCFG_EXTICR1_EXTI1_;SYSCFG_EXTICR1_EXTI2_;SYSCFG_EXTICR1_EXTI3_;SYSCFG_EXTICR2_EXTI4_;SYSCFG_EXTICR2_EXTI5_;SYSCFG_EXTICR2_EXTI6_;SYSCFG_EXTICR2_EXTI7_;SYSCFG_EXTICR3_EXTI8_;SYSCFG_EXTICR3_EXTI9_;SYSCFG_EXTICR3_EXTI10_;SYSCFG_EXTICR3_EXTI11_;SYSCFG_EXTICR3_EXTI12_;SYSCFG_EXTICR3_EXTI13_;SYSCFG_EXTICR3_EXTI14_;SYSCFG_EXTICR3_EXTI15_;SYSCFG_EXTICR4_EXTI12_;SYSCFG_EXTICR4_EXTI13_;SYSCFG_EXTICR4_EXTI14_;SYSCFG_EXTICR4_EXTI15_;SYSCFG_EXTIRCR_EXTI4_;SYSCFG_EXTIRCR_EXTI5_;SYSCFG_EXTIRCR_EXTI6_;SYSCFG_EXTIRCR_EXTI7_;DMA_RMPCR;SYSCFG_ITLINE;RCC_CFGR_MCO_PLL3CLK_DIV;DMA1_CSELR;DMA2_CSELR;PWR_CR1_PLS_LEV;AES_KEYR;AES_SUSP;FLASH_OPTR_BOR_LEV_;RCC_CR_MSIRANGE_;I2C_OAR2_OA2MASK0;PWR_CR1_LPMS_;PWR_CR2_PLS_;RCC_CSR_MSISRANGE_</IgnoredSubregisterPrefixes>
 	<IgnoredSubregisterRegexes>RCC_.*_(DIV[12468]*|HSI);ETH_.*BITS.*;ETH_.*_DIV.*;ETH_MACTFCR_PLT_MINUS.*;VREFBUF_CSR_VRS_OUT[0-4]?;RCC_CFGR2?_PLL[23]?(MULL?[23]?|DIV)[^_].*;SCB_AIRCR_PRIGROUP[^_]+;FLASH_ACR_LATENCY_.*WS;FLASH_DATA[0-9]_n?DATA[0-9];CAN_FFA[0-9]R?_FFA[0-9]+;RCC_CFGR3_[^_]+SW.*;RCC_CFGR.*(DIV|SRC).*;COMP[0-9]?_CSR_COMP[0-9]?I(N|P|)NSEL.*;TIM_CCMR[23]_OC[0-9]M.*;FLASH_WRPR?[1-9]?_n?WRP[1-9]?;FW_[A-Z]+_(ADD|LENG)</IgnoredSubregisterRegexes>
 	<IgnoredSubregisterSuffixes>_EMPTY;_IDLE;_NOVLANTAG;_DONOTSTRIP;_REMAP1;_REMAP2;_REMAP3;_NOREMAP;_PARTIALREMAP;_PARTIALREMAP1;_PARTIALREMAP;_FULLREMAP</IgnoredSubregisterSuffixes>
 	<IgnoredMismatchingSubregisters>USB_HS_PHYC_USB_HS_PHYC_PLL;COMP_CSR_COMP2SW1;COMP_CSR_COMP1SW1;RTC_BKP0R;DMA_SxNDT;AES_DINR;AES_DOUTR;AES_KEYR0;AES_KEYR1;AES_KEYR2;AES_KEYR3;AES_IVR0;AES_IVR1;AES_IVR2;AES_IVR3;RTC_BKP.*;NVIC.*;SysTick.*;SCB_.*;TIM(2|21|22|3)_OR_.*;HRTIM1?_.*</IgnoredMismatchingSubregisters>
 	<IgnoredDefinitionsInBaseAddressArea>SRAM3_SIZE;FLASH_OTP_BANK1_END;FLASH_OTP_BANK2_END;OPAMP12_COMMON;OPAMP1_COMMON;COMP12_COMMON;FSMC_BANK1;FSMC_BANK1_1;FSMC_BANK1_2;FSMC_BANK1_3;FSMC_BANK1_4;FSMC_BANK2;FSMC_BANK3;FSMC_BANK4;SRAM1_SIZE_MAX;SRAM2_SIZE;FMC_BANK1;FMC_BANK;FMC_BANK1_1;FMC_BANK1_2;FMC_BANK1_3;FMC_BANK1_4;FMC_BANK2;FMC_BANK3;FMC_BANK4</IgnoredDefinitionsInBaseAddressArea>
 	<KnownRegistersWithoutSubregisters>OCTOSPIM/PCR[12];GFXMMU/LUT.*;SDMMC[12]/ACKTIME|IDMABSIZE|IDMABASE[01];USB[12]_OTG_[HF]S/GSNPSID|GHWCFG[12];|MDIOS/R.*|WRFR|CWRFR|CRDFR;HSEM/R.*;ETH/MAC.*|DMACSFCSR|MMC.*;SDMMC.*/IPVR;CRYP/DIN;EXTI/D3PCR.*;SYSCFG/UR1;TIM([2356479]|10|11|13|14|12|15|16|17)/AF[21]|TISEL;TIM[23]/AF2;FLASH/KEYR2|OPTSR.*|PRAR_.*|SCAR_.*|WPSN_.*|BOOT_.*;DAC1/DHR12R2|DHR12L2|DHR8R2|DOR2|SHSR2;USB_HS_PHYC/USB_HS_PHYC_TUNE;PWR/PUCRD|PDCRD|PUCRE|PDCRE;OPAMP123_COMMON/OTR;OPAMP12_COMMON/OTR;RTC/BKP.*;JPEG/QMEM[0-9]+|HUFFMIN[0-9]*|HUFFBASE[0-9]*|HUFFSYMB[0-9]*|DHTMEM[0-9]+|HUFFENC_AC[0-9]+|HUFFENC_DC[0-9]+;MDIOS/DINR[0-9]+|DOUTR[0-9]+;COMP56_COMMON/CSR;COMP34_COMMON/CSR;COMP12_COMMON/CSR;OB/DATA[01]|RDP|USER|WRP.*;TSC/.*;FS?MC_Bank1E?/BTCR|BWTR;GPIO.*/LCKR|AFR[LH];FLASH/KEYR|OPTKEYR;DMA[12]_Stream.*/PAR|M0AR|M1AR;ETH/DMARSWTR;DCMI/ESCR|ESUR|CWSTRTR|CWSIZER|DR;CRYP/CSGCM.*|CSGCMCCM.*|DR|DOUT|K[0123][LR]R|IV[01][LR]R;(HASH|HASH_DIGEST)/HR.*|CSR.*|DIN;RNG/DR;TIM.*/OR;DMA2D/IFCR|[FB]GCLUT.*;CMD_BANK1:BTCR.*;GPIO:BRR.*;MEM:(RAM|DMA)PROTR.*|RAMCR;SC_DMA_Channel:DMA(BEG|END)ADD[AB]R;RTC:CALR.*;FW:.*;DMA_Request:.*;SYSCFG:IT_LINE_SR.*|PMC;DMA:RPMCR;SPDIFRX:DR;USB_OTG:GHWCFG3|GDFIFOCFG|GADPCTL;I2C.*/DR;COMP:CSR;DMA:CSELR;USB:EP.*|ISTR|DADDR|BTABLE|LPMCS?R;CRC:POL;LPTIM:OR;FLASH:WRPR[0-9];TIM[0-9]+/OR[0-9]+;FIREWALL:.*;FLASH:PDKEYR;USB_OTG_FS/GSNPSID|GHWCFG1|GHWCFG2;RCC/CKGATENR;SYSCFG/CFGR2|SWPR2;RCC/AHB3ENR</KnownRegistersWithoutSubregisters>
+	<PotentiallyNotSequentialRegisters>TIM_SMCR_TS;TIM_SMCR_SMS</PotentiallyNotSequentialRegisters>
 	<RegisterSetRenameRules>
 
 
diff --git a/libraries/BSPGenerationTools/BSPGeneratorTools.cs b/libraries/BSPGenerationTools/BSPGeneratorTools.cs
@@ -304,13 +304,21 @@ public void ValidateBSP(BoardSupportPackage bsp)
                 }
             }
 
-            HashSet<string> usedFolders = new HashSet<string>();
+            Dictionary<string, string> usedFoldersToCompatibleIDs = new Dictionary<string, string>();
+            int ambiguousFolders = 0;
             foreach(var fw in bsp.Frameworks ?? new EmbeddedFramework[0])
             {
-                if (usedFolders.Contains(fw.ProjectFolderName))
-                    throw new Exception($"'{fw.ProjectFolderName}' is used by more than 1 framework. This will break builds in Visual Studio.");
-                usedFolders.Add(fw.ProjectFolderName);
+                var id = fw.ClassID ?? fw.ID;
+                if (usedFoldersToCompatibleIDs.TryGetValue(fw.ProjectFolderName, out var tmp) && tmp != id)
+                {
+                    ambiguousFolders++;
+                    Console.WriteLine($"'{fw.ProjectFolderName}' is used by both {id} and {tmp}. This will break builds in Visual Studio.");
+                }
+                usedFoldersToCompatibleIDs[fw.ProjectFolderName] = id;
             }
+
+            if (ambiguousFolders > 0)
+                throw new Exception($"Found {ambiguousFolders} ambiguous folders. Please check the generator output.");
         }
     }
 

Original file line number	Diff line number	Diff line change
`@@ -41,6 +41,7 @@ public override string ToString()`
`41`	`41`	`public class RegisterParserConfiguration`
`42`	`42`	`{`
`43`	`43`	`Dictionary<string, bool> _IgnoredSubregisters = new Dictionary<string, bool>();`
	`44`	`+ Dictionary<string, bool> _PotentiallyNotSequentialRegisters = new Dictionary<string, bool>();`
`44`	`45`	`string[] _IgnoredSubregisterPrefixes;`
`45`	`46`	`string[] _IgnoredSubregisterSuffixes;`
`46`	`47`	`Regex[] _IgnoredSubregisterRegexes;`
`@@ -271,6 +272,20 @@ public string IgnoredSubregisters`
`271`	`272`	`}`
`272`	`273`	`}`
`273`	`274`
	`275`	`+ //Those registers might be non-sequential for some devices, but not all. We will only ignore the actual non-sequential instances of them.`
	`276`	`+ public bool IsKnownNonSequentialRegister(string register) => _PotentiallyNotSequentialRegisters.ContainsKey(register);`
	`277`	`+`
	`278`	`+`
	`279`	`+ public string PotentiallyNotSequentialRegisters`
	`280`	`+ {`
	`281`	`+ get => throw new NotImplementedException();`
	`282`	`+ set`
	`283`	`+ {`
	`284`	`+ foreach (var r in value.Split(';'))`
	`285`	`+ _PotentiallyNotSequentialRegisters[r] = true;`
	`286`	`+ }`
	`287`	`+ }`
	`288`	`+`
`274`	`289`	`public string IgnoredSubregisterPrefixes`
`275`	`290`	`{`
`276`	`291`	`get`
`@@ -1518,9 +1533,14 @@ private static Dictionary<string, List<HardwareSubRegister>> ProcessSubregisters`
`1518`	`1533`	`{`
`1519`	`1534`	`ExtractFirstBitAndSize(ParseHex(address_offset), out size, out offset);`
`1520`	`1535`	`}`
`1521`		`- catch(Exception ex)`
	`1536`	`+ catch`
`1522`	`1537`	`{`
`1523`		`- errors.AddError(new RegisterParserErrors.BitmaskNotSequential { FileName = fileName, LineContents = line, LineNumber = nextLine - 1 });`
	`1538`	`+ if (cfg.IsKnownNonSequentialRegister(subreg_name))`
	`1539`	`+ {`
	`1540`	`+ //Nothing to do - ignore the error.`
	`1541`	`+ }`
	`1542`	`+ else`
	`1543`	`+ errors.AddError(new RegisterParserErrors.BitmaskNotSequential { FileName = fileName, LineContents = line, LineNumber = nextLine - 1 });`
`1524`	`1544`	`continue;`
`1525`	`1545`	`}`
`1526`	`1546`
Original file line number	Diff line number	Diff line change
`@@ -304,13 +304,21 @@ public void ValidateBSP(BoardSupportPackage bsp)`
`304`	`304`	`}`
`305`	`305`	`}`
`306`	`306`
`307`		`- HashSet<string> usedFolders = new HashSet<string>();`
	`307`	`+ Dictionary<string, string> usedFoldersToCompatibleIDs = new Dictionary<string, string>();`
	`308`	`+ int ambiguousFolders = 0;`
`308`	`309`	`foreach(var fw in bsp.Frameworks ?? new EmbeddedFramework[0])`
`309`	`310`	`{`
`310`		`- if (usedFolders.Contains(fw.ProjectFolderName))`
`311`		`- throw new Exception($"'{fw.ProjectFolderName}' is used by more than 1 framework. This will break builds in Visual Studio.");`
`312`		`- usedFolders.Add(fw.ProjectFolderName);`
	`311`	`+ var id = fw.ClassID ?? fw.ID;`
	`312`	`+ if (usedFoldersToCompatibleIDs.TryGetValue(fw.ProjectFolderName, out var tmp) && tmp != id)`
	`313`	`+ {`
	`314`	`+ ambiguousFolders++;`
	`315`	`+ Console.WriteLine($"'{fw.ProjectFolderName}' is used by both {id} and {tmp}. This will break builds in Visual Studio.");`
	`316`	`+ }`
	`317`	`+ usedFoldersToCompatibleIDs[fw.ProjectFolderName] = id;`
`313`	`318`	`}`
	`319`	`+`
	`320`	`+ if (ambiguousFolders > 0)`
	`321`	`+ throw new Exception($"Found {ambiguousFolders} ambiguous folders. Please check the generator output.");`
`314`	`322`	`}`
`315`	`323`	`}`
`316`	`324`