@@ -23,21 +23,7 @@ class Zicsr : public RevExt {
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// / Modify a CSR Register according to CSRRW, CSRRS, or CSRRC
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// Because CSR has a 32/64-bit width, this function is templatized
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template <typename XLEN, OpKind OPKIND, CSROp OP>
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- static bool ModCSRImpl ( RevFeature* F, RevRegFile* R, RevMem* M, const RevInst& Inst ) {
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-
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- // Alternative forms of rdcycle[h], rdtime[h], rdinstret[h] which use an immediate 0 or csrrc
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- // Canonical forms of rdcycle[h], rdtime[h], rdinstret[h] use csrrs with register x0
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- if ( OP != CSROp::Write && Inst.rs1 == 0 ) {
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- switch ( Inst.imm ) {
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- case 0xc00 : return rdcycle ( F, R, M, Inst );
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- case 0xc80 : return rdcycleh ( F, R, M, Inst );
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- case 0xc01 : return rdtime ( F, R, M, Inst );
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- case 0xc81 : return rdtimeh ( F, R, M, Inst );
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- case 0xc02 : return rdinstret ( F, R, M, Inst );
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- case 0xc82 : return rdinstreth ( F, R, M, Inst );
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- }
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- }
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-
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+ static bool ModCSRImpl ( RevRegFile* R, const RevInst& Inst ) {
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XLEN old = 0 ;
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// CSRRW with rd == zero does not read CSR
@@ -81,7 +67,7 @@ class Zicsr : public RevExt {
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// This calls the 32/64-bit ModCSR depending on the current XLEN
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template <OpKind OPKIND, CSROp OP>
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static bool ModCSR ( RevFeature* F, RevRegFile* R, RevMem* M, const RevInst& Inst ) {
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- return R->IsRV32 ? ModCSRImpl<uint32_t , OPKIND, OP>( F, R, M, Inst ) : ModCSRImpl<uint64_t , OPKIND, OP>( F, R, M , Inst );
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+ return R->IsRV32 ? ModCSRImpl<uint32_t , OPKIND, OP>( R, Inst ) : ModCSRImpl<uint64_t , OPKIND, OP>( R , Inst );
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}
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static constexpr auto & csrrw = ModCSR<OpKind::Reg, CSROp::Write>;
@@ -91,53 +77,6 @@ class Zicsr : public RevExt {
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static constexpr auto & csrrsi = ModCSR<OpKind::Imm, CSROp::Set>;
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static constexpr auto & csrrci = ModCSR<OpKind::Imm, CSROp::Clear>;
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- // Performance counters
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- // TODO: These should be moved to a separate Zicntr extension, but right now the
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- // spec is unclear on what order Zicntr should appear in an architecture string
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-
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- // template is used to break circular dependencies and allow for an incomplete RevCore type now
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- template <typename T, typename = std::enable_if_t <std::is_same_v<T, RevRegFile>>>
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- static uint64_t rdcycleImpl ( RevFeature* F, T* R, RevMem* M, const RevInst& Inst ) {
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- return R->Core ->GetCycles ();
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- }
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-
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- template <typename T, typename = std::enable_if_t <std::is_same_v<T, RevRegFile>>>
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- static uint64_t rdtimeImpl ( RevFeature* F, T* R, RevMem* M, const RevInst& Inst ) {
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- return R->Core ->GetCurrentSimCycle ();
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- }
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-
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- static uint64_t rdinstretImpl ( RevFeature* F, RevRegFile* R, RevMem* M, const RevInst& Inst ) { return R->GetInstRet (); }
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-
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- enum Half { Lo, Hi };
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-
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- // / Performance Counter template
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- // Passed a function which gets the 64-bit value of a performance counter
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- template <Half HALF, uint64_t COUNTER ( RevFeature* F, RevRegFile* R, RevMem* M, const RevInst& Inst )>
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- static bool perfCounter( RevFeature* F, RevRegFile* R, RevMem* M, const RevInst& Inst ) {
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- if ( R->IsRV32 ) {
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- if constexpr ( HALF == Lo ) {
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- R->SetX ( Inst.rd , static_cast <uint32_t >( COUNTER ( F, R, M, Inst ) & 0xffffffff ) );
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- } else {
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- R->SetX ( Inst.rd , static_cast <uint32_t >( COUNTER ( F, R, M, Inst ) >> 32 ) );
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- }
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- } else {
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- if constexpr ( HALF == Lo ) {
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- R->SetX ( Inst.rd , COUNTER ( F, R, M, Inst ) );
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- } else {
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- return false ; // Hi half is not available on RV64
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- }
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- }
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- R->AdvancePC ( Inst );
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- return true ;
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- }
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-
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- static constexpr auto & rdcycle = perfCounter<Lo, rdcycleImpl>;
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- static constexpr auto & rdcycleh = perfCounter<Hi, rdcycleImpl>;
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- static constexpr auto & rdtime = perfCounter<Lo, rdtimeImpl>;
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- static constexpr auto & rdtimeh = perfCounter<Hi, rdtimeImpl>;
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- static constexpr auto & rdinstret = perfCounter<Lo, rdinstretImpl>;
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- static constexpr auto & rdinstreth = perfCounter<Hi, rdinstretImpl>;
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-
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// ----------------------------------------------------------------------
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//
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// RISC-V CSR Instructions
@@ -178,12 +117,12 @@ class Zicsr : public RevExt {
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{ RevZicsrInstDefaults ().SetMnemonic ( " csrrci %rd, %csr, $imm" ).SetFunct3 ( 0b111 ).SetImplFunc ( csrrci ).SetPredicate ( []( uint32_t Inst ){ return DECODE_RD ( Inst ) != 0 ; } ) },
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{ RevZicsrInstDefaults ().SetMnemonic ( " csrci %csr, $imm" ).SetFunct3 ( 0b111 ).SetImplFunc ( csrrci ).SetPredicate ( []( uint32_t Inst ){ return DECODE_RD ( Inst ) == 0 ; } ) },
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- { RevZicsrInstDefaults ().SetMnemonic ( " rdcycle %rd" ).SetFunct3 ( 0b010 ).SetImplFunc ( rdcycle ).SetPredicate ( []( uint32_t Inst ){ return DECODE_RS1 ( Inst ) == 0 && DECODE_IMM12 ( Inst ) == 0xc00 ; } ) },
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- { RevZicsrInstDefaults ().SetMnemonic ( " rdcycleh %rd" ).SetFunct3 ( 0b010 ).SetImplFunc ( rdcycleh ).SetPredicate ( []( uint32_t Inst ){ return DECODE_RS1 ( Inst ) == 0 && DECODE_IMM12 ( Inst ) == 0xc80 ; } ) },
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- { RevZicsrInstDefaults ().SetMnemonic ( " rdtime %rd" ).SetFunct3 ( 0b010 ).SetImplFunc ( rdtime ).SetPredicate ( []( uint32_t Inst ){ return DECODE_RS1 ( Inst ) == 0 && DECODE_IMM12 ( Inst ) == 0xc01 ; } ) },
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- { RevZicsrInstDefaults ().SetMnemonic ( " rdtimeh %rd" ).SetFunct3 ( 0b010 ).SetImplFunc ( rdtimeh ).SetPredicate ( []( uint32_t Inst ){ return DECODE_RS1 ( Inst ) == 0 && DECODE_IMM12 ( Inst ) == 0xc81 ; } ) },
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- { RevZicsrInstDefaults ().SetMnemonic ( " rdinstret %rd" ).SetFunct3 ( 0b010 ).SetImplFunc ( rdinstret ).SetPredicate ( []( uint32_t Inst ){ return DECODE_RS1 ( Inst ) == 0 && DECODE_IMM12 ( Inst ) == 0xc02 ; } ) },
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- { RevZicsrInstDefaults ().SetMnemonic ( " rdinstreth %rd" ).SetFunct3 ( 0b010 ).SetImplFunc ( rdinstreth ).SetPredicate ( []( uint32_t Inst ){ return DECODE_RS1 ( Inst ) == 0 && DECODE_IMM12 ( Inst ) == 0xc82 ; } ) },
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+ { RevZicsrInstDefaults ().SetMnemonic ( " rdcycle %rd" ).SetFunct3 ( 0b010 ).SetImplFunc ( csrrs ).SetPredicate ( []( uint32_t Inst ){ return DECODE_RS1 ( Inst ) == 0 && DECODE_IMM12 ( Inst ) == 0xc00 ; } ) },
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+ { RevZicsrInstDefaults ().SetMnemonic ( " rdcycleh %rd" ).SetFunct3 ( 0b010 ).SetImplFunc ( csrrs ).SetPredicate ( []( uint32_t Inst ){ return DECODE_RS1 ( Inst ) == 0 && DECODE_IMM12 ( Inst ) == 0xc80 ; } ) },
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+ { RevZicsrInstDefaults ().SetMnemonic ( " rdtime %rd" ).SetFunct3 ( 0b010 ).SetImplFunc ( csrrs ).SetPredicate ( []( uint32_t Inst ){ return DECODE_RS1 ( Inst ) == 0 && DECODE_IMM12 ( Inst ) == 0xc01 ; } ) },
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+ { RevZicsrInstDefaults ().SetMnemonic ( " rdtimeh %rd" ).SetFunct3 ( 0b010 ).SetImplFunc ( csrrs ).SetPredicate ( []( uint32_t Inst ){ return DECODE_RS1 ( Inst ) == 0 && DECODE_IMM12 ( Inst ) == 0xc81 ; } ) },
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+ { RevZicsrInstDefaults ().SetMnemonic ( " rdinstret %rd" ).SetFunct3 ( 0b010 ).SetImplFunc ( csrrs ).SetPredicate ( []( uint32_t Inst ){ return DECODE_RS1 ( Inst ) == 0 && DECODE_IMM12 ( Inst ) == 0xc02 ; } ) },
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+ { RevZicsrInstDefaults ().SetMnemonic ( " rdinstreth %rd" ).SetFunct3 ( 0b010 ).SetImplFunc ( csrrs ).SetPredicate ( []( uint32_t Inst ){ return DECODE_RS1 ( Inst ) == 0 && DECODE_IMM12 ( Inst ) == 0xc82 ; } ) },
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};
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// clang-format on
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