Merge pull request #238 from tactcomplabs/fenv

Add support for CSR instructions, FP exception flags, FP rounding modes, Performance Counters

Author: leekillough

.gitignore

@@ -4,10 +4,9 @@
 *.csv
 .cache/clangd/index
 .vscode
-*.dylib
+*.o
 .#*
 *~
 .gdb_history
 *.out
-build/*
 *.asm

CMakeLists.txt

@@ -77,13 +77,13 @@ endif()
 # Compiler Options
 if ("${CMAKE_CXX_COMPILER_ID}" MATCHES "Clang")
   set(WERROR_FLAG "")
-  set(FP_MODE_FLAG "-ffp-model=strict")
+  set(FP_MODE_FLAG "-ffp-model=strict -frounding-math -ftrapping-math")
 else()
   set(WERROR_FLAG "-Werror")
-  set(FP_MODE_FLAG "-frounding-math")
+  set(FP_MODE_FLAG "-frounding-math -ftrapping-math")
 endif()
 
-set(CMAKE_CXX_FLAGS "-std=c++17 ${FP_MODE_FLAG} -O2 -Wall -Wextra ${WERROR_FLAG} -Wvla -Wuninitialized -Wfloat-conversion -Wdouble-promotion -Wno-unused-parameter -Wno-deprecated-declarations ${CMAKE_CXX_FLAGS} -I./ ${LDFLAGS} ${REVCPU_COMPILER_MACROS}")
+set(CMAKE_CXX_FLAGS "-std=c++17 ${FP_MODE_FLAG} -O2 -Wall -Wextra ${WERROR_FLAG} -Wvla -Wuninitialized -Wdouble-promotion -Wno-unused-parameter -Wno-deprecated-declarations ${CMAKE_CXX_FLAGS} -I./ ${LDFLAGS} ${REVCPU_COMPILER_MACROS}")
 set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} -O0 -Wall ${REVCPU_COMPILER_MACROS}")
 set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -O3 -Wall ${REVCPU_COMPILER_MACROS}")
 

include/AllRevInstTables.h

@@ -31,6 +31,7 @@
 #include "insns/RV64M.h"
 #include "insns/RV64P.h"
 #include "insns/Zicbom.h"
+#include "insns/Zicsr.h"
 #include "insns/Zifencei.h"
 
 #endif

include/RevCPU.h

@@ -212,17 +212,17 @@ class RevCPU : public SST::Component {
   }
 
 private:
-  unsigned              numCores{};      ///< RevCPU: number of RISC-V cores
-  unsigned              numHarts{};      ///< RevCPU: number of RISC-V cores
-  unsigned              msgPerCycle{};   ///< RevCPU: number of messages to send per cycle
-  unsigned              RDMAPerCycle{};  ///< RevCPU: number of RDMA messages per cycle to inject into PAN network
-  unsigned              testStage{};     ///< RevCPU: controls the PAN Test harness staging
-  unsigned              testIters{};     ///< RevCPU: the number of message iters for each PAN Test
-  RevOpts*              Opts{};          ///< RevCPU: Simulation options object
-  RevMem*               Mem{};           ///< RevCPU: RISC-V main memory object
-  RevLoader*            Loader{};        ///< RevCPU: RISC-V loader
-  std::vector<RevCore*> Procs{};         ///< RevCPU: RISC-V processor objects
-  bool*                 Enabled{};       ///< RevCPU: Completion structure
+  unsigned numCores{};     ///< RevCPU: number of RISC-V cores
+  unsigned numHarts{};     ///< RevCPU: number of RISC-V cores
+  unsigned msgPerCycle{};  ///< RevCPU: number of messages to send per cycle
+  //  unsigned          RDMAPerCycle{};  ///< RevCPU: number of RDMA messages per cycle to inject into PAN network
+  //  unsigned          testStage{};     ///< RevCPU: controls the PAN Test harness staging
+  //  unsigned          testIters{};     ///< RevCPU: the number of message iters for each PAN Test
+  RevOpts*              Opts{};     ///< RevCPU: Simulation options object
+  RevMem*               Mem{};      ///< RevCPU: RISC-V main memory object
+  RevLoader*            Loader{};   ///< RevCPU: RISC-V loader
+  std::vector<RevCore*> Procs{};    ///< RevCPU: RISC-V processor objects
+  bool*                 Enabled{};  ///< RevCPU: Completion structure
 
   // Initializes a RevThread object.
   // - Adds it's ThreadID to the ThreadQueue to be scheduled
@@ -266,16 +266,16 @@ class RevCPU : public SST::Component {
   // Generates a new Thread ID using the RNG.
   uint32_t GetNewThreadID() { return RevRand( 0, UINT32_MAX ); }
 
-  uint8_t  PrivTag{};  ///< RevCPU: private tag locator
-  uint32_t LToken{};   ///< RevCPU: token identifier for PAN Test
+  uint8_t PrivTag{};  ///< RevCPU: private tag locator
+  //  uint32_t LToken{};   ///< RevCPU: token identifier for PAN Test
 
   int address{};  ///< RevCPU: local network address
 
   unsigned fault_width{};  ///< RevCPU: the width (in bits) for target faults
-  int64_t  fault_range{};  ///< RevCPU: the range of cycles to inject the fault
-  int64_t  FaultCntr{};    ///< RevCPU: the fault counter
+  // int64_t  fault_range{};  ///< RevCPU: the range of cycles to inject the fault
+  int64_t FaultCntr{};  ///< RevCPU: the fault counter
 
-  uint64_t PrevAddr{};  ///< RevCPU: previous address for handling PAN messages
+  // uint64_t PrevAddr{};  ///< RevCPU: previous address for handling PAN messages
 
   bool EnableNIC{};     ///< RevCPU: Flag for enabling the NIC
   bool EnableMemH{};    ///< RevCPU: Enable memHierarchy

include/RevCore.h

@@ -37,7 +37,6 @@
 #include <vector>
 
 // -- RevCPU Headers
-#include "AllRevInstTables.h"
 #include "RevCoProc.h"
 #include "RevCorePasskey.h"
 #include "RevFeature.h"
@@ -54,20 +53,22 @@
 #include "../common/include/RevCommon.h"
 #include "../common/syscalls/syscalls.h"
 
+#include "AllRevInstTables.h"
+
 namespace SST::RevCPU {
 class RevCoProc;
 
 class RevCore {
 public:
   /// RevCore: standard constructor
   RevCore(
-    unsigned                  Id,
-    RevOpts*                  Opts,
-    unsigned                  NumHarts,
-    RevMem*                   Mem,
-    RevLoader*                Loader,
+    unsigned                  id,
+    RevOpts*                  opts,
+    unsigned                  numHarts,
+    RevMem*                   mem,
+    RevLoader*                loader,
     std::function<uint32_t()> GetNewThreadID,
-    SST::Output*              Output
+    SST::Output*              output
   );
 
   /// RevCore: standard destructor
@@ -157,7 +158,9 @@ class RevCore {
 
   RevMem& GetMem() const { return *mem; }
 
-  ///< RevCore: Called by RevCPU to handle the state changes threads may have happened during this Proc's ClockTick
+  uint64_t GetCurrentSimCycle() const { return currentSimCycle; }
+
+  ///< RevCore: Called by RevCPU to handle the state changes threads may have happened during this Core's ClockTick
   auto TransferThreadsThatChangedState() { return std::move( ThreadsThatChangedState ); }
 
   ///< RevCore: Add
@@ -171,7 +174,7 @@ class RevCore {
   ///< RevCore: Returns the current HartToExecID active pid
   uint32_t GetActiveThreadID() { return Harts.at( HartToDecodeID )->GetAssignedThreadID(); }
 
-  ///< RevCore: Get this Proc's feature
+  ///< RevCore: Get this Core's feature
   RevFeature* GetRevFeature() const { return feature; }
 
   ///< RevCore: Mark a current request as complete
@@ -257,7 +260,7 @@ class RevCore {
   ///< RevCore: Returns the id of an idle hart (or _INVALID_HART_ID_ if none are idle)
   unsigned FindIdleHartID() const;
 
-  ///< RevCore: Returns true if all harts are available (ie. There is nothing executing on this Proc)
+  ///< RevCore: Returns true if all harts are available (ie. There is nothing executing on this Core)
   bool HasNoBusyHarts() const { return IdleHarts == ValidHarts; }
 
   ///< RevCore: Used by RevCPU to determine if it can disable this proc
@@ -268,6 +271,9 @@ class RevCore {
   ///< RevCore: Returns true if there are any IdleHarts
   bool HasIdleHart() const { return IdleHarts.any(); }
 
+  ///< RevCore: Returns the number of cycles executed so far
+  uint64_t GetCycles() const { return cycles; }
+
 private:
   bool           Halted      = false;  ///< RevCore: determines if the core is halted
   bool           Stalled     = false;  ///< RevCore: determines if the core is stalled on instruction fetch
@@ -276,9 +282,10 @@ class RevCore {
   bool           ALUFault    = false;  ///< RevCore: determines if we need to handle an ALU fault
   unsigned       fault_width = 0;      ///< RevCore: the width of the target fault
   unsigned const id;                   ///< RevCore: processor id
-  uint64_t       ExecPC         = 0;   ///< RevCore: executing PC
-  unsigned       HartToDecodeID = 0;   ///< RevCore: Current executing ThreadID
-  unsigned       HartToExecID   = 0;   ///< RevCore: Thread to dispatch instruction
+  uint64_t       ExecPC          = 0;  ///< RevCore: executing PC
+  unsigned       HartToDecodeID  = 0;  ///< RevCore: Current executing ThreadID
+  unsigned       HartToExecID    = 0;  ///< RevCore: Thread to dispatch instruction
+  uint64_t       currentSimCycle = 0;  ///< RevCore: Current simulation cycle
 
   std::vector<std::shared_ptr<RevHart>> Harts{};                ///< RevCore: vector of Harts without a thread assigned to them
   std::bitset<_MAX_HARTS_>              IdleHarts{};            ///< RevCore: bitset of Harts with no thread assigned
@@ -293,7 +300,7 @@ class RevCore {
   RevLoader* loader{};    ///< RevCore: loader object
 
   // Function pointer to the GetNewThreadID function in RevCPU (monotonically increasing thread ID counter)
-  std::function<uint32_t()> GetNewThreadID;
+  std::function<uint32_t()> const GetNewThreadID;
 
   // If a given assigned thread experiences a change of state, it sets the corresponding bit
   std::vector<std::unique_ptr<RevThread>>
@@ -316,6 +323,8 @@ class RevCore {
 
   std::bitset<_MAX_HARTS_> CoProcStallReq{};
 
+  uint64_t cycles{};  ///< RevCore: The number of cycles executed
+
   ///< RevCore: Utility function for system calls that involve reading a string from memory
   EcallStatus EcallLoadAndParseString( uint64_t straddr, std::function<void()> );
 

include/RevExt.h

@@ -17,6 +17,7 @@
 // -- Standard Headers
 #include <cmath>
 #include <string>
+#include <type_traits>
 #include <utility>
 #include <vector>
 
@@ -34,7 +35,13 @@ struct RevExt {
     : name( name ), feature( feature ), mem( mem ), output( output ) {}
 
   /// RevExt: standard destructor. virtual so that Extensions[i] can be deleted
-  virtual ~RevExt() = default;
+  virtual ~RevExt()                  = default;
+
+  // We do not allow copying, moving or assigning
+  RevExt( const RevExt& )            = delete;
+  RevExt( RevExt&& )                 = delete;
+  RevExt& operator=( const RevExt& ) = delete;
+  RevExt& operator=( RevExt&& )      = delete;
 
   /// RevExt: sets the internal instruction table
   // Note: && means the argument should be an rvalue or std::move(lvalue)
@@ -72,8 +79,8 @@ struct RevExt {
   std::vector<RevInstEntry> ctable{};  ///< RevExt: compressed instruction table
   std::vector<RevInstEntry> otable{};  ///< RevExt: optional compressed instruction table
 
-  auto SetFPEnv( unsigned Inst, const RevInst& Payload, uint16_t threadID, RevRegFile* regFile );
 };  // class RevExt
+
 }  // namespace SST::RevCPU
 
 #endif

include/RevFenv.h

@@ -11,69 +11,103 @@
 #ifndef _REV_FENV_H_
 #define _REV_FENV_H_
 
+#include "RevInstTable.h"
 #include <cfenv>
-#include <memory>
+#include <cmath>
+#include <stdexcept>
 
 // GCC and Clang do not fully support FENV_ACCESS now. See:
 //
+// https://bugs.llvm.org/show_bug.cgi?id=8100
 // https://gcc.gnu.org/legacy-ml/gcc-patches/2003-09/msg00104.html
 // https://gcc.gcc.gnu.narkive.com/hDi1eOot/setting-frounding-math-by-default
-// https://bugs.llvm.org/show_bug.cgi?id=8100
-// https://github.com/llvm/llvm-project/issues/8472
 // https://discourse.llvm.org/t/why-is-pragma-stdc-fenv-access-not-supported/46128/25
 //
 // Currently FP_MODE_FLAG in CMakeLists.txt is used as a workaround
 //#pragma STDC FENV_ACCESS ON
 
 namespace SST::RevCPU {
 
-// TODO: Right now we only need to save/restore rounding mode.
-// Later, we may need to save and restore the entire fenv_t state
 class RevFenv {
-  int saved_round;  ///< Saved Floating-Point Rounding Mode
-
-  // We use Meyers singleton to avoid initialization order fiasco
-  static int& round() {
-    thread_local int round = fegetround();
-    return round;
-  }
+  FCSR&       fcsr;         // Reference to this register file's FCSR
+  std::fenv_t saved_env{};  // The saved FP environment which is restored
 
 public:
-  /// Constructor saves Fenv state
-  RevFenv() : saved_round( round() ) {
-    if( saved_round < 0 ) {
-      throw std::runtime_error( "Getting floating-point rounding mode with "
-                                "fegetround() is not working." );
+  /// Constructor saves Fenv state to be restored at destruction
+  RevFenv( RevRegFile* R, FRMode rm, SST::Output* output ) : fcsr( R->GetFCSR() ) {
+
+    // Save host's FP environment and set flags to default, non-trapping
+    if( std::feholdexcept( &saved_env ) ) {
+      throw std::runtime_error( "Getting floating-point environment with feholdexcept() is not working." );
+    }
+
+    // If the encoded rounding mode is dynamic, load the frm register
+    if( rm == FRMode::DYN ) {
+      rm = R->GetFRM();
+    }
+
+    // Set the Floating-Point Rounding Mode on the host
+    int ret = 0;
+    switch( rm ) {
+    case FRMode::RNE:  // Round to Nearest, ties to Even
+      ret = std::fesetround( FE_TONEAREST );
+      break;
+
+    case FRMode::RTZ:  // Round towards Zero
+      ret = std::fesetround( FE_TOWARDZERO );
+      break;
+
+    case FRMode::RDN:  // Round Down (towards -Inf)
+      ret = std::fesetround( FE_DOWNWARD );
+      break;
+
+    case FRMode::RUP:  // Round Up (towards +Inf)
+      ret = std::fesetround( FE_UPWARD );
+      break;
+
+    case FRMode::RMM:  // Round to Nearest, ties to Max Magnitude
+#ifdef FE_TONEARESTFROMZERO
+      ret = std::fesetround( FE_TONEARESTFROMZERO );
+#else
+      output->fatal( CALL_INFO, -1, "Error: Round to nearest Max Magnitude not implemented at PC = 0x%" PRIx64 "\n", R->GetPC() );
+#endif
+      break;
+
+    case FRMode::DYN:
+      output->fatal( CALL_INFO, -1, "Illegal FCSR Rounding Mode of DYN at PC = 0x%" PRIx64 "\n", R->GetPC() );
+      break;
+
+    default: output->fatal( CALL_INFO, -1, "Unknown Rounding Mode at PC = 0x%" PRIx64 "\n", R->GetPC() ); break;
+    }
+    if( ret != 0 ) {
+      output->fatal( CALL_INFO, -1, "Could not set FP rounding mode at PC = 0x%" PRIx64 "\n", R->GetPC() );
     }
   }
 
-  /// Destructor restores Fenv state
-  ~RevFenv() { SetRound( saved_round ); }
+  /// Destructor sets FP exception flags and restores host FP Environment
+  ~RevFenv() {
+    // RISC-V does not support FP traps
+    // Set the accumulated fflags based on exceptions
+    int except = std::fetestexcept( FE_ALL_EXCEPT );
+    if( except & FE_DIVBYZERO )
+      fcsr = FCSR{ static_cast<uint32_t>( fcsr ) | static_cast<uint32_t>( FCSR::DZ ) };
+    if( except & FE_INEXACT )
+      fcsr = FCSR{ static_cast<uint32_t>( fcsr ) | static_cast<uint32_t>( FCSR::NX ) };
+    if( except & FE_INVALID )
+      fcsr = FCSR{ static_cast<uint32_t>( fcsr ) | static_cast<uint32_t>( FCSR::NV ) };
+    if( except & FE_OVERFLOW )
+      fcsr = FCSR{ static_cast<uint32_t>( fcsr ) | static_cast<uint32_t>( FCSR::OF ) };
+    if( except & FE_UNDERFLOW )
+      fcsr = FCSR{ static_cast<uint32_t>( fcsr ) | static_cast<uint32_t>( FCSR::UF ) };
 
-  // We allow moving, but not copying RevFenv
-  // This is to ensure that there is only a single copy
-  // of the saved state at a time, similar to std::unique_ptr
+    // Restore the host's saved FP Environment
+    std::fesetenv( &saved_env );
+  }
+
+  // We allow moving, but not copying or assigning RevFenv.
   RevFenv( RevFenv&& )                 = default;
   RevFenv( const RevFenv& )            = delete;
-
-  // We disallow assigning
   RevFenv& operator=( const RevFenv& ) = delete;
-  RevFenv& operator=( RevFenv&& )      = delete;
-
-  // Get the current FP rounding state
-  static int GetRound() { return round(); }
-
-  // Set the FP rounding state if it differs from current
-  static int SetRound( int mode ) {
-    int rc = 0;
-    if( mode != round() ) {
-      rc = fesetround( mode );
-      if( rc == 0 ) {
-        round() = mode;
-      }
-    }
-    return rc;
-  }
 };  // RevFenv
 
 }  // namespace SST::RevCPU

include/RevHart.h

@@ -59,7 +59,7 @@ class RevHart {
   uint16_t GetID() const { return ID; }
 
   ///< RevHart: Returns the ID of the assigned thread
-  uint32_t GetAssignedThreadID() const { return ( Thread != nullptr ) ? Thread->GetID() : _INVALID_TID_; }
+  uint32_t GetAssignedThreadID() const { return Thread ? Thread->GetID() : _INVALID_TID_; }
 
   ///< RevHart: Load the register file from the RevThread
   void LoadRegFile( std::unique_ptr<RevRegFile> regFile ) {