From 54d4692d88354e23903e2832765f9bb11756e516 Mon Sep 17 00:00:00 2001
From: leekillough <15950023+leekillough@users.noreply.github.com>
Date: Wed, 17 Jul 2024 16:43:39 -0500
Subject: [PATCH] Zicond extension

---
 include/AllRevInstTables.h |  1 +
 include/RevFeature.h       | 13 ++++----
 include/insns/Zicond.h     | 68 ++++++++++++++++++++++++++++++++++++++
 src/RevCore.cc             |  5 +++
 src/RevFeature.cc          |  1 +
 5 files changed, 82 insertions(+), 6 deletions(-)
 create mode 100644 include/insns/Zicond.h

diff --git a/include/AllRevInstTables.h b/include/AllRevInstTables.h
index 85aba0b1b..51ba22d90 100644
--- a/include/AllRevInstTables.h
+++ b/include/AllRevInstTables.h
@@ -32,6 +32,7 @@
 #include "insns/RV64P.h"
 #include "insns/Zfa.h"
 #include "insns/Zicbom.h"
+#include "insns/Zicond.h"
 #include "insns/Zicsr.h"
 #include "insns/Zifencei.h"
 
diff --git a/include/RevFeature.h b/include/RevFeature.h
index 20359e47d..f103e48fa 100644
--- a/include/RevFeature.h
+++ b/include/RevFeature.h
@@ -36,12 +36,13 @@ enum RevFeatureType : uint32_t {
   RV_V        = 1 << 10,  ///< RevFeatureType: V-extension
   RV_H        = 1 << 11,  ///< RevFeatureType: H-extension
   RV_ZICBOM   = 1 << 12,  ///< RevFeatureType: Zicbom-extension
-  RV_ZICSR    = 1 << 13,  ///< RevFEatureType: Zicsr-extension
-  RV_ZIFENCEI = 1 << 14,  ///< RevFeatureType: Zifencei-extension
-  RV_ZFA      = 1 << 15,  ///< RevFeatureType: Zfa-extension
-  RV_ZFH      = 1 << 16,  ///< RevFeatureType: H-extension
-  RV_ZFHMIN   = 1 << 17,  ///< RevFeatureRtpe: Zfhmin extension
-  RV_ZTSO     = 1 << 18,  ///< RevFeatureType: Ztso-extension
+  RV_ZICOND   = 1 << 13,  ///< RevFeatureType: Zicond-extension
+  RV_ZICSR    = 1 << 14,  ///< RevFEatureType: Zicsr-extension
+  RV_ZIFENCEI = 1 << 15,  ///< RevFeatureType: Zifencei-extension
+  RV_ZFA      = 1 << 16,  ///< RevFeatureType: Zfa-extension
+  RV_ZFH      = 1 << 17,  ///< RevFeatureType: H-extension
+  RV_ZFHMIN   = 1 << 18,  ///< RevFeatureRtpe: Zfhmin extension
+  RV_ZTSO     = 1 << 19,  ///< RevFeatureType: Ztso-extension
 };
 
 class RevFeature {
diff --git a/include/insns/Zicond.h b/include/insns/Zicond.h
new file mode 100644
index 000000000..32dee76e2
--- /dev/null
+++ b/include/insns/Zicond.h
@@ -0,0 +1,68 @@
+//
+// _Zicond_h_
+//
+// Copyright (C) 2017-2024 Tactical Computing Laboratories, LLC
+// All Rights Reserved
+// contact@tactcomplabs.com
+//
+// See LICENSE in the top level directory for licensing details
+//
+
+#ifndef _SST_REVCPU_ZICOND_H_
+#define _SST_REVCPU_ZICOND_H_
+
+#include "../RevExt.h"
+#include "../RevInstHelpers.h"
+
+namespace SST::RevCPU {
+
+class Zicond : public RevExt {
+
+  template<template<typename> class CMP>
+  static bool czero( RevFeature* F, RevRegFile* R, RevMem* M, const RevInst& Inst ) {
+    if( R->IsRV32 ) {
+      R->SetX( Inst.rd, CMP()( R->GetX<uint32_t>( Inst.rs2 ), 0 ) ? 0 : R->GetX<uint32_t>( Inst.rs1 ) );
+    } else {
+      R->SetX( Inst.rd, CMP()( R->GetX<uint64_t>( Inst.rs2 ), 0 ) ? 0 : R->GetX<uint64_t>( Inst.rs1 ) );
+    }
+    R->AdvancePC( Inst );
+    return true;
+  }
+
+  static constexpr auto& czero_eqz = czero<std::equal_to>;
+  static constexpr auto& czero_nez = czero<std::not_equal_to>;
+
+  // ----------------------------------------------------------------------
+  //
+  // RISC-V Zicond Instructions
+  //
+  // ----------------------------------------------------------------------
+  struct RevZicondInstDefaults : RevInstDefaults {
+    RevZicondInstDefaults() {
+      SetOpcode( 0b0110011 );
+      SetFunct2or7( 0b0000111 );
+    }
+  };
+
+  /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+  // Single-Precision Instructions
+  /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+  // clang-format off
+  std::vector<RevInstEntry> ZicondTable = {
+    RevZicondInstDefaults().SetMnemonic( "czero.eqz %rd, %rs1, %rs2" ).SetFunct3( 0b101 ).SetImplFunc( czero_eqz ),
+    RevZicondInstDefaults().SetMnemonic( "czero.nez %rd, %rs1, %rs2" ).SetFunct3( 0b111 ).SetImplFunc( czero_nez ),
+  };
+
+  // clang-format on
+
+public:
+  /// Zicond: standard constructor
+  Zicond( RevFeature* Feature, RevMem* RevMem, SST::Output* Output ) : RevExt( "Zicond", Feature, RevMem, Output ) {
+    SetTable( std::move( ZicondTable ) );
+  }
+};  // end class Zicond
+
+}  // namespace SST::RevCPU
+
+#endif
diff --git a/src/RevCore.cc b/src/RevCore.cc
index 279ab8c42..35b2f0f1f 100644
--- a/src/RevCore.cc
+++ b/src/RevCore.cc
@@ -197,6 +197,11 @@ bool RevCore::SeedInstTable() {
     EnableExt( new Zicbom( feature, mem, output ) );
   }
 
+  // Zicond Extension
+  if( feature->IsModeEnabled( RV_ZICOND ) ) {
+    EnableExt( new Zicond( feature, mem, output ) );
+  }
+
   // Zicsr Extension
   if( feature->IsModeEnabled( RV_ZICSR ) ) {
     EnableExt( new Zicsr( feature, mem, output ) );
diff --git a/src/RevFeature.cc b/src/RevFeature.cc
index af20e8779..43850e2f0 100644
--- a/src/RevFeature.cc
+++ b/src/RevFeature.cc
@@ -69,6 +69,7 @@ bool RevFeature::ParseMachineModel() {
     { "V",          1, 0, -1, 0, RV_V | RV_D | RV_F | RV_ZICSR                             },
     { "H",          1, 0, -1, 0, RV_H                                                      }, // Unsupported
     { "Zicbom",     1, 0,  1, 1, RV_ZICBOM                                                 },
+    { "Zicond",     1, 0,  1, 1, RV_ZICOND                                                 },
     { "Zicsr",      2, 0,  2, 2, RV_ZICSR                                                  },
     { "Zifencei",   2, 0,  2, 2, RV_ZIFENCEI                                               },
     { "Zfa",        1, 0,  1, 1, RV_ZFA | RV_F | RV_ZICSR                                  }, // Unsupported